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Part Manufacturer Description Datasheet BUY
SN74LS107ANSR Texas Instruments Dual J-K Flip-Flops With Clear 14-SO 0 to 70 visit Texas Instruments
SN74LS107ADRE4 Texas Instruments Dual J-K Flip-Flops With Clear 14-SOIC 0 to 70 visit Texas Instruments
SN74LS107AD Texas Instruments Dual J-K Flip-Flops With Clear 14-SOIC 0 to 70 visit Texas Instruments
SN74LS107ANSRE4 Texas Instruments LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN, PLASTIC, SOP-14 visit Texas Instruments
SN74LS107ADR Texas Instruments Dual J-K Flip-Flops With Clear 14-SOIC 0 to 70 visit Texas Instruments
SN74LS107ADG4 Texas Instruments Dual J-K Flip-Flops With Clear 14-SOIC 0 to 70 visit Texas Instruments

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74LS107 Datasheet

Part Manufacturer Description PDF Type
74LS107 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan
74LS107 Raytheon Dual J-K Negative-Edge-Triggered Flip-Flops Scan
74LS107 Signetics Dual J-K Flip-Flop Scan
74LS107 Signetics Dual J-K Flip-Flop Scan
74LS107 Signetics Integrated Circuits Catalogue 1978/79 Scan
74LS107DC Fairchild Semiconductor Dual J-K Flip-Flop Scan
74LS107FC Fairchild Semiconductor Dual J-K Flip-Flop Scan
74LS107M N/A TTL Data Book 1980 Scan
74LS107PC Fairchild Semiconductor Dual J-K Flip-Flop Scan

74LS107

Catalog Datasheet MFG & Type PDF Document Tags

pin configuration 74LS107

Abstract: 74LS107 stable while the Clock is HIGH for conventional oper ation. The 74LS107 is a negative edge-trig gered , output LOW and HIGH. asynchronous LOW, it over inputs, forcing the , inputs of the 74107 must be stable while the Clock is HIG H for conventional operation. The 74LS107 is , all outputs open, Ice is measured with the O and (5 outputs HIGH in turn. 74LS107 UNIT Max Min 2.7
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OCR Scan
LS107 pin configuration 74LS107 LS-107 74107 AN ttl 74107 74107 pin configuration N74107N N74LS107N N74LS107D 1N916 1N3064

CI 7474

Abstract: CI 7473 o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J , /74LS76 J,K "L X X 60 12 20 D58 4L,6B,9B 7 Dual JK 54LS/74LS107 J,K "L â'" X 60 12 20 D57a 3I,6A,9A 8
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OCR Scan
CI 7474 CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 54S/74S109 54LS/74LS109 54H/74H74 54S/74S74 54LS/74LS74 54LS/74LS107

74107 pin diagram

Abstract: CI 74107 stable while the Clock is HIGH for conventional operation. The 74LS107 is a negative edge-triggered , CURRENT (TOTAL) 74107 20MHz 20mA 74LS107 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5 , must be stable while the Clock is HIGH for conventional operation. 2. The 74LS107 is edge-triggered , 0.2 Max 74LS107 Min 0.4 -1.5 1.0 -18 40 80 80 2.7 Typ2 Max UNIT 3.4 0.35 0.25 -1.6
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OCR Scan
74107 pin diagram 2RD22 74107 74LS N74107

IC 74107

Abstract: IC 74LS107 over inputs, forcing the Q output NOTE: TYPE 74107 74LS107 TYPICAL f MAX 20MHz 45MHz TYPICAL , stable while the Clock is HIGH for conventional operation. The 74LS107 is edge-triggered. Data must be , ma 74LS107 UNIT V qh HIGH-level output voltage Vcc = MIN, V|H = MIN, V|L = MAX, Ioh = MAX
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OCR Scan
IC 74107 IC 74LS107

74107 pin diagram

Abstract: 74LS107 operation. The 74LS107 Is a negative edge-triggered flip-flop. The J and K inputs must be stable one set-up , . The 74LS107 is edge-triggered. Data must be stable one set-up time prior to the negative edge of the , operating free-air temperature range unless otherwise noted.) PARAMETER TEST CONDITIONS1 74107 74LS107
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OCR Scan
74107 flip flop LS 107

logic ic 7476 pin diagram

Abstract: logic ic 74LS76 pin diagram /74109 54LS/74LS114 54LS/74LS107 c_ >; r 1 54S/74S114 DEVICE NO. c_ c_ c_ c , 54/7473, 54H/74H73, 54LS/74LS73 *54/74107, ` 54LS/74LS107 14 - J 1 - 0 CP 3- K Q -1 2 2- J 5 -0 CP
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OCR Scan
logic ic 7476 pin diagram logic ic 74LS76 pin diagram ic 74109 74109 dual JK 74LS109 IC 74196 54LS/74LS77 54LS/74LS75 54LS/74LS197 93L14 54LS/74LS196 54LS/74LS279

74LS183

Abstract: 74LS275 CM O S/BiCM O S Gate Array LZ93/LZ95/LZ96/LZ97 Series 74LS Series Macro Cell Libraries (LZ93/LZ95/LZ96/LZ97 Series) Model No. 74LS00 74LS02 74LS04 74LS08 74LS10 74LS11 74LS20 74LS21 74LS27 74LS28 74LS30 74LS32 74LS37 74LS40 74LS42 7443 7444 74LS48 Model No. 74LS51 74LS54 74LS55 74LS73 74LS74 74LS75 74LS76 7447 74LS78 74LS83 74LS85 74LS86 74LS90 74LS91 74LS92 74LS93 74LS95 74LS97 Model No. 74LS107 74LS109 74LS112 74LS113 74LS114 74LS125 74LS126 74LS137 74LS138 74LS139 74LS147 74LS148 74LS151
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OCR Scan
74LS152 74LS183 74LS248 74LS258 74LS275 74LS356 74ls series 74LS396 7447 74LS153 74LS155 74LS157 74LS158 74LS160A

TTL 74ls74

Abstract: 7474 14 PIN o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J
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OCR Scan
TTL 74ls74 7474 14 PIN 7476 ttl ttl 74ls109 TTL 74ls76 54H/74H103 54H/74H76 54LS/74LS76

74LS107

Abstract: pin-out com patible w ith LS · TTL (74LS107) and uses silicon gate process technology to achieve operating speeds and drivability sim ilar to LS · TTL (74LS107). · All inputs are protected from dam age. A b s o
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OCR Scan
MLC74HC107

7475 D latch

Abstract: D146 60 12 20 D58 4L,6B,9B 7 Dual JK 54LS/74LS107 J,K "L â'" X 60 12 20 D57a 3I,6A,9A 8 Dual JK 54LS
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OCR Scan
7475 D latch D146 D147 ci 7475 rs latch 7475 data latch 54LS/74LS541 54LS/74LS78 54LS/74LS168 54LS/74LS169 54LS/74LS490 54LS/74LS373

IC 74LS107

Abstract: 74LS107 TC74HC107AP/AF CMOS TC74HC107AP,TC74HC107AF Dual J-K Flip-Flop with Clear TC74HC107A CMOS CMOS JK CMOS LSTTL J K "L" · TC74HC107AP : fmax = 75 MHz () (VCC = 5 V) · : ICC = 2 A () (Ta = 25°C) · : VNIH = VNIL = 28% VCC () · : LSTTL 10 · TC74HC107AF · : |IOH| = IOL = 4 mA () : tpLH - tpHL · · LSTTL (74LS107) : VCC (opr) = 2~6 V DIP14-P-300-2.54 : 0.96 g () SOP14-P-300-1.27A : 0.18
Toshiba
Original

IC 74107

Abstract: LS-107 e r inp u ts, fo rcin g th e O o u tp u t NOTE: TYPE 74107 74LS107 TYPICAL fMAX 20MHz 45MHz , -3 .2 -1 8 -5 7 40 re c o m m e n d e d o p e ra tin g c o n d itio n s fo r th e 74LS107 UNIT
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OCR Scan

d146

Abstract: RS latch Dual JK 54LS/74LS107 J,K "L â'" X 60 12 20 D57a 3I,6A,9A 8 Dual JK 54LS/74LS78 J.K S X X 45 16 20 D82
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OCR Scan
CI 74196 fairchild 9314 74LS76 logic diagram 74ls112 pin diagram 74196 TTL 74279 54H/74H78 54H/74H106 54S/74S112 54LS/74LS112 54H/74H108 54S/74S113

74107PC

Abstract: 74ls107 = +5.0 V ±5%, Ta = 0°C to +125°C 74107PC, 74LS107PC 74107DC, 74LS107DC 74107FC, 74LS107FC , 107 54/74107 '54LS/74LS107 e> DUAL JK FLIP-FLOP (With Separate Clears and Clocks) DESCRIPTIONâ'"The '107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows
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OCR Scan
54LS107DM 54107DM 54107FM cpn0 54LS107 54/74LS CLS107

74107PC

Abstract: 74LS107n = 0 °C to +125°C 74107PC, 74LS107PC 74107DC, 74LS107DC 74107FC, 74LS107FC 54107DM, 54LS107DM 54107FM , 107 54/74107 O ' 54LS/74LS107^ n o r D UAL JK FLIP-FLO P (With Separate Clears and Clocks) DESCRIPTION - T he '107 dual J K master/slave flip-flops have a separate clo ck for each flip-flop. Inputs to the master section are controlled by the clo ck pulse. The clo ck pulse also regulates the state of the co upling transi stors w hich connect the master and slave sections. The sequence of opera tion is
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OCR Scan
74LS107n S4/74LS

ci 7475

Abstract: D147 D58 4L,6B,9B 7 Dual JK 54LS/74LS107 J,K "L â'" X 60 12 20 D57a 3I,6A,9A 8 Dual JK 54LS/74LS78 J.K S
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OCR Scan
74L576 TTL 7475 pin diagram 7475 74109 74LS279 7475 FAIRCHILD 93L08 54S/74S175 54LS/74LS175 54S/74S174 54LS/74LS174 93L38

TTL 74ls74

Abstract: 74ls74 o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J
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OCR Scan
7476 JK TTL 7474 ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 74H71 54H/74H101 54H/74H72 54H/74H102 54LS/74LS113

CI 74LS90

Abstract: ci 74193 D58 4L,6B,9B 7 Dual JK 54LS/74LS107 J,K "L â'" X 60 12 20 D57a 3I,6A,9A 8 Dual JK 54LS/74LS78 J.K S
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OCR Scan
CI 74LS90 ci 74193 ci 74ls193 ci 7492 CI 74176 TTL 74293 54/7490A 54LS/74LS90 S4/74293 54LS/74LS293 S4/7493A 54LS/74LS93

IC 7408

Abstract: IC 7812 74S38 1820-1453 STTL IC 74S163 1820-1469 LSTTL IC 74LS107 1820-1470 LSTTL IC
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Original
IC 7408 IC 7812 REGULATOR IC 7812 IC TTL 7400 NEC d446c d446c HP1350 82S126 1818-0373B MK34127N D446C-2 HP9836

of 74HC107 ic

Abstract: 74hc107 I T/ SGS-mOMSON RÃ"lD(g[S®IIL[i(gTns®R!lD(gi M54HC107 M74HC107 DUAL J-K FLIP FLOP WITH CLEAR i HIGH SPEED 'max = 58 MHz (TYP.) at VCc= 5V i LOW POWER DISSIPATION Ice = 2 iiA (MAX.) at TA = 25°C i HIGH NOISE IMMUNITY Vnih = VN|L = 28% Vcc (MIN.) i OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS i SYMMETRICAL OUTPUT IMPEDANCE I'OHi = lOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tpHL WIDE OPERATING VOLTAGE RANGE Vcc (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54/74LS107 DESCRIPTION The M54
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OCR Scan
M74HC107B1N of 74HC107 ic 74hc107 M74HC107B1 54HC 74HC 54/74LS107 M54/74HC107

Bt218

Abstract: 74LS107 * 74LS107 K Q MISSING CODE +5V 0.1 (O)AB (O)A=B 1M J 74LS32 CLR* Q* 74LS107 K VIN OF BT218 1M Q + MAX452 0.1 AC Characterization Signal-to-noise ratio can be
Rockwell Semiconductor Systems
Original
74F269 pin configuration 74LS04 RS-170A RS-343 internal circuitry of 74LS85 74ls04 not DVIDAN13B 218EVM BT218DIP

74LS107* pin and application

Abstract: CLR* Q * 74LS107 Q K â'¢ MISSING CODE +5V (0)AB (0)A=B 1M J & > K 7-20 CLR* -W 74LS107 1M Q A V - VIN OF BT208
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OCR Scan
74LS107* pin and application RS-170 RS-343A 208KP 18MSPS 208KPJ BT206

BT253

Abstract: BT254 )A
Rockwell Semiconductor Systems
Original
BT254 BT253 74F373 74LS32 TTL DVIDAN15B 254KPJ

BT251

Abstract: BT252 * 74LS107 K Q MISSING CODE +5V 0.1 (O)AB (O)A=B 1M J 74LS32 CLR* Q* 74LS107 K VIN OF BT252 1M Q + MAX452 0.1 AC Characterization Signal­to­noise ratio can be
Rockwell Semiconductor Systems
Original
BT251 Bt252EVM BT252KPJ DVIDAN14B 252KPJ
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