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SN74LS04DBR Texas Instruments Hex inverters 14-SSOP visit Texas Instruments Buy
SN74LS04NSR Texas Instruments Hex inverters 14-SO 0 to 70 visit Texas Instruments Buy
SN74LS04NSRG4 Texas Instruments Hex inverters 14-SO 0 to 70 visit Texas Instruments
SN74LS04N Texas Instruments Hex inverters 14-PDIP 0 to 70 visit Texas Instruments Buy
SN74LS04J-00 Texas Instruments LS SERIES, HEX 1-INPUT INVERT GATE, CDIP14 visit Texas Instruments
SN74LS04NE4 Texas Instruments Hex inverters 14-PDIP 0 to 70 visit Texas Instruments

74LS04 Hex Inverter definition

Catalog Datasheet MFG & Type PDF Document Tags

not 7404

Abstract: ls 7404 Signetics 7404, LS04, S04 Inverters Hex Inverter Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7404 10ns 12mA 74LS04 9.5ns 2.4mA 74S04 3ns 22mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; Ta = 0°C to +70°C Plastic DIP N7404N , for 74LS; VM - 1.5V for all other TTL families. Input Pulse Definition FAMILY INPUT PULSE , .) PARAMETER TEST CONDITIONS1 7404 74LS04 74S04 UNIT Min Typ2 Max Min Typ2 Max Min Typ2 Max v
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not 7404 ls 7404 7404 pin configuration 74LS04 Hex Inverter definition 7404 ttl inverter with propagation delay 6ns 7404 N74LS04N N74S04N N74LS04D N74S04D

7404

Abstract: 7404 pin configuration Signetics Logic Products 7404, LS04, S04 Inverters Hex Inverter Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7404 10ns 12mA 74LS04 9.5ns 2.4mA 74S04 3ns 22mA ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = 5V+5%; TA = OX to +70°C Plastic DIP N7404N , be less than or equal to the table entries. input Pulse Definition FAMILY INPUT PULSE REQUIREMENTS , CONDITIONS1 7404 74LS04 74S04 UNIT Min Typ2 Max Min Typ2 Max Min Typ2 Max HIGH-level OH output
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74LS04 fan-out 7404 inverter pin configuration TTL 7404 7404 TTL 7404 ttl inverter 74LS 7404

74LS04

Abstract: 74ls04 dip is manufactured using a commercially available hex inverter DIP (e.g., 74LS04) with a small PC board , delays differ from hybrid devices? A typical hybrid consists of a hex inverter DIP, a PC board acting as , -inch wafers by Dallas Semiconductor's Class 1 facility. Using lasers for late definition of finished wafers , variations of the 74LS04 devices procured from other manufacturers. On silicon delay lines, Page 6 of 11
Maxim Integrated Products
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DS1100 DS1135 DS1110 74ls04 dip ttl cmos advantages disadvantages DS-1100 TTL 74ls04 data Appnote14 DS1005 APP14

74LS04

Abstract: 74ls04 dip and its silicon counterpart. A hybrid is manufactured using a commercially available hex inverter DIP (e.g., 74LS04) with a small PC board placed on top to supply a ground plane. Next, several leads are , hybrid consists of a hex inverter DIP, a PC board acting as a ground plane plus chip capacitors, a , facility. Using lasers for late definition of finished wafers provides both economy and maximum , variations of the 74LS04 devices procured from other manufacturers. On silicon delay lines, temperature
Dallas Semiconductor
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DS1000-IND DS1007 specification of IC 74ls04 20-PIC DS1000 DS1010

74ls04 dip

Abstract: 74LS04 delay line and its silicon counterpart. A hybrid is manufactured using a commercially available hex inverter DIP (e.g., 74LS04) with a small PC board placed on top to supply a ground plane. Next, several , hex inverter DIP, a PC board acting as a ground plane plus chip capacitors, a terminating resistor , fabricated on six­inch wafers by Dallas Semiconductor's Class 1 facility. Using lasers for late definition , comes at a premium price. Furthermore, timing is subject to the variations of the 74LS04 devices
Dallas Semiconductor
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DS1013 DS1044 13 tap inductor NOT gate 74LS04 inductor STC

DS-1100

Abstract: 74ls04 dip manufactured using a commercially available hex inverter DIP (e.g., 74LS04) with a small PC board placed on , hex inverter DIP, a PC board acting as a ground plane plus chip capacitors, a terminating resistor , -inch wafers by Dallas Semiconductor?s Class 1 facility. Using lasers for late definition of finished wafers , variations of the 74LS04 devices procured from other manufacturers. On silicon delay lines, temperature
Dallas Semiconductor
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DS-1135 74LS04 NOT gate IC data sheet 74LS04 polysilicon fuse sample 74LS04

PWm matlab source code

Abstract: Park transformation 74LS04 hex inverting buffer, and some passive components. The user connections to the board are made via , the external digital I/O connector. The ADMC200/ ADMC201 PWM outputs are buffered using a 74LS04 hex inverter to give active high PWM signals at the connector. Other signal formats can be obtained by using a , signals are buffered by a 74LS04 HEX buffer IC and brought to the 8-way terminal block. If active low signals are required, direct from the ADMC200, this inverter IC can be bypassed. The buffer can be
Analog Devices
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ADDS-2101-EZ-LAB PWm matlab source code Park transformation 74LS04 Hex Inverter Gate function table clarke transformation pin configuration and description OF IC 74ls04 AN-407 ADMC200-EVAL ADMC21 ADSP-2105 ADMC200/ADMC201

MXO-55GA-2C

Abstract: PLCCB-44-PS-T , Mfg. No. 35 3 10125 ECL-TTL Translator U2 - U4 MC10125P, Motorola 36 1 74LS04 Hex Inverter U25 SN74LS04N, Texas Instruments or equivalent 37 1 74F08 Quad 2 , DIGITAL VIDEO ENCODER PXCK E2 S-VIDEO OUTPUT TMC2490 PROGRAMMER TMC22091 HEX SWITCH FOR , , as in the TMC2490, improves the horizontal color definition. The TRS decoder extracts the field (F , 1 74F174 Hex D-type FF U17 MC74F174AN, Motorola or equivalent 42 2 74LS244 Octal
Raytheon
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MXO-55GA-2C PLCCB-44-PS-T CCIR-656-format CTS MXO-55GA-2C rotary encoder schematic 74ls74 pin configuration TMC2063 CCIR-656- TMC2063P7C CCIR-601 DS70002063

CCIR-656-format

Abstract: MXO-55GA-2C Translator U2 - U4 MC10125P, Motorola 36 1 74LS04 Hex Inverter U25 SN74LS04N, Texas , DIGITAL VIDEO ENCODER PXCK E2 S-VIDEO OUTPUT TMC2490 PROGRAMMER TMC22091 HEX SWITCH FOR , , as in the TMC2490, improves the horizontal color definition. The TRS decoder extracts the field (F , , U10, U11 MC74LS163AN, Motorola or equivalent 41 1 74F174 Hex D-type FF U17 , S2 TP11FG-RA-0, Alco Switch 61 1 HEX rotary switch S1 350134GSV, EECO 62 1
Fairchild Semiconductor
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ICA203STG ICA-286-S-TG 74LS05 inverter MC74LS74 5 pin sip resistor 4.7k r3175
Abstract: clock drivers Power inverter Others 20 10 < Example> Clock skew Vfhen a large fan out is , shown in the table. Pre-driver Max. simultaneous transition Inverter/NAND 12 2 input NOR 16 3 input NOR 18 In example 1, inverter pre-drivers are used. In this case , required, an inverter should be added i.e. as shown in example 2. FD CK + Q & "Iâ' . "0" [>o , "1" causes a glitch due to the delay at inverter. Consequently, switching at A=B=0 is required -
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G01341Q 4TLS03 0G13411 HD14508B HD14510B HD14512B

8272 floppy disk controller

Abstract: intel floppy disk controller 8272 designs this would be 3F0 Hex to 3F7 Hex A2 A1 A0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 , when the LOCK bit is set to ``0'' (see section 5 3 2 for LOCK bit definition) Once set it remains set , is set to ``0'' (See section 5 3 2 for the definition of the LOCK bit) This maintains PC-AT , (See section 5 3 2 for the definition of the LOCK bit) The DSR Reset clears itself automatically , automatically enters the next phase as defined by the command definition The FIFO is disabled during the
Intel
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8272 floppy disk controller intel floppy disk controller 8272 block diagram of 8272 floppy disk controller 8272A 8272A floppy disk controller block diagram floppy disk controller 8272 82077AA 82077AA-5 82077AA-1

Amdasm

Abstract: AM9080A Gate 2 74LS02 Quad Two-Input NOR Gate 1 74LS04 Hex Inverter 2 74LS21 Dual Four-Input AND Gate 1 Total , Control Path U5161, U121 Am25LS374 CP-»-Y 22 37 11.5 17 Note 1 U62 74LS04 In -> Out 10 15 not , -»â'¢ Y 22 37 11.5 17 U65, U66 Am25LS157 S ->- Y 15 23 12 18 Note 2 U62 74LS04 In -> Out 10 15 3 5 U63 , are defined in the Definition Phase, each having a small number of variables, i.e., anywhere from two , hardware. Appendix I is the print-out of the microprogram Definition File* The listing, containing many
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Amdasm AM9080A 74ls04 hex inverter gates NS4F AM2901A am29761 9080A AMPUB-064 25LS374 U7172 U8182

74LS08 fan-in

Abstract: 74LS398 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Inverter . . . , . . . . . . . . . . . . . . . . . . . . . . Hex Inverter Schmitt Trigger . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Inverter . . . . . . . . . . . . . . . . . , Hex Inverter, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . Hex Inverter with Common Enable, 3-State . . . . . . .
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74LS08 fan-in 74LS398 74LS273 74LS181 MC74F579 74LS14 Hex Inverter definition 74LS797 SN54/74LS798 SN54/74LS848 81LS95 81LS96 81LS97

ferranti ula

Abstract: pia 6820 PC-AT or PS/2 designs, the pri­ mary and secondary address ranges are 3F0 Hex to 37F Hex and 370 Hex to 377 Hex respectively. A2 A1 AO Access Type Register 0 0 oâ'™ R Status , definition for 82077SL to be in powerdown. The bits reflecting the floppy disk drive input pins (TRKO, INDEX , to the DIR register, Hardware or Software RESET. The DRQ bit is low by definition for 82077SL to be , for LOCK bit definition). Once set, it remains set until the user clears this bit. This bit is set by
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ferranti ula pia 6820 yx 805 led driver IC CD 4440 cs pic RAM 2102 RADIO SHACK PARTS CROSS REF 0897-X S-100
Abstract: PS/2 designs, the pri mary and secondary address ranges are 3F0 Hex to 37F Hex and 370 Hex to 377 Hex , the state of the INVERT pin. The INT PENDING bit is low by definition for 82077SL to be in powerdown , RESET. The DRO bit is low by definition for 82077SL to be in powerdown. The bits reflecting the floppy , the FIFO circuits when the LOCK bit is set to " 0" (see Section 5.3.2 for LOCK bit definition). Once , into 8272A compatible mode if the LOCK bit is set to " 0" (See section 5.3.2 for the definition of the -
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386SL 82077SL-5 82077SL-1

8272 floppy disk controller

Abstract: 82077sl designs, the pri mary and secondary address ranges are 3F0 Hex to 37F Hex and 370 Hex to 377 Hex , INT PENDING bit is low by definition for 82077SL to be in powerdown. The bits reflecting the floppy , or Software RESET. The DRQ bit is low by definition for 82077SL to be in powerdown. The bits , LOCK bit definition). Once set, it remains set until the user clears this bit. This bit is set by a , 82077SL into 8272A compatible mode if the LOCK bit is set to " 0" (See section 5.3.2 for the definition
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toggle flip flop ic 82072 RKS-D2

SK 6211

Abstract: 82077sl mary and secondary address ranges are 3F0 Hex to 37F Hex and 370 Hex to 377 Hex respectively. Access , the cable and are independent of the state of the INVERT pin. The INT PENDING bit is low by definition , DIR register, Hardware or Software RESET. The DRQ bit is low by definition for 82077SL to be in , the FIFO circuits when the LOCK bit is set to " 0" (see Section 5.3.2 for LOCK bit definition). Once , 2-321 4fl2bl75 0143Qlb 7 f ll 82077SL for the definition of the LOCK bit). This maintains
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SK 6211 lds8h nec A2C Intel 82072 29041

82077sl

Abstract: SK 6211 COMPARISON REGISTER DEFINITION Figure 4 HEX VALUE BYTEO BYTE 1 BYTE 2 BYTE 4 BYTE 5 BYTE 6 BYTE 7 NOTE: The pattern recognition in Hex is C5,3A, A 3,5C, C5,3A, A 3,5C. The odds of this , 52 TIME CHIP REGISTER DEFINITION Figure 5 REGISTER 7 6 0.1 SEC 5 4 3 2 1 0.01 SEC 0 00-99 RANGE
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FDC 82077SL

DS2501 transistor

Abstract: WASHING machine interfacing 8051 + HHH+ Hex Non-Inverting Buffer Hex Inverter Hex Inverter, Schmitt Trig Hex Inverter, Schmitt Trig 3-St Hex, Non-Inv. Buffer 3-St Hex, Non-Inv. Buffer 3-St Hex, Inverting Buffer 3-St Hex, Inverting Buffer , Master/Slave Dual, 0-K w/Clear . Dual, J-K W/Clear 3-State Quad D Hex D Hex D Quad D Quad D 3-State Octal , 4049B 156-0503-02 156-0504-00 156-0504-01 156-0504-02 156-0494-02 N N N N A HHHHH Hex Hex Hex Hex Hex
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DS2501 transistor WASHING machine interfacing 8051 Sony Semiconductor Replacement Handbook 1991 touch dimmer TC 306 S PNI 12927 edn handbook DS1802
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