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Part Manufacturer Description Datasheet BUY
SN74LS00N-00 Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PDIP14 visit Texas Instruments
SN74LS00DBR Texas Instruments Quad 2-input positive-NAND gates 14-SSOP 0 to 70 visit Texas Instruments Buy
SN74LS00NE4 Texas Instruments Quad 2-input positive-NAND gates 14-PDIP 0 to 70 visit Texas Instruments
SN74LS00DBRE4 Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PDSO14, GREEN, PLASTIC, SSOP-14 visit Texas Instruments
SN74LS00NSR Texas Instruments Quad 2-input positive-NAND gates 14-SO 0 to 70 visit Texas Instruments Buy
SN74LS00J-00 Texas Instruments IC LS SERIES, QUAD 2-INPUT NAND GATE, CDIP14, Gate visit Texas Instruments

74LS00 function table

Catalog Datasheet MFG & Type PDF Document Tags

74LS00 pin configuration

Abstract: gd74ls04 GD54/74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES Description This device contains four independent 2-input NAND gates, jt^ performs the Boolean functions Y = A B or Y=A+B in positive logic. Function Table (each gate) INPUTS OUTPUT A B Y H H L L X H X L H Pin Configuration Vcc 4B 4 A 4 Y 3B , to 150°C 4-3 This Material Copyrighted By Its Respective Manufacturer GD54/74LS00 Recommended , 4-4 This Material Copyrighted By Its Respective Manufacturer GD54/74LS00 Application Example
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GD74LSOO 74LS04 74LS00 pin configuration gd74ls04 74LS00 function table pin configuration 74LS00 74LS00 Electrical and Switching characteristics 74LS04 NOT gate GD54/74LS00 125CC GD74LS04

74LS00 function table

Abstract: pin configuration 74LS00 lIoJ lioJ Function Table (each gate) OUTPUT INPUTS 1 2 A B V 1A 1B 3 H , GD54/74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES Description This device contains four independent 2-input NAND gates. K performs the Boolean functions Y = A B or Y = A + B in positive logic , . - 6 5 ° C to 1 5 0 ° C 4-3 GD54/74LS00 Recommended Operating Conditions SYMBOL MIN , -1 1 . 4-4 GD54/74LS00 Application Example Crystal Clock Generator (1) G D74LS00 c
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74LS00 clock frequency D74LS04

IC 74LS00

Abstract: 74LS00 GD54/74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES Description This device contains four independent 2-input NAND gates. It performs the Boolean functions Y = A B or Y = A + B in positive logic. Pin Configuration V cc 14 4B 13 4A 12 4Y 11 3B 10 3A 9 3Y 8 Function Table (each gate) INPUTS A H , . - 6 5 CC to 1 5 0 ° C 2-45 40HÖ7S7 OOGHnO fib4 GD54/74LS00 Recommended Operating , GD54/74LS00 Application Example Crystal Clock Generator (1) G D 7 4 L S 0 0 c, Frequency (MHz) 1
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IC 74LS00 NAND 74LS00 74ls00 NAND gate 74LS00 application 402B757

ls 7400

Abstract: 7400 signetics TTL DIP N7400N, N74LS00N, N74S00N Plastic SO N74LS00D, N74S00D FUNCTION TABLE INPUTS OUTPUT A B Y L , Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7400 9ns 8mA 74LS00 9.5ns 1.6mA , . INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74 74S , 74LS A, B Inputs 1ul 1Sul 1 LSul , , 1N3064, or equivalent. tTLH. t-rHL Values should be less than or equal to the table entries. VM = 1.3V , .) PARAMETER TEST CONDITIONS1 7400 74LS00 74S00 UNIT Min Typ2 Max Min Typ2 Max Min Typ2 Max
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ls 7400 7400 signetics TTL TTL LS 7400 7400 ls 7400 pin configuration TTL 7400 propagation delay 74SOO WF07570S

7400 signetics

Abstract: 74LS00 7400 74S00 N7400N, N74LS00N, N74S00N Plastic SO N74LS00D, N74S00D FUNCTION TABLE INPUTS OUTPUT A B Y U L H L , Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7400 9ns 8mA 74LS00 9.5ns 1.6mA , OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74 74S 74LS A, B Inputs 1ul 1Sul 1 LSul y Output , , 1N3064, or equivalent. tTLHi tTHL Values should be less than or equal to the table entries. 1.3V for , CONDITIONS1 7400 74LS00 74S00 UNIT Min Typ2 Max Min Typ2 Max Min Typ2 Max HIGH-level OH output
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7400 signetics 74LS00 7400 74S00 TTL 7400 74LS00 DATA 74LS00 fan-out tPHL 7400 LS03Z90S

74LS00 function table

Abstract: pin configuration logic symbol 74LS00 ; TA = 0°C to + 70°C N7400N, N74LS00N, N74S00N N74LS00D, N74SOOD FUNCTION TABLE INPUTS A L L H H H , Products TYPE 7400 74LS00 74S00 TYPICAL PROPAGATION DELAY 9ns 9.5ns 3ns TYPICAL SUPPLY CURRENT , . INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS A, B Y MOTE: Where a 74 unit load (ul) is understood , equivalent. triH , tTHL Values should be less than or equal to the table entries. Input Pulse Definition , 74LS00 Max Min 2.7 0.4 Typ2 3.4 0.35 0.25 -1 .5 0.5 0.4 -1 .5 Max Min 2.7 74S00 UNIT Min Typ2 3.4 0.2
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pin configuration logic symbol 74LS00 specification of 74ls00 logic symbol 74LS00 TTL 74ls00 7400 quad NAND pin configuration N74LS00

74LS00 TTL

Abstract: 74LS00 noise immunity or 10 U.L. 40nA Relative load and drive factors for the basic TTL families are given in Table 1. Table 1 Family 74LS00 7400 9000 74H00 74S00 Input Load High 0.5 U.L. 1 U.L. 1 U.L. 1.25 U.L. 1.25 U.L , +125°C. TTL families may be mixed for optimum system design. The following table specify the worst case , 3. The 74LS00 gate which has an Iil of 0.36 mA and an I ih of 20 |iA, has input LOW load factor of , the 74LS00 (Commercial Grade) will sink 8.0 mA in the LOW state and source 400 l±A in the HIGH state
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74LS00 TTL 74LS00 noise immunity 74LS00 gate 7400 fan-in 74ls00 applications TTL 7400 rise and fall time 54H/74H 54LS/74LS

IC TTL 74LS00

Abstract: TTL LS 7400 families are given in Table 3.3. INPUT LOAD OUTPUT DRIVE FAMILY HIGH 74LS00 7400 9000 74H00 , . Table 3.1 lists the guaranteed logic levels for various TTL families and can be used to calculate noise margin. Table 3.2 specifies these noise margins for systems containing LS, S, ALS and/or FASTTM TTL. Note that Table 3.2 represents "worst case" limits and assumes a maximum power supply and temperature , can be achieved by designing with decreased maximum allowable operating ranges. Table 3.1 Worst
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IC TTL 74LS00 IC TTL 74 ls 04 7400 fan-out cmos 7400 fan-out TTL 7400 catalog of ic 74ls00

IC AND GATE 7408 specification sheet

Abstract: 74LS96 Support for TTL Macrofunctions Table 4. TTL Function Mappings in Altera-Provided LMFs (Part 1 o f 3 , Page 325 PLS-EDIF Data Sheet Table 4. TTL Function Mappings in Altera-Provided LMFs (Part 2 o , P L U S -c o m p a tib le functions. Table 1. Mentor Graphics Library Mapping File (Basic Functions) Mentor Graphics Function AND# BUF DELAY DFF INV JKFF LATCH NAND# NOR# OR# XFER XNOR2 XOR2 MAX+PLUS-Compatible Function AND# SCLK MCELL DFF2 NOT JKFF2 MLATCH NAND# NOR# OR# TRI XNOR XOR (#=2,3,4,5 6,9) (#=2,3
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IC AND GATE 7408 specification sheet 74LS96 74LS183 SN 74168 7486 XOR GATE IC 74LS192

74HC00M

Abstract: IC 74HC00 RANGE Vcc (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 SYMMETRICAL OUTPUT IMPEDANCE I I , 54/M 74HC00 TRUTH TABLE A L L H H B L H L H Y H H H L .A I B 2 2 A B II 2 - I Ì 2 - ^ ^ \ ( 6 ) à , , 11 7 14 3 B Ü 5 L SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND Vcc NAME AND FUNCTION Data Inputs Data
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54HC00 74HC00M 00B1R IC 74HC00 74hc00 equivalent 74LS00 PIN M74HC00M1R 54/74LS00 54HC00F1R M54/74HC00

TTL 74HC00

Abstract: 74LS00 TTL Logic Symbol and Logic Diagram Function Table INPUTS OUTPUT nA nB nY L L H L H H H L H H H L H-HIGH , GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are characterized for opération over Wide temperature ranges to meet in-dustry and military spécifications. Features â'¢ Low Power consumption characteristic of CMOS devices â'¢ Output drive capability: 10 LS TTL
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TTL 74HC00 74hc00 and gates 74LS00 gate diagram 5V 74HC00 74HC00 CMOS 000M5L7 00Q42 GD74HC00 GD54HC00 GD74HCT00

74LS00 pinout

Abstract: 74hc00 and gates Logic Symbol and Logic Diagram Function Table INPUTS OUTPUT nA nB nY L L H L H H H L H H H L , GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet industry and military specifications. Features â'¢ Low Power consumption characteristic of CMOS devices â'¢ Output drive capability: 10 LS TTL
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74LS00 pinout 74HC GD54HCT00

74LS00 integrated circuit

Abstract: Package) C1R (Chip Carrier) tPLH = tPHL â  PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 â , -6946 >- 9 o >- < NZ zw O O 1/4 99 M 54/M 74HC T00 IEC LOGIC SYMBOL TRUTH TABLE A B Y , NAME AND FUNCTION 1 ,4 ,9 , 12 1A to 4A Data Inputs 2, 5, 10, 13 1B to 4B Data Inputs
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74LS00 integrated circuit M54HCT00 M74HCT00 M54/74HCT00 54HCT00F1R 74HCT00M 74HCT00B1R

CD4011 internal diagram

Abstract: of 74ls00 in plastic PIN ASSIGNMENTS PIN FUNCTION PIN FUNCTION 1 CH0/CH0 HI 40 LATCH 2 CH1/CH1 HI 39 MA2 , defined in Tables 1, 2, and 3. FUNCTION DEFINITION FUNCTION R/C Read/Convert 1L_ initiates conversion 2 , Select Channels MA1 Address (see MUX Logic Table 3) MA2* MODE 12-bit/8-bit 1. High (1) indicates 8-bit conversion 2. Low (0) indicates 12-bit conversion 'HS 9408 only Table 1. Defining the Control Functions , Initiates read Table 2. Truth Table - Control Inputs MUX ADDRESS INPUTS CHANNEL SELECTED MA2* MA1 MAO
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CD4011 HI-509A MUX-24 CD4011 internal diagram of 74ls00 CD4011 equivalent pin configuration cd4011 CD4011 PIN DIAGRAM cd40115 HS9404 HI-508A
Abstract:   WIDE OPERATING VOLTAGE RANGE Vcc (OPR) = 2 V TO 6 V â  PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 , IEC LOGIC SYMBOL TRUTH TABLE A B Y L L H L H H H L H H H L PIN D ESC RIPTIO N PIN No SYMBOL NAME AND FUNCTION 1 ,4 , 9, 12 1A to 4A Data -
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M54HC00 M74HC00 74HC00B1R 74HC00C1R S-6499 G05431D
Abstract: elays tpLHMpHL â'¢ Wide Operating Voltage Range V -
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TC74HC00AP/AF/AFN TC74HC00A TC74HC00AP/AF/AFN-1 TC74HC00AP/AF/AFN-3

pin diagram of ic 74ls00

Abstract: M74HC00 when at least one of the inputs is low, the output Y will become high. FUNCTION TABLE Inputs Output Y , logic 4000B series while giving high-speed performance equivalent to the 74LS00. Buffered outputs Y
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M74HC00P M74HC00DP pin diagram of ic 74ls00 74LS00 transfer function pin diagram of 74ls00 74ls00 circuit diagram M74HCOO 14P2P

TTL 74HC00

Abstract: 74HCoo Suffix-D : Small Outline Package Logic Symbol and Logic Diagram Function Table INPUTS OUTPUT nA nB , GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet industry and military specifications. Features â'¢ Low Power consumption characteristic of CMOS devices â'¢ Output drive capability: 10 LS TTL
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74HCoo 74hc00 tphl tplh tPHL 74hc00 74HCT00 74 LS 00 Logic Gates

74ls163 function table

Abstract: 74LS163 ENP or ENT are allowed regardless of the level of the clock input. Function Table (Note 1) CLR LOAD , without addiitional ga«ngin f "â"¢"â"¢ in accomplishing this function are two counter-enable inputs and a , . Inhibit CLEAR OUTPUTS ^ Application Example VARIABLE MODULO COUNTER 1/6 74LS04 or 1/4 74LS00 or1/3 , transition for the LS163A. Function Block Diagram 4-131 This Material Copyrighted By Its Respective
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74ls163 function table 74LS163 pin configuration 74LS10 1324NS SYNCHRONOUS LOAD CLEAR ENABLE COUNTER 54LS GD54/74LS163A GD54/74LS163

74ls163 function table

Abstract: . Function Table (Note 1) CLR LOAD Et Ep CK L X X X t H L L X Q Qb Qc , pulse regardless of the levels of the enable inputs The clear function is asynchronous and a low level , synchronous applications without additional gating. Instrumental in accomplishing this function are two , to inputs of GATE 3 Qc 6 Qa Qc 7 Q b Qc 9 1/6 74LS04 or1/4 74LS00 or1 , Note 1 propagation delay for clearing is measured from the clock transition for the LS 163A Function
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4DE6757 000424G
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