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SN74LS00DBRE4 Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PDSO14, GREEN, PLASTIC, SSOP-14 visit Texas Instruments
SN74LS00NSR Texas Instruments Quad 2-input positive-NAND gates 14-SO 0 to 70 visit Texas Instruments Buy
SN74LS02DE4 Texas Instruments Quad 2-input positive-NOR gates 14-SOIC 0 to 70 visit Texas Instruments
SN74LS02NSRG4 Texas Instruments Quad 2-input positive-NOR gates 14-SO 0 to 70 visit Texas Instruments
SN74LS03NSR Texas Instruments Quad 2-input positive-NAND gates with open collector outputs 14-SO 0 to 70 visit Texas Instruments
SN74LS04N Texas Instruments Hex inverters 14-PDIP 0 to 70 visit Texas Instruments Buy

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74LS Datasheet

Part Manufacturer Description PDF Type
74LS National Semiconductor Decade and Binary Counters Original
74LS On Semiconductor SYNCHRONOUS 4-BIT UP/DOWN COUNTER Original
74LS Mitsubishi OCTAL BUFFER/LINE DRIVERS WITH 3-STATE OUTPUT(NONINVERTED) Scan
74LS00 Fairchild Semiconductor Quad 2-Input NAND Gate Original
74LS00 Fairchild Semiconductor QUAD 2-INPUT NAND GATE Scan
74LS00 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan
74LS00 Raytheon Positive-NAND Gates, Hex Inverters Scan
74LS00 Signetics Quad 2-INPUT NAND Gate Scan
74LS00 Signetics Quad Two-Input NAND Gate Scan
74LS00 Signetics Integrated Circuits Catalogue 1978/79 Scan
74LS00C N/A TTL Data Book 1980 Scan
74LS00DC Fairchild Semiconductor QUAD 2-INPUT NAND GATE Scan
74LS00FC Fairchild Semiconductor QUAD 2-INPUT NAND GATE Scan
74LS00M N/A TTL Data Book 1980 Scan
74LS00N Fairchild Semiconductor Quad 2-Input NAND Gate Original
74LS00N Motorola QUAD 2-INPUT NAND GATE Original
74LS00N On Semiconductor Quad 2-Input NAND Gate Original
74LS00N Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Original
74LS00PC Fairchild Semiconductor Quad 2-INPUT NAND Gate Scan
74LS00PC N/A QUAD 2-INPUT NAND GATE Scan
Showing first 20 results.

74LS

Catalog Datasheet MFG & Type PDF Document Tags

D836A

Abstract: k1606 834 D N 835 DN 837 DN 838 DN 839 DN 850 DN851 D N 852/P D N 6835 DN 6844 DN 6845 DN 6846 D N 74LS 00/S D N 74LS 01/S D N 74LS 02/S D N 74LS 03/S D N 74LS 04/S D N 74LS 05/S D N 74LS 08/S D N 74LS 09/S D N 74LS 10/S D N 74LS11/S O N 74LS12/S D N 74LS 13/S D N 74LS 14/S D N 74LS 15/S - Alternative DN , /6853 - Type No. D N 74LS 16-1/S D N 74LS 17-1/S D N 74LS 20/S D N 74LS 21/S D N 74LS 22/S D N 74LS 26/S D N 74LS 27/S D N 74LS 28/S D N 74LS 30/S D N 74LS 32/S D N 74LS 33/S D N 74LS 37/S D N 74LS 38
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D836A k1606 K 1833 B948A D856A N6015 MN115P 1204B 1215P MN1221 1227B 1237/A

rs flip-flop IC 7400

Abstract: 74ls105 types used are shown in table 4. Table 4 QUANTITY 54/74LS TYPE STD TYPE CMOS TYPE 200 54/74LS00 54/7400 54/7474 54/74LS74 8280 54/74LS196 Table 5 DEVICE POWER REQUIREMENTS - Per Package (mW) 54/74LS , derived from the ability to upgrade 5400/7400 designs to 54/74LS. 1. The ability to immediately eliminate , affected by sim ply plugging in 54/74LS. 2. Reduced power supply cost. 3. Upgrade system capability by , 54L/74L with 54/74LS. 2. Check loading rules. The loading rules for 54/74L are almost identical to 54
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rs flip-flop IC 7400 74ls105 TTL LS 7400 74LS series logic gates 7400 fan-out 74LS 3 input AND gate 54/74XX

LS367A

Abstract: equivalent. Rx · 1kH for 74, 74S, Rx = 5kH for 74LS. tjLH. tjHL Values should be less than or equal to the , Products FUNCTION TABLE, '365A, '366A INPUTS I° l ml oe2 TYPE 74365A, 367A 74LS365A, 367A 74366A, 368A 74LS366A, 368A OUTPUTS I L H X X Y L H (Z) (Z) Y H L (Z) (Z) L L X H L L H X ORDERING , 74 1ui 20ul 74LS 1LSul 30LSul Where a 74 unit load (ul) is understood to be 40/jA Iih and - 1 .6mA l(L, and a 74LS unit load (LSul) is 20juA Iih and -0.4mA Iil- PIN CONFIGURATION '365A '366A
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LS367A LS365A LS366A LS368A SO-16 N74365AN

74LS259

Abstract: 8bit latch 74ls 74LS259 AC ELECTRICAL CHARACTERISTICS TA - 25°C, v cc - 5.0V 74LS TEST CONDITIONS CL =15pF, RL = , ; Vu - 1.3V lo r 74LS. VM - 1.5V (or 74 and 74S; VM - 1.3V lo r 74LS. Waveform 1. Propagation , r 74LS. VM - 1.5V for 74 and 74S; VM = 1.3V for 74LS. Waveform 3. Propagation Delay Address To , and 74S; VM - 1.3V for 74LS. The shaded areas indicate when the input is permitted to change for predictable output performance. VM - 1.5V for 74 and 74S; VM - 1.3V for 74LS. The shaded areas indicate when
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8bit latch 74ls N74LS259N N74LS259D 1N916 1N3064

74ls gate symbols

Abstract: 74LS series logic gate symbols 54LS/74LS51 - - 54LS /74LS 54 - - - 54LS /74LS 55 54/7450 54/7451 54/7453 54/7454 - - - - - , Schottky 54S/74S 3 ns/19 mW L o w Power Schottky 54LS/74LS 5 ns/2 mW ~c g o c 3 li. < 0 S > o> (S J£ o < 0 a. Exclusive NOR Gate 1 Q uad 2 -In p u t (OC) 9386 (8242) Item - 74LS266 , (3S) Hex
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74ls gate symbols 74LS series logic gate symbols 74LS logic gates 74LS TTL series oc 44 buffer 74ls series logic gates 54H/74H 54LS/74LS 54LS/74LS51 54H/74H51 54S/74S51

74LS

Abstract: 74ls characteristics SPEED /PACK AG E AVAILABILITY 54 54H 54LS 54S F,W F,W F,W F,W 74 74H 74LS 74S A,F A,F A,F A,F PIN CONFIGURATION 54/74, 54/74LS, 54S A,F,W PACKAGE 54/74H W PACKAGE SWITCHING CHARACTERISTICS vCc - 5V, t a - 2s°c 54/74 U E 54/74H C[_=25pF RL =280« MAX MIN TYP MAX MIN 54/74LS C L =15pF RL =2kQ , AG E AVAILABILITY 54 F,W 54H F,W 54LS F,W 74 74H 74LS A,F A,F A,F PIN CONFIGURATION 74.54/74LS A , AG E AVAILABILITY 54 F,W 54LS F,W 54S F,W 74 A ,F 74LS A, F 74S A,F PIN CONFIGURATION 74.54/74LS
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74ls characteristics 74LSc 7454 configuration 54/74LS 54/74S 54/74L8 280S2

74LS259

Abstract: CD042 WAVEFORMS 74LS259 VM - 1.5V for 74 and 74S; VM - 1.3V lor 74LS. Waveform 1. Propagation Delay Enable To , 74LS. Waveform 2. Propagation Delay Data To Output - , Qn WM,EÂ¥/' VM - 1,5V for 74 and 74S; VM - 1.3V for 74LS. The shaded areas indicate when the input , VM - 1.5V for 74 and 74S; VM - 1.3V for 74LS. The shaded areas indicate when the input is permitted
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CD042 demultiplexer 74ls

74LS259

Abstract: AC WAVEFORMS - 'PHI- »M VM - 1.5V for 74 and 74S; VM - 1.3V lo r 74LS. VM - 1.5V lo r 74 and 74S; Vu - 1.3V lo r 74LS. Waveform 1. Propagation Delay Enable To Output And Enable Pulse , * y z r ={ VM - 1.5V for 74 and 74S; VM - 1.3V for 74LS. VM - 1.5V for 74 and 74S; VM - 1.3V for 74LS. Waveform 3. Propagation Delay Address To Output Waveform 4. Clear To Output Delay And Clear Pulse Width ADDRESS VM - 1.5V for 74 and 74S; VM - 1.3V for 74LS. The shaded areas
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74LS541

Abstract: 74LS541 equivalent Signetics I 74LS540, 74LS541 Buffers/Drivers Logic Products Octal Buffer/Line Driver (3 , 74LS540, 74LS541 ABSOLUTE MAXIMUM RATINGS (Over operating free-air temperature range unless otherwise , 74LS540, 74LS541 AC ELECTRICAL CHARACTERISTICS TA = 25°C, Vcc = 5.0V PARAMETER TEST CONDITIONS 74LS540 , AC WAVEFORMS Vm Vqut % VM MplhH VM - 1.5V for 74 and 74S; VM = 1.3V lor 74LS. Waveform 1 , 1.3V for 74LS. Waveform 2. Waveform For Non-Inverting Outputs v. â'"'PZH > f -=1.; vM à Vm
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N74LS540N N74LS541N N74LS540D N74LS541D 74LS541 equivalent signetics 74LS541 SOL-20 LS06090S

PIN CONFIGURATION 7475

Abstract: 7475 D latch i Jf- m 'plh £ VM- 1.5V for 74 and 74S; Vu - 1.3V for 74LS. Waveform 1. Propagation Delay , 74 and 74S; VM-1.3V for 74LS. Waveform 3. Latch Enable To Output Delays And Latch Enable Pulse Width V». â'¢'phl* V i-'plkh VM- 1.5V for 74 and 74S; Vâ'ž-1.3V for 74LS. Waveform 2. Propagation Delay Data to Q Q Outputs W -W â'" VM - 1.5V for 74 and 74S; VM - 1.3V tor 74LS. The shaded areas , Signetics Logic Products FEATURES â'¢ 4-bit bistable latch â'¢ Refer to 74LS375 for Vcc and
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74LS75 PIN CONFIGURATION 7475 7475 D latch LS 7475 7475 Quad bistable latches pin configuration pin configuration of 7475 TTL 7475 N7475N N74LS75N N74LS25D

schmitt trigger 7414

Abstract: 7414 31mA 74LS14 15ns 10mA ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = 5V±5%; Ta = 0°C to +70°C , FAN-OUT TABLE PINS DESCRIPTION 74 74LS A Inputs 1ul 1LSul Y Output 10ul 10LSul NOTE: Where a 74 unit load (ul) is understood to be 40/jA l,H and -1.6mA l,L, and 74LS unit load (LSul) is 20jiA ltH and , unless otherwise noted.) PARAMETER 74 74LS UNIT Vcc Supply voltage 7.0 7.0 V ViN Input voltage -0.5 to , RECOMMENDED OPERATING CONDITIONS PARAMETER 74 74LS UNIT Min Nom Max Min Nom Max Vcc Supply voltage
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N7414N N74LS14N N74LS14D schmitt trigger 7414 7414 TTL 7414 7414 ttl inverter TTL 7414 data LS14

TTL 7414

Abstract: TTL 7414 data and supply voltage varia tions. TYPE 7414 74LS14 TYPICAL PROPAGATION DELAY 15ns 15ns TYPICAL , Iih and -1 .6 m A l)L, and 74LS unit load (LSul) is 20#iA Iih and -0 .4 m A lu_. DESCRIPTION Inputs Output 74 1ul 10ul 74LS 1LSul 10LSul PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC , 7.0 -0 .5 to + 5 .5 - 3 0 to + 5 -0 .5 to + V c c 0 to 70 74LS 7.0 - 0 .5 to +7.0 - 3 0 to +1 -0 .5 to , Min 4.75 Nom 5.0 Max 5.25 -1 8 -4 0 0 8 70 V mA HA mA 74LS UNIT 4.75 Vcc IlK >O H !ol Ta Supply
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74LS14 function table 7414 hex not 7414 equivalent pin configuration 74LS14 7414 PIN 74ls14 pin configuration

74256

Abstract: ttl 74256 for 74 and 74S; VM = 1.3V for 74LS. Waveform 2. Propagation Delay Data To Output "V. Iâ'"'I V. VM = 1.5V for 74 and 74S; VM = 1.3V for 74LS. Waveform 4. Clear To Output Delay And Clear Pulse Width VM - 1.5V tor 74 and 74S; VM - 1.3V for 74LS. The shaded areas indicate when the input is , AC WAVEFORMS / jâ'"â'",â'"V _r- v- /' VM - 1.5V for 74 and 74S; VM - 1.3 V for 74LS. Waveform , ; VM = 1.3V for 74LS. Waveform 3. Propagation Delay Address To Output IS Vâ'ž - 1.5V for 74 and 74S
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74LS256 N74LS256N N74LS256D 74256 ttl 74256
Abstract: Flip-Flop 74LS364 RECOMMENDED OPERATING CONDITIONS 74LS PARAMETER Min VCC V|H VlL IlH lOH >O L Ta , Flip-Flop 74LS364 AC ELECTRICAL CHARACTERISTICS TA = 25°C, vcc = 5.0V 74LS PARAMETER , ~ )r r-'pzM- I VM 'PMZ VM = 1.5V for 74 and 74S; VM=1.3V for 74LS. VM - 1.5V fo r 74 and 74S; VM-1 .3 V lo r 74LS. Waveform 1. Clock To Output Delays And Clock Pulse Width Waveform , - tpLZ - L in \ VM - 1.5V for 74 ar>d 74S; VM=*1.3V for 74LS. The shaded areas indicate when the -
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N74LS364N

74LS364

Abstract: 1N3064 and 74S; VM-1.3V for 74LS. Waveform 1. Clock To Output Delays And Clock Pulse Width "-'PZH i 'PHZ VM - 1.5V for 74 and 74S; VM=1.3V for 74LS. Waveform 2. 3-State Enable Time To High Level And , 74LS. Waveform 3. 3-State Enable Time To Low Level And Disable Time From Low Level Vm - 1.5V for 74 and 74S; Vâ'ž-1.3V for 74LS. The shaded areas indicate when the input is permitted to change for , Generators. D = Diodes are 1N916, 1N3064, or equivalent. Rx - 1ki2 for 74, 74S, Rx = 5kf2 for 74LS.
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7421 ttl AND gate

Abstract: TTL 7421 8mA 74LS20 10ns 0.8mA 74S20 3 ns 8mA 7421 12ns 8mA 74LS21 9ns 1.7mA ORDERING CODE FUNCTION TABLE , l-'PLH-j VOUT \v" -f* wf07570s VM - 1-3V for 74LS- VM - 1 5V for all other TTL families. Waveform 1 , DESCRIPTION 74 74S 74LS A-D Inputs 1ul 1Sul 1LSul Y Output 10ui 10Sul 10LSul Where a 74 unit load (ul) is understood to be 40/jA l|H and -1.6mA l|L, a 74S unit load (Sul) is 50(jA I,h and -2.0mA l|L, and 74LS unit , +Vcc 74LS 7.0 -0.5 to +7.0 -30 to +1 -0.5 to +Vcc 74S 7.0 -0.5 to +5.5 -30 to +5 -0.5 to +Vcc
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7421 ttl AND gate TTL 7421 7421 pin configuration PIN CONFIGURATION 7420 TTL 7420 logic gate 7421 AND N7420N N74LS20N N74S20N N7421N N74LS21N N74LS20D

74ls Logic Family Specifications

Abstract: 74LS136 .) 74LS136 UNIT Min Typ2 Max 100 Io l = MAX Io l = 4mA (74LS) mA !oh HIGH-level output current , Signetics 74LS136 Gate Quad Two-Input Exclusive-OR Gate (Open Collector) Product Specification Logic Products TYPE 74LS136 TYPICAL PROPAGATION DELAY 18ns TYPICAL SUPPLY CURRENT (TOTAL) 6.1mA , voltage level INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS A, B Y DESCRIPTION Inputs Output 74LS 2LSul 10LSul NOTE: Where a 74LS unit load (LSul) is 20/jtA Iih and-0.4mA ln_. PIN CONFIGURATION
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74ls Logic Family Specifications 74Ls signetics N74LS136N WF07570S F07380S

TTL 7475

Abstract: 7475 D latch VM - 1,5V for 74 and 74S; VM - 1.3V for 74LS. Waveform 1. Propagation Delay Data To Q Outputs , 1.3V for 74LS. Waveform 3. Latch Enable To Output Delays And Latch Enable Pulse Width "-jf*" V »'PHL* V 3k VM - 1.5V for 74 and 74S; VM - 1.3V for 74LS. Waveform 2. Propagation Delay Data to Q Q Outputs VM - 1,5V for 74 and 74S; VM - 1.3V for 74LS. The shaded areas indicate when the input is , FEATURES â'¢ 4-bit bistable latch â'¢ Refer to 74LS375 for VCc and GND on corner pins DESCRIPTION The
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7475 data latch Equivalent 74LS75 7475 ttl pin diagram of 7475 7475 latch 7475F
Abstract: AC WAVEFORMS r-'pzH AT 1 h 1 V M - 1.5V for 74 and 74S; V M« 1 .3 V fo r 74LS. V M = 1.5V for 7 4 and 74S; V M= 1 3 V for 74LS. Waveform 1. Clock To Output Delays And Clock Pulse Width , - \ V m - 1.5 V for 7 4 and 74S; V M= 1 .3 V for 74LS. V M - 1 . 5 V for 74 and 74S; V M« 1 .3 V for 74LS. T h e shaded are a s indicate w hen th e input is permitted to ch a n g e for predictable , Specification Flip-Flop 74LS364 TEST CIRCUITS AND WAVEFORMS Vcc V M = 1.3 V for 74LS; V M = 1.5V -
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74LS364

Abstract: ; VM-1 .3 V for 74LS. AT 1 h ' " '" " H ( - 0.5V _ ,.,V VM - 1.5V tor 74 and 74S; VM- 1.3V for 74LS. Waveform 1. Clock To Output Delays And Clock Pulse Width Waveform 2. 3 , - 'PLZ - VM - 1.5V for 74 and 74S; VM-1 .3 V for 74LS. VM - 1.5V for 74 and 74S; VM-1 .3 V for 74LS. The shaded areas indicate when the input is permitted to change for predictable output , Flip-Flop 74LS364 TEST CIRCUITS AND WAVEFORMS Vcc VM - 1.3V for 74LS; VM - 1.5V for all other TTL
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74 and and or

Abstract: 74ls 834 D N 835 DN 837 DN 838 DN 839 DN 850 DN851 D N 852/P D N 6835 DN 6844 DN 6845 DN 6846 D N 74LS 00/S D N 74LS 01/S D N 74LS 02/S D N 74LS 03/S D N 74LS 04/S D N 74LS 05/S D N 74LS 08/S D N 74LS 09/S D N 74LS 10/S D N 74LS11/S O N 74LS12/S D N 74LS 13/S D N 74LS 14/S D N 74LS 15/S - Alternative DN , /6853 - Type No. D N 74LS 16-1/S D N 74LS 17-1/S D N 74LS 20/S D N 74LS 21/S D N 74LS 22/S D N 74LS 26/S D N 74LS 27/S D N 74LS 28/S D N 74LS 30/S D N 74LS 32/S D N 74LS 33/S D N 74LS 37/S D N 74LS 38
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74 and and or buffer 74 LS 04 74LS95 LS 109 LS-20 20DIP

cem wax a

Abstract: Signetics Military Products Data Manual. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74LS All Inputs 1LSul All Outputs 30LSul MOTE: A 74LS unit load (LSul) is 20jiA t,H and -0.4mA lrL , and disable outputs H H Ã t 1 h L H (Z) (Z) PARAMETER 74LS UNIT Vcc Supply voltage 7.0 V V,n , OPERATING CONDITIONS PARAMETER 74LS UNIT Min Nom Max Vcc Supply voltage 4.75 5.0 5.25 V VlH , MIN, Vih = MIN, iol = MAX 0.35 0.5 v Vil = MAX Iol= 12mA (74LS) 0.25 0.4 v V|k Input clamp
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cem wax a 74LS620 LS623 LS620 74LS623 74LS620N

1N3064

Abstract: 1N916 AND FAN-OUT TABLE PINS All All NO TE: DESCRIPTION Inputs Outputs 74LS 1LSul 30LSul A 74LS unit load (LSul) is 20 /j A l|H and -0 .4 m A l|_. tion, is transferred to the corresponding , applied to output In HIGH output state Operating free-air temperature range 74LS 7.0 - 0 .5 to +7 .0 - , OPERATING CONDITIONS 74LS PARAMETER Min Vcc ViH V,L ilH ·o h lO L Ta UNIT Nom 5.0 Max 5.25 V V + , (74LS) MIN, l| - Iik = = MAX, V ,l MAX, V0 = 3.65V 20 -2 0 bZL VCc
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74LS295B N74LS295BN
Abstract: INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS All All NOTE: A 74LS unit load (LSui) is 20juA I¡h and -0 .4 m A In., DESCRIPTION Inputs Outputs 74LS 1LSul 10LSul latches, the enable should be , Voltage applied to output in HIGH output state Operating free-air temperature range 74LS 7.0 -0.5 to +7.0 -3 0 to +1 -0.5 to +Vcc 0 to 70 UNIT V V mA V "C RECOMMENDED OPERATING CONDITIONS 74LS PARAMETER , current3 Supply current4 (total) " MAX 2.7 " MAX 4mA (74LS) Io l = MAX, V, MAX, V, = -
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SN54/74LS377 SN54/74LS378 SN54/74LS379

74LS245 buffer ic

Abstract: ic 74ls245 · BCD decade counter TY PE 74L S 568A 74LS 569A T Y P IC A L W 35M H z 35M H z T Y P IC A L S U , 4LS 5 69A N INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS All Qo - Qa TC, GC NOTE: A 74LS unit load (LSul) is 20;uA Iih and -0 .4 m A l|L. D E S C R IP TIO N Inputs O utpu ts O utputs 74LS 1 , pe ratin g free -air tem p e ra tu re range unless otherw ise noted.) 74LS 7.0 - 0 .5 to + 7 .0 - 3 0 , RECOMMENDED OPERATING CONDITIONS 74LS P A R A M E TE R Min Vcc V|H V|L l|K 'OH Supply volta g e H IG H -level
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74LS245 74LS245 buffer ic ic 74ls245 74LS245 SIGNETICS LS 74LS245 function table of 74LS245 N74LS245N N74LS245D LS245
Abstract: description Input Input Inputs Outputs 74s 1Sul 2Sul 1Sul 10Sul 74ls 2LSul 1LSul 1LSul 10LSul Whlre a 74S unit load (Sul) is understood to be 50â'žA l,â'ž and -2.0mA lIL and a 74LS uni. load (LSul , output in HIGH output state Ta Operating free-air temperature range_ 74LS 7.0 -0.5 to +7.0 -30 to +1 , OPERATING CONDITIONS PARAMETER Vcc Supply voltage_ V|H HIGH-level input voltage 74LS Min VlL , for 74LS; vu â = 1,5v for all other TTL families. Input Pulse Definition mA MA mA °C FAMILY -
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74LS568A LS568/ LS569

74LS169A

Abstract: 74S168 LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74 74LS D Input 2ul 1LSUI E Input 4ul 4LSUI All Outputs 10ui 10LSul Where a 74 unit foad (ul) is understood to be 40/iA Iih and â'" t .6mA and a 74LS unit , RATINGS (Over operating free-air temperature range unless otherwise noted.) PARAMETER 74 74LS UNIT Vqc , Operating free-air temperature range 0 to 70 °C RECOMMENDED OPERATING CONDITIONS PARAMETER 74 74LS , outputs open. AC ELECTRICAL CHARACTERISTICS TA=25°C, vcc = 5.0V 74 74LS PARAMETER TEST
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74LS168A 74LS169A S168A 74S168A 74S169A N74LS168AN 74S168 N74S168AN S169A

74LS390N

Abstract: . INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74LS All Inputs 1LSul All Outputs 10LSul NOTE: a 74LS unit load (LSul) is 20(ja i,h and -0.4mA l,L. latches, the enable should be held HIGH , free-air temperature range unless otherwise noted.) PARAMETER 74LS UNIT Vcc Supply voltage 7.0 V VlN , CONDITIONS PARAMETER 74LS UNIT Min Nom Max Vcc Supply voltage 4.75 5.0 5.25 V VlH HIGH-level input , , Vih = min, Iol = max 0.35 0.5 V V|l = max |ol = 4ma (74LS) 0.25 0.4 V V|K input clamp voltage
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74LS390N 74LS390
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