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Part Manufacturer Description Datasheet BUY
SN74LS54FN Texas Instruments LS SERIES, 10-INPUT AND-OR-INVERT GATE, PQCC20 visit Texas Instruments
SN74LS55N-10 Texas Instruments LS SERIES, 8-INPUT AND-OR-INVERT GATE, PDIP14 visit Texas Instruments
SN74LS51FN Texas Instruments LS SERIES, DUAL 6-INPUT AND-OR-INVERT GATE, PQCC20 visit Texas Instruments
SN74LS55D Texas Instruments LS SERIES, 8-INPUT AND-OR-INVERT GATE, PDSO14 visit Texas Instruments
SN74LS54N-00 Texas Instruments LS SERIES, 10-INPUT AND-OR-INVERT GATE, PDIP14 visit Texas Instruments
SN74LS51J-00 Texas Instruments LS SERIES, DUAL 6-INPUT AND-OR-INVERT GATE, CDIP14 visit Texas Instruments

74LS series logic gate symbols

Catalog Datasheet MFG & Type PDF Document Tags

74ls gate symbols

Abstract: 74LS series logic gate symbols ,9B 4L,6B,9B 1. OC = open collector, 3S = 3-state. 2. The logic symbols located in the Logic , FAIRCHILD DIGITAL T T L SSI FUNCTIONS (Cont'd) Logic/Connection Diagram< 2 ) Std. TTL 9 N 54/74 1 0 ns/10 mW 9000 Series 8 ns/10 mW High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW L o w Power Schottky 54LS/74LS 5 ns/2 mW ~c g o c 3 li. < 0 S > o> (S J£ o < 0 a. Exclusive NOR Gate 1 Q uad 2 -In p u t (OC) 9386 (8242) Item - 74LS266
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74ls gate symbols 74LS series logic gate symbols 74LS series logic gates 74LS logic gates 74LS TTL series 74LS 54LS/74LS 54LS/74LS51 54H/74H51 54S/74S51 74S64

74ls gate symbols

Abstract: 74LS534 latch passes eight bits of data from the inputted) to the outputs (O) when the gate (G) is high. Th^dala Is *ï|atéhed" Function Tables '533 8-Bit Late Ordering Information Logic Symbols V '533 8 , V. For Series 54/74LS, Ro = 5K, Vj = 1.3 V. D. Waveform 1 is for an output with internal conditions , , ZouT = 50ftand: For Series 54/74S, tR < 2.5 ns, tp < 2.5 ns. For Series 54/74LS and PALs, tR < 15 ns , Mil Com Latch S 54S534 74S534 J,W,L N,J Mil Com Register when the gate (G> goes low. The reg
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SN54/74S533 74LS533 74LS534 74S533 74LS53 am290l SN54/74LS533 SN54/74LS534 SN54/74S534 SN54/74LS373/4 SN54/74S373/4

74LS series logic gates 3 input or gate

Abstract: 74LS series logic gates -state. 2. The logic symbols located In the Logic/Connection Diagram Section are for the DIP version. 3. For , FAIRCHILD DIGITAL TTL SSI FUNCTIONS (Cont'd) Item Function'1 ' 9000 Series 8 ns/10 mW Low Power Schottky 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram(2) 5
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74LS series logic gates 3 input or gate 74LS51 74125 ic 74LS55 r025 74LS125 54H/74H52 54H/74H50 54H/74H53 54H/74H54 54LS/74LS54 74S65
Abstract: t LorHorl X Q H L X X H L Qo z Logic Symbols â'™533 8-Bit Latch (Inverting , Series 54/74S, Rq - 1K, VT = 1.5 V. For Series 54/74LS, R o = 5K, V j = 13 V. D. Waveform 1 is fo ra n , . For Series 54/74LS and PALs, tR < 15 ns. tp < 6 ns. G. When measuring propagation delay limes of 3 , polarity must be changed Invert i Latch s Register when the gate(G) , buffers at the applications that require inversion as in interfacing the Am: ' A \gate/clock"lfiputs -
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54LS533 54LS534 54S533 1N916 1N3064 54/74LS

TTL 74126

Abstract: 74ls gate symbols Inverter (3S) 54LS/74LS368 D71 4L,6B,9B 1. OC = open collector, 3S = 3-state. 2. The logic symbols , FAIRCHILD DIGITAL TTL SSI FUNCTIONS (Cont'd) E « g s u c 3 LL. 9000 Series 8 ns/10 mW Low Power Schottky 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW , Gate 1 Quad 2-lnput (OC) _ 74LS266 9386 (8242) D94 3I,6A,9A AND-OR Gates 2 Dual , â'" D33 3I,6A,9A 12 4-4 Input 54LS/74LS55 - â'" â'" D34 3I,6A,9A Gate Expanders 13
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TTL 74126 7450 ttl Fairchild logic/connection diagrams ttl 74LS367 74LS126 74126 high speed 54H/74H55 54H/74H61 54H/74H60 54H/74H62 54LS/74LS125 54LS/74LS126

7450 ttl

Abstract: 74LS series logic gates 3 input or gate DIGITAL TTL SSI FUNCTIONS (Cont'd) Item Function'1 ' 9000 Series 8 ns/10 mW Low Power Schottky 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram(2) 5 , /74LS368 â'" â'" â'" D71 4L,6B,9B 1. OC = open collector, 3S = 3-state. 2. The logic symbols located In , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D25 9S42 Vcc S3 LüliJliJLtiLiJliJLiJUJ
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7454 9S42 74H51 74H55 74S84 9006 54LS/75LS54 54LS/74LS365 54LS/74LS366 54LS/74LS367

74ls gate symbols

Abstract: TTL 74ls125 '1 ' 9000 Series 8 ns/10 mW Low Power Schottky 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram(2) 5 , -state. 2. The logic symbols located In the Logic/Connection Diagram Section are for the DIP version. 3. For , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D65 54/7413, 54LS/74LS13 Vcc NC
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TTL 74ls125 74125 logic diagram 74125 74LS366 TTL 74ls126 54LS 54LS/74LS260

SN54173

Abstract: SN54LS173A SN74173 or SN74LS173A outputs may be connected to a common bus and still drive two Series 54/74 or 54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load, respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic , -STATE OUTPUTS logic symbols t '173 LS173A i (15) p I iV r^ & EN C1 ' p- i (2) r^ . (9) r^ &
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SN74 Scans-008894 SDLS067 SAI74LS173A

74LS series logic gates 3 input or gate

Abstract: 74LS series logic gate symbols Function'1 ' 9000 Series 8 ns/10 mW Low Power Schottky 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram(2) 5 , , 3S = 3-state. 2. The logic symbols located In the Logic/Connection Diagram Section are for the DIP , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D33 54H/74H55 D34 54LS/74LS55 Vcc Vcc 0
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74H62 TTL 74125 buffer 74ls series logic gates 74H60 ic 74125 S4H/74H61

TTL 74ls125

Abstract: 74ls125 ,6B,9B 4L,6B,9B 4L,6B,9B 4L,6B,9B O C = open collector, 3S = 3-state Th e logic symbols located in , FAIRCHILD DIGITAL TTL SSI FUNCTIONS (Cont'd) Logic/Connection Diagram(2) Std. TTL 9 N 54/74 1 0 ns/10 mW 9000 Series 8 ns/10 mW High Speed 54H/74H 6 ns/22 mW "c o o c 3 U. Exclusiv NOR Gate 1 Quad 2-Input (OC) _ - - 74LS266 9386 (8242) High Speed Schottky 54S/74S 3 ns , /74S51 D28 - - - 74S64 74S65 - - D29 D30 D31 D32 D32 D33 D34 Gate Expanders 13 14 15 T riple 3
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74ls368 S4LS/74LS13

74LS series logic gate symbols

Abstract: ly2j 3-STATE OUTPUTS logic symbols «1 (1 ) |N* EN ^ fc, 4 «1 r u«i (171 (1C) n si (14) m> (12) (11) 117» (It ) (15) (14) m i s . M« m i (3, «, IS ) «1 m in « logic diagram , and line drivers are designed to have the performance of the popular SN 54LS240/ S N 74LS24 0 series , . Th is arrangement greatly en hances printed circuit board layout. The three-state control gate is a 2 , SN 74LS 54 0 and S N 7 4 L S 5 4 1 are characterized for operation from 0 °C to 70 °C . SN54LSS40
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SN74LSS40 ly2j IC 74LS 121 SN74LS540 SN74LS541 SN54LS540 SN54LS541 LS541 54LS541

74LS series logic gate symbols

Abstract: drivers are designed to have the performance of the popular SN54LS240/ SN 74LS240 series and, at the same , greatly en hances printed circuit board layout. The three-state control gate is a 2-input NOR such that if , SN54LSS40, SN54LS541. SN74LS540, SN74LS541 OCTAL BUFFERS AND LIME DRIVERS WITH 3-STATE OUTPUTS logic symbols* ft G 1 - Ü Î- * G2 EN G 1 -Ü L-0 ¡SV rs & EN S . nii y i < 2 1 (31 («) (Si « 17) (8 , 4 ^ 2 * L v5 - *t3> Y B a iiL v ? ^ J ilL v s * These symbols are in accordance with ANSI/IEEE
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SNS4LS541 LS540 74LS541

74LS series logic gate symbols

Abstract: 74ls gate symbols 5 H L Qo z Logic Symbols '533 8-Bit Latch (Inverting) '533 8-Blt Register (Inverting , , V-p = 1.5 V. For Series 54/74LS. R q = 5K, V j = 1.3 V. D. W a v e fo rm l is fo ra n o u tp u tw , < 1 MHz, Z q u T - 5 0 fla n d : For S eries 54/74S, tR < 2.5 ns, tp < 2.5 ns. For Series 54/74LS and , assertive-low bus. The latch passes eight bits of data from the inputs (D) to the outputs (Q) when the gate (G) is high. The data is "latched" when the gate (G) goes low. The register loads eight bits of input
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SN54/74SS34

HJ6D

Abstract: 74365 -Bit Register (Inverting) OE CK D Q L î H L L î L H L L or H ori X Qo H X X z Logic Symbols 'S535 8 , < 2.5 ns. For Series 54/74LS and PALs, tR < 15 ns. tp i 6 ns. G. When measuring propagation delay , \ oufeiks^^*when thefg6telQ% h High. The data is "latched" \\grtjgklhe gate (Gtffoe» itow. VHi roister , SN74S535 SN74S536 IEEE Symbols 'S535 S536 Monolithic ISEII Memories 12-55 SN74S535 SN74S536 Absolute , includes probe and jig capacitance. B. All diodes are 1N916 or 1N3064. C. For Series 54/74S, Ro = 1K, VT
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HJ6D 74365 S535 SS36 7718Q SN74S533/4 SN54/74365/366/ 2901A S535/536

74ls gate symbols

Abstract: L X X Q H L Qo z Logic Symbols '373 8-Bit Latch '374 8-Bit Register O E E 1 Q E 10 E 2 Ö , , Z q u t = SOfiand. For Series 54/74S, t p < 2.5 ns. tp < 2.5 ns. For Series 54/74LS and PALs, 1 r , outputs (Q) when the gate (G) is high. The data is " latched" when the gate (G) goes low. The register , buffers at the gate/clock inputs improve system noise margin by providing typically 400 mV of hysteresis , IEEE Symbols '373 OEG3 JTG1 2 374 OECK3 - t ^ T EN JXC 1 1D > V 2 5 6 9 12 15 16 19 1D
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SN54LS373 SN74LS373 SN54LS374 SN74LS374 SN54S373 SN74S373

ALU IC 74181

Abstract: IC 74181 alu -state. 2. The logic symbols located In the Logic/Connection Diagram Section are for the DIP version. 3. For , 'S « Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 1 Adder 54/7480 Gated 1 , Logic Unit 9340 ALU with Internal CLA 4 24 400 D106 4M,6N,9N 10 Arithmetic Logic Unit 54/74181 ALU with External CLA 4 27 450 D107 4M,6N,9N 11 Arithmetic Logic Unit 93L41 ALU with External CLA 4 35 120 D107 4M,6N,9N 12 Arithmetic Logic Unit 74LS181 ALU with External CLA 4 20 105 D107 6N,9N 13 Arithmetic
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ALU IC 74181 IC 74181 alu ic 74LS83 74181 alu IC 74181 ic 7485 93H183 54H/74H183 54/7483A S/74LS83 54LS/74LS283 93S41

IC TTL 7432

Abstract: 74LS86 gate diagram -state. 2. The logic symbols located In the Logic/Connection Diagram Section are for the DIP version. 3. For , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 , ! li! li] li] GND 13-44 FAIRCHILD LOGIC/CONNECTION DIAGRAMS D93 54LS/74LS379 1 A 4 5 12 13 | E , 13-55 FAIRCHILD DIGITAL TTL SSI FUNCTIONS (Cont'd) Item Function'1 ' 9000 Series 8 ns/10 mW Low Power Schottky 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW
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IC TTL 7432 74LS86 gate diagram 7411 3 INPUT AND gate IC 7432 7411 pin diagram IC 7486 54S/74S09 54LS/74LS09 54H/74H21 54LS/74LS21 54S/74S32 54LS/74LS32

ALU IC 74181

Abstract: 74181 ic pin diagram -state. 2. The logic symbols located In the Logic/Connection Diagram Section are for the DIP version. 3. For , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 , ! li! li] li] GND 13-44 FAIRCHILD LOGIC/CONNECTION DIAGRAMS D93 54LS/74LS379 1 A 4 5 12 13 | E , 'S « Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 1 Adder 54/7480 Gated 1 , Logic Unit 9340 ALU with Internal CLA 4 24 400 D106 4M,6N,9N 10 Arithmetic Logic Unit 54/74181 ALU with
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74181 ic pin diagram DS 7409 7480 full adder 1 bit 74LS86 full adder TTL 74ls83 pin diagram of 7411 54H/74H11 54S/74S11 54LS/74LS11 54S/74S15 54LS/74LS15 54S/74S86

74s532

Abstract: 74LS series logic gate symbols 50fiand: For Series 54/74S, tp < 2.5 ns, tp < 2.5 ris. For Series 54/74LS and PALs. tp < 15 ns. tp ^ 6 ns , outputs (Q) when the gate (G) is high. The data is "latched" when the gate (G) goes low. The register , outputs are active when OE is low, and highimpedance when OE is high. Schmitt-trigger buffers at the gate , Q H L OE L L L H S532 8-Bit Register CK t t L or H or I X D H L X X Q H L Qq Qo z z Logic Symbols S531 8-Bit Latch SJvcc OE S532 8-Bit Register 3 ID ] ID I -E l id e FF JT OE
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74S531 74s532 6D70 SN74S373/4 SN74S531 SN74S532 SN54/74365A/366A/
Abstract: most other TTL logic families. All '166 and 'LS166A inputs are buffered to lower the drive requirements to one Series 54/74 or Series 54LS/74LS standard load, respectively. Input clamping diodes minimize , , Explanation of Logic Symbols Training Booklet (Rev. A) (SDYZ001A, 138 KB - Updated: 07/01/1996) Palladium Lead , accomplished on the low-to-high-level edge of the clock pulse through a two-input positive NOR gate permitting , NOTES Back to Top View Application Notes for Digital Logic q q q Designing With Logic (Rev. C Texas Instruments
Original
59629558301QEA 59629558301QFA SN54166J SNJ54166J 5962V 9558301QEA
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