74HC107PW Search Results
74HC107PW Price and Stock
Nexperia 74HC107PW,118IC FF JK TYPE DUAL 1BIT 14TSSOP |
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74HC107PW,118 | Reel | 2,500 |
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74HC107PW,118 | 2,189 |
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74HC107PW,118 | 5,729 | 1 |
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74HC107PW,118 | Reel | 5,000 |
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Nexperia 74HC107PW,112IC FF JK TYPE DUAL 1BIT 14TSSOP |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74HC107PW,112 | Tube |
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74HC107PW,112 | 21,984 | 1 |
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74HC107PW,112 | 1 | 3 |
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Nexperia 74HC107PW-Q100JIC FF JK TYPE DUAL 1BIT 14TSSOP |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74HC107PW-Q100J | Reel | 2,500 |
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74HC107PW-Q100J | Reel | 6 Weeks | 5,000 |
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74HC107PW-Q100J | 1,944 |
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74HC107PW-Q100J | 864 | 1 |
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74HC107PW-Q100J | Reel | 5,000 |
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74HC107PW-Q100J | 6 Weeks | 5,000 |
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Nexperia 74HC107PW118Flip Flop JK-Type Neg-Edge 2-Element 14-Pin TSSOP T/R - Tape and Reel (Alt: 74HC107PW,118) |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74HC107PW118 | Reel | 6 Weeks | 7,500 |
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74HC107PW118 | 6 Weeks | 7,500 |
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NXP Semiconductors 74HC107PW,11274HC107PW - J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, TSSOP14 |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74HC107PW,112 | 6,549 | 1 |
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74HC107PW Datasheets (8)
Part | ECAD Model | Manufacturer | Description | Curated | Type | |
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74HC107PW |
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Dual JK flip-flop with reset negative-edge trigger | Original | |||
74HC107PW |
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Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Scan | |||
74HC107PW,112 |
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Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger ; Fmax: 78 MHz; Logic switching levels: CMOS ; Number of pins: 14 ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 16@5V ns; Voltage: 2.0-6.0 V; Package: SOT402-1 (TSSOP14); Container: Tube | Original | |||
74HC107PW,118 |
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Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger ; Fmax: 78 MHz; Logic switching levels: CMOS ; Number of pins: 14 ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 16@5V ns; Voltage: 2.0-6.0 V; Package: SOT402-1 (TSSOP14); Container: Reel Pack, SMD, 13" | Original | |||
74HC107PW-Q100 |
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Dual JK flip-flop with reset; negative-edge trigger | Original | |||
74HC107PW-Q100J |
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74HC107PW-Q100 - 74HC107PW-Q100 - Dual JK flip-flop with reset; negative-edge trigger | Original | |||
74HC107PW-T |
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Dual JK flip-flop with reset negative-edge trigger | Original | |||
74HC107PW-T |
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Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Scan |