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ADCS7476AIMFE Texas Instruments 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6, SOT-23, 6 PIN visit Texas Instruments
SN7476J Texas Instruments IC TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, FF/Latch visit Texas Instruments
ADCS7476AIMFX/NOPB Texas Instruments 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP 6-SOT-23 -40 to 125 visit Texas Instruments Buy
ADCS7476AIMF/NOPB Texas Instruments 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP 6-SOT-23 -40 to 125 visit Texas Instruments Buy
ADCS7476AIMFE/NOPB Texas Instruments 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP 6-SOT-23 -40 to 125 visit Texas Instruments Buy
ADCS7476AISDX Texas Instruments 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, DSO6, LLP-6 visit Texas Instruments

7476 pin configuration

Catalog Datasheet MFG & Type PDF Document Tags

pin diagram of 7476

Abstract: 7476 J-K Flip-Flop 1LSul 10LSul PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEE/IEC) 76 LS76 E ®D 1OE *01 GE , Signetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with Individual J, K, Clock, Set and Reset inputs. The 7476 is , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f HAX , Flip-Flops 7476, LS76 LOGIC DIAGRAM FUNCTION TABLE INPUTS OPERATING MODE SD Asynchronous set
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pin diagram of 7476 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 PIN DIAGRAM 7476 N7476N N74LS76N 1N916 1N3064

ci 7476

Abstract: 7476 PIN DIAGRAM , Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the , Table. 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = , understood tobe40*iA l,H and-1.6mA l|L, and a74LS unit load (LSul) is20/uA lIH and -0.4mA l(L. PIN CONFIGURATION cp, [T 13 «i Soi Å' Do, »01 Å' 13 5, â ME jUsno VccÅ' j3k2 cpj [T mo2 SoîE ]Ã
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ci 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 PIN DIAGRAM input and output 7476 ttl LS 7476

pin diagram of 7476

Abstract: PIN CONFIGURATION 7476 . PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEE/IEC) 76 LS76 CP, U 33*1 D o , 1J , Signetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f MAx , 81501 Signetics Logic Products Product Specification Flip-Flops 7476, LS76 LOGIC DIAGRAM
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Jk 74ls76 pin out 7476 pin configuration TTL 7476 7476 signetics TTL 7476 logic diagram 7476 signetics

PIN CONFIGURATION 7476

Abstract: pin diagram of 7476 l|H and -0 .4 m A lIL. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEE/IEC) 76 LS76 CP , Sjgnetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , , forcing the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f , 5-114 853-0566 81501 Signetics Logic Products Product S pecification Flip-Flops 7476
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J-K Flip-Flop 7476 TTL 74ls76 74LS76 logic diagram Flip-Flop 7476 Diagram of 7476 Pin Configuration of 7476

jk flip flop 7476

Abstract: 7476 PIN DIAGRAM : PIN CONFIGURATION cp, [T 33*1 «di Å' Do, «oí E 5, JilZ ï3]qnd VccE cp2 (T mos SoîŠ, , Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the , understood to be 40>iA l,H and -1.6mA l,L. and a 74LS unit load (LSul) is 20juA l)H and -0.4mA l|L. 7476 , (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; TA = , Flip-Flops 7476, LS76 LOGIC DIAGRAM ld02900s FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS SD Rd
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74LS76 ttl Jk 7476 LS76 flip-flop 74ls76

7476 truth table

Abstract: 74ls76 jk flip-flop logic symbol and truth table '"1, > CP 6 â'"O >CP 16- Û -14 12 - K "O 0 -10 Vcc = Pin 5 GND = Pin 13 PIN CONFIGURATION CP, [T , 54/7476 54H/74H76 54LS/74LS76 LOGIC SYMBOL DESCRIPTION The "76" is a DualJK Flip-Flop with individual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 are positive pulse triggered flip-flops. JK , Information) PACKAGES PIN CONF. COMMERCIAL RANGES VCC = 5V ± 5%; TA = 0°C to *70°C MILITARY RANGES VCC = , operation. e. The J and K inputs of the 7476 and 74H76 must be stable while the Clock is HIGH for
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N74H76N S5476F 7476 truth table 74ls76 jk flip-flop logic symbol and truth table 74Ls76 truth table 74ls76 pin configuration N7476F N74H76F N74LS76F S54H76F

logic ic 7476 pin diagram

Abstract: and pin diagram of IC 7476 N7476F PIN CONFIGURATION Flatpak S5476W [T H ]o , m q i INPUT AND OUTPUT LOADING AND , 54/7476 54H/74H76 54LS/74LS76 DESCRIPTION The "76'' is a Dual JK Flip-Flop w ith individ ual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 are positive pulse triggered flip-flops. JK inform ation , PACKAGES PIN CONF. Fig A Fig A Fig A Fig A Fig A Fig A (See Section 9 for further Package and Ordering , V ± 1 0 % ; T a = - 5 5 ° C to *1 2 5 ° C V cc = Pin 5 GND = Pin 13 Plastic DIP N7476N ·
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logic ic 7476 pin diagram and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram pin diagram for IC 7476 pin configuration of 74LS76 IC IC 74LS76 S54LS76F S54H76W S54LS76W 54H/74H 54S/74S 54LS/74LS
Abstract: A Table Of Contents ^Arrays Pages Pin Grid Arrays / Zero Insertion Force PG A/ZIF PG , Module â'" SIMM IC-176 33-34 Dual Inline Memory M odule-DIMM (72 Pin) DIMM (100 Pin) DIMM (144 Pin) DIMM (160 Pin) DIMM (168 Pin) IC-554 IC-581 IC-497 IC-553 IC-438 35 36 37 , Package-BQFP (Clamshell) BQFP (Open Top) IC51 IC211 55-56 69-70 IC51 IC120 71-73 74-76 IC51 , (Clamshell) TSOP (Type 1, Open Top) TSOP (Type 2, Open Top) TSOP (MCR, 44 Pin, 0.8mm Pitch) Speciality -
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NP161 NP171 NP236 NP178 IC264 NP276

PIN CONFIGURATION 7476

Abstract: dc to dc chopper by thyristor solder pin flat base cable TO 220 case disc B C E F T 4.Letter maximum turn-off time 8 µs , after to DIN IEC turn-off: 747-6: 50 V/µs 50 V/µs 500 V/µs 500 V/µs 1000 V/µs 1000 V/µs 500 V , pin flat-base cable press-pack FF 200 R 12 K F FF FZ FS dual version single version six , Module 100 current rating IC G technology: G = IGBT-technology B Configuration: A = single switch
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dc to dc chopper by thyristor DIODE D180 thyristor control ic with current sense Half-Controlled Thyristor PIN CONFIGURATION single phase bridge rectifier pin configuration

2526N

Abstract: signetics 2526 SILICON GATE MOS 2500 SERES PIN CONFIGURATION (Top View) n/l packages 1. Output 6 2. Output 7 3 , INPUTS â'¢ TTL/DTL COMPATIBLE TRI-STATE OUTPUTS â'¢ Vcc"+5V,Vgq = -12V â'¢ 24-PIN SILICONE DIP â , scan. PART IDENTIFICATION PART OP. TEMP. RANGE PACKAGE 2526N 0-70°C 24-Pin Silicone DIP 25261 0-70°C 24-Pin Ceramic DIP 88 SIGNETfCS 64 X 9 X 9 ROM STATIC CHARACTER GENERATOR â  2526 MAXIMUM , . The 9x9 dot configuration for each character allows the 2526 to be used as a 7x9 character generator
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signetics 2526 7x9 decoder pin diagram decoder 7476 CM3940 CM3400 CHARACTER table application 24-PIN

7476 truth table

Abstract: 2526-N,! DESCRIPTION PIN CONFIGURATION The 2526 is a high speed 5 184-bit Static Read-Only Memory. It may be organized as 64x9x9 tor use as a character generator, or as a 512x9 ROM tor general purpose use. This device has TTL compatible inputs and outputs and requires+5V and -12 V power supplies , ' Blank Name 2 Data Cards Card No. 1 Column 1-9 10 11-19 20 21-29 73 74-76 77 , 11-19 20-70 71 72 73 74-76 77 78-80 Information Binary outputs of rows 9 through 1, (MSB at
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0I0I00I0I 0I00I0T0T NQISM3AN03 N-92S

pin diagram for jk flip flop 7476

Abstract: jk flip flop 7476 definition Clock J-K y -3V ,1.3V h-ov \l-3Y_¿Ã.3V HIGH data LOW data P-2 16-pin plastic DIL package P-5 16-pin Panaflat package (SO-16D) Pin configuration (top view) icp|T 1 Set [7 1 Reset [T , LS TTL DN74LS Series DN74LS76 DN74LS76 £>ivJ 74^76 Dual J-K Flip-Flops (with Set and Reset) I Description DN74LS76 contains two negative-edge triggered J-K flip-flop circuits, each with independent clock-CP, J, K, and direct-coupled set and reset input terminals. â  Features â'¢ Negative-edge
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pin diagram for jk flip flop 7476

jk flip flop 7476

Abstract: pin diagram for jk flip flop 7476 definition Clock J-K y -3V ,1.3V h-ov \l-3Y_¿Ã.3V HIGH data LOW data P-2 16-pin plastic DIL package P-5 16-pin Panaflat package (SO-16D) Pin configuration (top view) icp|T 1 Set [7 1 Reset [T , LS TTL DN74LS Series DN74LS76 DN74LS76 £>ivJ 74^76 Dual J-K Flip-Flops (with Set and Reset) I Description DN74LS76 contains two negative-edge triggered J-K flip-flop circuits, each with independent clock-CP, J, K, and direct-coupled set and reset input terminals. â  Features â'¢ Negative-edge
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thyristor tt 500 n 16

Abstract: thyristor phase control rectifier solder pin flat base cable TO 220 case disc B C E F T 4.Letter maximum turn-off time 8 µs , after to DIN IEC turn-off: 747-6: 50 V/µs 50 V/µs 500 V/µs 500 V/µs 1000 V/µs 1000 V/µs 500 V , pin flat-base cable press-pack FF 200 R 12 K F FF FZ FS dual version single version six , Module 100 current rating IC G technology: G = IGBT-technology B Configuration: A = single switch
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thyristor tt 500 n 16 thyristor phase control rectifier thyristor t 500 n 1800 thyristor tt 121 thyristor t 500 n 18 single phase thyristor controlled rectifier

EUPEC T 691 S 30 thyristor

Abstract: T 308 THYRISTOR pin flat base cable TO 220 case disc B C E F T 4.Letter maximum turn-off time 8 µs 10 , metric thread cable stud solder pin flat-base cable press-pack Avalanche Diode anode / case , : G = IGBT-technology B Configuration: A = single switch / diode B = Halfbridge D = 3-phase full , according immediately after to DIN IEC turn-off: 747-6: 50 V/µs 50 V/µs 500 V/µs 500 V/µs 1000 V
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EUPEC T 691 S 30 thyristor T 308 THYRISTOR EUPEC Thyristor h 198 s T 468 THYRISTOR EUPEC T 1078 F T 481 thyristor

all type of thyristor

Abstract: DISC THYRISTOR thread solder pin flat base cable TO 220 case disc B C E F T 4.Letter maximum turn-off , thread wire metric thread cable stud solder pin flat-base cable press-pack Avalanche Diode anode , : G = IGBT-technology B Configuration: A = single switch / diode B = Halfbridge D = 3-phase full , according immediately after to DIN IEC turn-off: 747-6: 50 V/µs 50 V/µs 500 V/µs 500 V/µs 1000 V
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all type of thyristor DISC THYRISTOR 1000 A thyristor TO 220 THYRISTOR FAST SWITCHING fast thyristor

single phase bridge fully controlled rectifier

Abstract: EUPEC DD 105 N 16 L .Letter mechanical construction anode: cathode: metric thread cable metric thread solder pin flat base cable , : critical rate of rise of forward voltage according immediately after to DIN IEC turn-off: 747-6: 50 , metric thread cable stud solder pin flat-base cable press-pack Avalanche Diode anode / case , Diode Module current rating IC = 100 A technology: G = IGBT-technology Configuration: A = single
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single phase bridge fully controlled rectifier EUPEC DD 105 N 16 L single phase fully controlled rectifier 3 phase rectifier circuit thyristor EUPEC tt 105 N 16 EUPEC DD 151 N 14 k

PS-20 pressure switch

Abstract: eupec phase control thyristor thread wire metric thread cable stud solder pin flat-base cable press-pack Avalanche Diode anode / case , construction anode: cathode: metric thread cable metric thread solder pin flat base cable TO 220 case disc , turn-off: 747-6: 50 V/ps 50 V/ps 500 V/ps 500 V/ps 1000 V/ps 1000 V/ps 500 V/ps 50 V/ps 1000 V/ps 500 V/ps , = 100 A technology: G = IGBT-technology Configuration: A = single switch / diode B = Halfbridge D =
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PS-20 pressure switch eupec phase control thyristor fast diode "40 A" thyristor short circuit
Abstract: Frequency Mixers print this page Notes: · For Surface Mount Environmental Specifications, please click here. SKY-60MH · General Quality Control Procedures and LO Power Level 13 dBm Pin Configuration Port LO RF IF Gnd Ext. Case Gnd Not Used je 1 5 7 2,3,4,6,8 - Environmental Specifications are given in MiniCircuits Guarantees Quality. Hi-Rel, MIL description are given in Hi-Rel and MIL without , 27.96 4710.53 217.17 37.29 4894.74 100.50 42.14 5078.95 64.17 42.02 5263.16 89.09 51.37 74.76 51.54 Mini-Circuits
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DC-1500
Abstract: W h a ì HEW LETT mLUM P A C K A R D Avantek Products Low Noise Surface Mount Amplifier 2000 to 6000 MHz Technical Data PPA-6213 Features Description Pin Configuration â'¢ U ltra Low N oise: 2.0 dB (T yp) The PPA-6213 is low current, high gain, low noise RF amplifier , surface mount configuration provides the user with excellent performance density in a 0.375" PlanarPak , Ang Mag Ang 159.06 -113.78 159.29 102.97 13.28 -74.76 -141.29 169.59 130.08 102.28 -
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PP-38
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