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Part Manufacturer Description Datasheet BUY
SN74196N-00 Texas Instruments TTL/H/L SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP14 visit Texas Instruments
SN74196J-00 Texas Instruments TTL/H/L SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, CDIP14 visit Texas Instruments
SN74196N-10 Texas Instruments TTL/H/L SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP14 visit Texas Instruments
SN74196J Texas Instruments TTL/H/L SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, CDIP14, CERAMIC, DIP-14 visit Texas Instruments
SN74196N Texas Instruments Asynchronous decade counters 14-PDIP 0 to 70 visit Texas Instruments
TTL-LOGIC-DATABOOK Texas Instruments TTL-LOGIC-DATABOOK visit Texas Instruments

74196 TTL

Catalog Datasheet MFG & Type PDF Document Tags

pin diagram decade counter 74196

Abstract: 74196 TTL TTL/MSI 93196/54196, 74196 93197/54197, 74197 HIGH SPEED DECADE AND BINARY COUNTER DESCRIPTION - The 93196/54196, 74196 and 93197/54197, 74197 High Speed Counters will provide either a divide-by-two and a divide-by-five counter (93196/54196, 74196) or a divide-by-two and a divide-by-eight counter , measured with all inputs grounded and all outputs open. 8-298 HIGH SPEED TTL/MSI . 93196/54196, 74196 â , +5.0 mA -0.5 V to +Vcc va|ue +30 mA 8-299 HIGH SPEED TTL/MSI . 93196/54196, 74196 â'¢ 93197/54197
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CI 74LS90

Abstract: ci 74193 10- CET TC t- CP MR Oo Qi 02 Ã3 TIMI 1 14 13 12 11 D125 54/74176, 54/74177, 54/74196, 54LS , DIGITAL TTL COUNTERS | Item Function DEVICE NO. Modulo Parallel Load * | Clock Transition i Max Clock , /74196 2x5 A "L 70 38 240 D125 3I,6A,9A 12 Asynchronous 54LS/74LS196 2x5 A "U 60 48 60 D125 3I,6A,9A 13 , asynchronous, S = synchronous 9-15 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS (Cont'd) Item , 17 4-Bit D Latch 54/74196 4xD L 1(L) 20 23 20 240 D125 3I,6A,9A 18 4-Bit D Latch 54LS/74LS196 4xD L
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74LS92 CI 74LS90 ci 74193 ci 74ls193 CI 74196 ci 7492 CI 74176 54/7490A 54LS/74LS90 S4/74293 54LS/74LS293 S4/7493A

sn 7492 ttl

Abstract: 74293 pin diagram 10- CET TC t- CP MR Oo Qi 02 Ã3 TIMI 1 14 13 12 11 D125 54/74176, 54/74177, 54/74196, 54LS , DIGITAL TTL COUNTERS | Item Function DEVICE NO. Modulo Parallel Load * | Clock Transition i Max Clock , /74196 2x5 A "L 70 38 240 D125 3I,6A,9A 12 Asynchronous 54LS/74LS196 2x5 A "U 60 48 60 D125 3I,6A,9A 13
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sn 7492 ttl 74293 pin diagram TTL 7493A TTL 74293 7493A 74162 54LS/74LS93 93L10 93S10 93L16 93S16 54LS/74LS160

TTL 74293

Abstract: 74LS90 FAIRCHILD DIGITAL TTL COUNTERS [Clock t o Q Output Delay-ns (Typ) Power Dissipation m W (Typ) Clock Transition Logic/Connection Diagram M ax Clock Rate MHz (Typ) Parallel Load * Function Modulo > IU Q 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous , /74290 54/7490A 54LS/74LS90 54/7492 74LS92 54/74293 54/7493A 54LS/74LS93 54/74176 54/74177 54/74196 54LS
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74LS90 D127 74290 7490 D124 74LS93 54LS/74LS197 54LS/74LS290 54LS/74LS390 54LS/74LS393 54LS/74LS490 93S05

CI 7474

Abstract: CI 7473 FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K â'ž 0 Cd D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 11 ~LT 2 â'" J SD 0 _6 14 0 4 â'" CP 12 , '" KC0 0 oL< 12_ O Vcc = Pin 5 GND = Pin 13 13-49 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL , ) 20 16 16 160 D149 3I 17 4-Bit D Latch 54/74196 4xD L 1(L) 20 23 20 240 D125 3I,6A,9A 18 4-Bit D
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CI 7474 CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 54H/74H74 54S/74S74 54LS/74LS74 54H/74H73 54LS/74LS73 54LS/74LS107

7475 D latch

Abstract: D146 12 Vcc = Pin 16 GND = Pin 8 13-53 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS (Cont'd , D149 3I 17 4-Bit D Latch 54/74196 4xD L 1(L) 20 23 20 240 D125 3I,6A,9A 18 4-Bit D Latch 54LS/74LS196
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7475 D latch D146 D147 74LS109 ci 7475 rs latch 54LS/74LS541 54LS/74LS78 54LS/74LS168 54LS/74LS169 54LS/74LS373 54LS/74LS374

TTL 74293

Abstract: 7490A , 02 03 03 TTTT 1 15 14 13 12 Vcc = Pin 16 GND = Pin 8 13-67 FAIRCHILD DIGITAL TTL COUNTERS , ,9A 10 Asynchronous 54/74177 2x8 A ~L 50 50 150 0125 3I,6A,9A 11 Asynchronous 54/74196 2x5 A "L 70
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7490A ttl 74LS173 74LS293 pin D188 D190 D194 54LS/74LS173 54LS/74LS375 54LS/74LS395

74LS160

Abstract: Synchronous 74163 FAIRCHILD DIGITAL TTL COUNTERS (Cont'd) Clock t o Q Output Delay-ns (Typ) I Max Clock Rate MHz (Typ) Power Dissipation m W (Typ) Logic/Connection Diagram Clock Transition Parallel Load* NO. E 1 2 3 4 Synchronous \/ Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Up/D own U p/D own Up/Down U p/D own Up/Down Up/Down U p/D own U p/D own , D125 54/74176, 54/74177, 54/74196, 54LS/74LS196, 54/74197, 54LS/74LS197 1 4 10 3 11 D126 9305
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74LS160 Synchronous 74163 74192 74LS190 pins 74LS193 74LS191 pins 54LS/74LS161 54LS/74LS162 54LS/74LS163 54LS/74LS192 54LS/74LS193 74LS190

TTL 74293

Abstract: 7490A FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL 14â'"0 Ko 15â'"O Ki 16â'"O K2 17â'"O k3 D114 9344 1» 18 4 5 23 22 21 20 Mi Mo Yi Yo Xo Xi X2 X3 So S2 S2 S3 S4 Ss TTTTTT 11 10 9 8 7 6 Vcc = Pin 24 GND = Pin 12 NC = Pin 1, 2, 3, 13 D115 93S43 7 8 5 4 3 1 19 18 17 16 X â'"1 *o X1 X2 , , 6 13-58 FAIRCHILD DIGITAL TTL COUNTERS | Item Function DEVICE NO. Modulo Parallel Load , ,9A 11 Asynchronous 54/74196 2x5 A "L 70 38 240 D125 3I,6A,9A 12 Asynchronous 54LS/74LS196 2x5 A "U
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93S62 74196 TTL D114 D115 D116 D117 93H87/74H87

ci 7475

Abstract: D147 FAIRCHILD LOGIC/CONNECTION DIAGRAMS D145 9370, 9374 DIGITAL -TTL 0146 9314, 93L14 D147 54/74279, 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 15 14 1 3 2 4 14 6 5 7 11 mijum Vcc E Do So Di Si D2 S2 D3 S3 MR Qo Ql 02 O3 TT 15 13 12 10 , Pin 16 GND = Pin 8 13-62 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS (Cont'd) Item , 17 4-Bit D Latch 54/74196 4xD L 1(L) 20 23 20 240 D125 3I,6A,9A 18 4-Bit D Latch 54LS/74LS196 4xD L
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74L576 TTL 7475 fairchild 9314 74LS78 pin diagram 7475 74279 54LS/74LS75 93L08 54LS/74LS77 54S/74S175 54LS/74LS175 54S/74S174

d146

Abstract: RS latch Pin 7 13-50 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS (Cont'd) Item Function DEVICE NO , 54/74196 4xD L 1(L) 20 23 20 240 D125 3I,6A,9A 18 4-Bit D Latch 54LS/74LS196 4xD L 1(L) 20 28 24 60
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74LS114 74LS112 74LS113 7475 data latch 74LS76 logic diagram 74ls112 pin diagram 54H/74H78 54H/74H106 54S/74S112 54LS/74LS112 54H/74H108 54S/74S113

74LS190 pins

Abstract: 74LS192 PIN diagram 10- CET TC t- CP MR Oo Qi 02 Ã3 TIMI 1 14 13 12 11 D125 54/74176, 54/74177, 54/74196, 54LS , DIGITAL TTL COUNTERS (Cont'd) Item Function DEVICE NO. Modulo Parallel Load* Clock Transition Max Clock
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74LS192 PIN diagram 74LS183 TTL 74ls163 74LS192 pins 74LS161 74160 54L8/74LS192 54LS/74L 74LS191

74LS93 P

Abstract: TTL 74LS93 12 Vcc = Pin 16 GND = Pin 8 13-53 FAIRCHILD DIGITAL TTL COUNTERS | Item Function DEVICE NO , 150 0125 3I,6A,9A 11 Asynchronous 54/74196 2x5 A "L 70 38 240 D125 3I,6A,9A 12 Asynchronous 54LS
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74LS93 P TTL 74LS93 74LS373 74176 74293 74LS490 54LS/74LS256

ic 7483 BCD adder

Abstract: Multiplexer IC 7483 are directly compatible w ith other TTL circuits such as the 8000 MSI circuits, 82/82S bipolar , conventional TTL processing to reduce storage time, PNP transistors can also be used to advantage by the circu , axim um of 1 second duration. BENEFITS · Compatible with 8000 series, 54/74, 54S/74S TTL as well as , use multiples of 7483's and Gates. Replaces 8280, 8290, T.l. 74176, T.l. 74196, FSC 93176, FSC 93196
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82S62 ic 7483 BCD adder Multiplexer IC 7483 4 bit bcd adder using ic 7483 IC 74196 transistor equivalent table SN29301

7408 CMOS

Abstract: TTL 7452 intervals along the row and column of the chip, also consist of I/O pads which are compatible of CMOS or TTL , Toggling Frequency: 40MHz â'¢ High density 3.5 micron geometries â'¢ TTL and CMOS I/O compatibility â , OF LS TTL TTL Pari No. Count TTL Part No. Count TTL Part No. Count TTL Part No. Count 7400 4 7470 , 74195 46 74374 74 7449 45 74135 24 74196 42 74375 16 7450 6 74136 12 74197 41 74376 40 7451 5 74138
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7408 CMOS TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 KG10000

STR W 5453 A

Abstract: STR 5453 TTL/MSI 9393/5493, 7493 4 -B IT BINARY COUNTER D E S C R IP T IO N -T h e T T L /M S I 9393/5 4 9 3 , 7493 is a 4-Bit Binary Counter consisting of four master/ slave flip-flops which are internally interconnected to provide a divide-by-two counter and a divide-by-eight counter. A gated direct reset line is provided which inhibits the count inputs and simultaneously returns the four flip-flop , 74150 74151 74152 74153 74164 74165 74180 74181 74182 74190 74191 74192 74193 74196 74197 74198 74H00
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STR W 5453 A STR 5453 STR W 5453 STR W 5453 C Truth Table 74190 Truth Table 74192

IC TTL 7432

Abstract: IC 7402, 7404, 7408, 7432, 7400 IC Tester Software version 2.08 Series 54/74 TTL ICs 7400 7401 7402 7403 7404 7405 7406 7407 , 74191 74192 74193 74194 74195 74196 74197 74198 74199 74200 74201 74224 74225 74230 74231 , the TTL section 4000 4001 4002 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016
ABI Electronics
Original
IC TTL 7432 IC 7402, 7404, 7408, 7432, 7400 ttl 74118 74189 memory ic 74138 74189 ttl memory TLC272 TLC274 TLC277 TLC279 TLC2872 TLE2061

IC 3-8 decoder 74138 pin diagram

Abstract: binary to gray code conversion using ic 74157 CODE TTL CODE 51 74196 52 74197 53 74198 54 74199 2-â'¢2 2 , /Vila are TTL level normal input buffers Vihb/Vilb are CMOS level normal input buffers Vmc/Vac are TTL , Min. Typ. Max, TTL level schmitt Trigger input threshold voltage VT+ - â'" 1,2 1.7 2.3 V VT- 0.8 , mm 1.0 1.5 2.0 ns 2ND (I: metal wiring length) 1.4 2.1 2.3 TTL level input buffer delay time , '" Type No. Function block name Logic function Max. No. of fan-outs Interface level TTL CMOS
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IC 3-8 decoder 74138 pin diagram binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder MSM91H000 72MS40

IC AND GATE 7408 specification sheet

Abstract: 74LS96 Support for TTL Macrofunctions Table 4. TTL Function Mappings in Altera-Provided LMFs (Part 1 o f 3 , Page 325 PLS-EDIF Data Sheet Table 4. TTL Function Mappings in Altera-Provided LMFs (Part 2 o , 74194 74195 74196 74197 74240 74241 74244 74251 74253 74257 74258 74259 Mentor Graphics 74LS114A 74LS133 , . TTL Function Mappings in Altera-Provided LMFs (Part 3 o f 3) MAX+PLUS 74260 74261 74273 74279 74280
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IC AND GATE 7408 specification sheet 74LS96 SN 74168 7486 XOR GATE IC 74LS192 74LS193 function table

74191, 74192, 74193 circuit diagram

Abstract: IC 7402, 7404, 7408, 7432, 7400 MAX+PLUSIITTL Macrofunction 74190 74191 74192 74193 74194 74195 74196 74197 74240 74241 74244 74251 74253 74257 , a NETED function to map. If no equivalent function currently exists in the MAX+PLUS II TTL , > Step 2: Design an equivalent circuit in AHDL if no equivalent function exists in the MAX+PLUS II TTL , relational operations. It is hierarchical, so that frequently used functions such as TTL and bus
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74191, 74192, 74193 circuit diagram Truth Table 74161 counter schematic diagram 74161 74244 uses and functions counter 74168 74191, 74192, 74193 HP400 IC-24 QIC-24
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