NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: fan-out delay per package per gate ns mW MIC 7430 NAND 1 8 13 10 10 MIC 7453 AND-OR-INVERT1 1 , Max. definition per inputs per inputs per toggle dissipation fan-out package flip-flop flip-flop , Max. Typ. Max. definition per package propagation frequency dissipation fan-out delay per , Logic Integrateci Circuits, MIC 7400 Series TTL Gates in order of gates per package Type , 7460 AND 2 4 5 8 42 MIC 7410 NAND 3 3 13 30 10 MIC 7400 NAND 4 2 13 40 10 MIC 7401 NAND 4 2 35 40 10 ... | OCR Scan |
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7420 NAND gate 7401 nand gate 7474 J-K Flip-Flop 7475 latch nand ttl 7400 7400 ttl 7410 7450 ttl 7402 TTL 7490 TTL 7400 propagation delay 7472 Flip-Flop Flip-Flop 7470 datasheet abstract |
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| Abstract: TTL SERIES 5400/7400 FEATURES • High speed (typical propagation delay 10 ns) combined with low power dissipation (typically 10mW per gate) • High fan-out - maximum 10 • High noise immunity - typically 1V at Tamb = 25°C • Low output impedance in both states • Supply voltage of 5V • Choice of three packages Typical Propagation Delay Temperature Range Package Series 5400 Series 5400J 5400J , 7400 Series 7400J 7400J Series 7400E 7400E 10ns 10ns 0 to + 70°C Oto + 70°C Ceramic Dual In-line (H14) Moulded ... | OCR Scan |
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10ns 5400F 5400J 7400J 7400E TTL 5400 7400 7400 ttl gate of 7400 Series - TTL 7400 series 7400 fan-out TTL 7400 propagation delay 7400 TTL TTL 7400 datasheet abstract |
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| Abstract: Fan-out: 20/tap max. â- Logic 0 Fan-out: 10/tap max. â- Power Dissipation: 740 MW max. Total Delay Part , 250 25.0 ±2.0 DDU-7-300 DDU-7-300 300 30.0 ±3.0 DDU-7-400 400 40.0 ±4.0 DDU-7-500 DDU-7-500 500 50.0 ±5.0 'Time delay ... | OCR Scan |
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DDU-7-500 DDU-7-100 DDU-7-150 DDU-7-20 DDU-7-200 DDU-7-25 DDU-7-250 DDU-7-300 DDU-7-400 DDU-7-50 7400 fan-out datasheet abstract |
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| Abstract: Logic 1 Fan-out: 20/tap max. â- Logic 0 Fan-out: 10/tap max. â- Power Dissipation: 740 MW max. Total , DDU-7-200 DDU-7-200 200 20.0 ±2.0 DDU-7-250 DDU-7-250 250 25.0 â- 2.0 DDU-7-300 DDU-7-300 300 30.0 -3.0 DDU-7-400 400 40.0 M.O ... | OCR Scan |
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DDU-7-500 DDU-7-10 DDU-7-100 DDU-7-150 DDU-7-20 DDU-7-200 DDU-7-25 DDU-7-250 DDU-7-300 DDU-7-400 DDU-7-50 7400 fan-out datasheet abstract |
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| Abstract: Fan-out: 20/tap max. â- Logic 0 Fan-out: 10/tap max. â- Power Dissipation: 740 MW max. Total Delay Part No. , DDU-7-300 DDU-7-300 300 30.0 ±3.0 DDU-7-400 400 40.0 ±4.0 DDU-7-500 DDU-7-500 500 50.0 ±5.0 'Vime delay referenced to 1st tap. ... | OCR Scan |
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datasheet abstract |
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| Abstract: Fan-out: 20/tap max. â- Logic 0 Fan-out: 10/tap max. â- Power Dissipation: 740 MW max. Total Delay Part No. , DDU-7-300 DDU-7-300 300 30.0 ±3.0 DDU-7-400 400 40.0 ±4.0 DDU-7-500 DDU-7-500 500 50.0 ±5.0 'Time delay referenced to Ist tap. ... | OCR Scan |
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datasheet abstract |
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| Abstract: : 0.5 V max. â- Logic 1 Fan-out: 20/tap max. â- Logic 0 Fan-out: 10/tap max. â- Power Dissipation: 740 , 200 20.0 ±2.0 DDU-7-250 DDU-7-250 250 25.0 ±2.0 DDU-7-300 DDU-7-300 300 30.0 ±3.0 DDU-7-400 400 40.0 ±4.0 DDU-7-500 DDU-7-500 ... | OCR Scan |
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DDU-7-500 DDU-7-100 DDU-7-150 DDU-7-20 DDU-7-200 DDU-7-25 DDU-7-250 DDU-7-300 DDU-7-400 DDU-7-50 DDU-7-10 datasheet abstract |
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| Abstract: 54/7400 v 54H/74H00 54H/74H00^f 54S/74S00 54S/74S00^// $ /V 54LS/74LS00 54LS/74LS00^ /^ QUAD 2-INPUT NAND GATE ORDERING CODE: See Section 9 INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions PINS Inputs Outputs 54/74 (U.L.) HIGH/LOW 1.0/1.0 20/10 54/74H 54/74H (U.L.) HIGH/LOW 1.25/1.25 12.5/12.5 54/74S 54/74S (U.L.) HIGH/LOW 1.25/1.25 25/12.5 54/74LS 54/74LS (U.L.) HIGH/LOW 0.5/0.25 10/5.0 (2.5) 00 PIN COMMERCIAL GRADE MILITARY GRADE PKG PKGS OUT Vcc = +5.0 V ±5%, Ta = 0° C to +70° C Vcc = +5.0 V ±10%, Ta = -55° C to +125°C TYPE ... | OCR Scan |
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ls 7400 74H00 74H00PC 7400 fan-out 74LS00D 74LS00P 74S00PC 7400DC 74H00DC 74LSOO 74LS00 pinout 74LS00 74LS00PC 7400PC 74LS00 7400 74S00 54H/74H00 54S/74S00 54H/74H00 abstract |
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| Abstract: Operating Free-Air Temperature Range -55 25 125 0 25 70 °C Normalized Fan-Out from Each Output, N 10 10 , FAIRCHILD TTL/SSI . 9N00/5400 9N00/5400, 7400 QUAD 2-INPUT NAND GATE logic and connection diagram dip (TOP VIEW) R pällTSl HI |îô| Fl m reà ra ULUüJLJLJÃœILJ Positive logic: Y = AB flatpak (TOP VIEW) GND 13 12 11 10 9 8 n n n ri n vccO- INPUTS ao- schematic diagram (EACH GATE) . 3.6 kSÃŽ â- RI E ti 1.6 kn R2 i , Output Short Circuit Current (Note 3) -20 -55 mA 9N00/5400 9N00/5400 Vcc = MAX. 5 -18 -55 mA 9N00/7400 'CCH ... | OCR Scan |
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7400 quad 2 input nand gate 7400 logic diagram tPHL 7400 TI TTL 5400 ttl nand gate 7400 quad 7400 fan-out 7400 quad 2-input NAND gate 9N00/5400 9N00/5400 abstract |
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| Abstract: AND FAN-OUT TABLE (See Note a) PINS 54/74 54H/74H 54H/74H 54S/74S 54S/74S 54LS/74LS 54LS/74LS Inputs llh I il ImAI 40 -1.6 50 , 54/7400 54H/74H00 54H/74H00 54S/74S00 54S/74S00 54LS/74LS00 54LS/74LS00 ORDERING CODE (See Section 9 for further Package and Ordering Information.) PIN CONFIGURATIONS PACKAGES PIN CONF. COMMERCIAL RANGES vcc = 5V ± 5%; Ta = 0°C to 70°C MILITARY RANGES Vcc = 5V ± 10%; TA = -55°C to *125°C Plastic DIP Fig. A Fig. A N7400N N7400N • N74H00N N74H00N N74S00N N74S00N • N74LS00N N74LS00N Ceramic DIP Fig. A Fig. A N7400F N7400F • N74H00F N74H00F N74S00F N74S00F • N74LS00F N74LS00F S5400F S5400F • S54H00F S54H00F ... | OCR Scan |
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N74S00N N74LS00 S5400 S5400W N7400F N7400N N74H00F 7400 family N74S00F N74LS00N N74LS00F N74H00N 74ls00 74H00 7400 fan-out 54H/74H00 54S/74S00 54H/74H00 abstract |
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| high fan-out signals, 3-state signals, and clocks inside a PLD device. The Â"Input/Output Functions are listed in alphanumeric order under each category. There are a number of standard TTL 7400-type functions in the different libraries. All 7400-type functions start with a Â"X74Â" prefix and are listed after Convention A carry-lookahead design accommodates large counters without extra gating. On TTL 7400-type Registers There are three TTL 7400-type data registers designed to function exactly as the TTL elements www.datasheetarchive.com/files/xilinx/docs/wcd00040/wcd04011.htm |
Xilinx | 16/02/1999 | 288.7 Kb | HTM | wcd04011.htm |
| |############################################################################## | TEXAS INSTRUMENTS INCORPORATED | Standard Linear and Logic Group | IBIS Model of CDC3RL02 CDC3RL02 CDC3RL02 CDC3RL02 | Low Phase-Noise Two Channel Clock Fan-Out Buffer | This file contains package information for the following: | WLBGA 8-pin (YEP_YZP) package as [Component] CDC3RL02 CDC3RL02 CDC3RL02 CDC3RL02_YEP_YZP | This device can be powered at the following Vccs: | 5 volt Vcc | 3.3 volt 2.7400e+00 3.8762e-04 4.5915e-04 1.3945e-04 2.7650e+00 www.datasheetarchive.com/download/91318899-917814ZC/schm006.zip (cdc3rl02.ibs) |
Texas Instruments | 26/08/2011 | 47.38 Kb | ZIP | schm006.zip |
| Da ta B oo k The Programmable Logic Data Book Click anywhere on this page to continue Success made simple 1996 On behalf of the employees of Xilinx, our sales representatives, our distributors, and our manufacturing partners, welcome to our 1996 Data Book, and thank you for your interest in Xilinx products and services. As the inventor of Field Programmable Gate Array technology and the world's leading supplier of programmable logic, we would like to pledge our continuing comm www.datasheetarchive.com/download/90212243-999460ZC/dbookold.zip (DBOOKOLD.PDF) |
Xilinx | 07/09/1996 | 10340.01 Kb | ZIP | dbookold.zip |