NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Clock Output (CO) and buffered Outputs from the 64th bit position (Q63, Q63>- Data from the selected , COMPLEMENTARY BUFFERED OUTPUTS AVAILABLE FROM 64TH STAGE PIN NAMES DO. S CP CO °63 063 Data Inputs Data Select Input Clock Input (L->H Edge-Triggered) Buffered Clock Output Buffered Output from the 64th Stage Complementary Buffered Output from the 64th Stage TRUTH TABLE s DO D1 Data Into Flip-Flop 1 L ... | OCR Scan |
2 pages, |
4031B 4000B 40318 64-STAGE 4031B abstract |
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| Abstract: 1 ; PWM PWM: MOV A,XXH MOV PWM0,A CLR PDC.0 SET PD.0 PWM: CLR PD.0 ;PD.0 PWM ; ; PWM ; ; elbanE - MWP noitpO ksaM PWM MWP 64 T7400AH T7400AH HT46 MCU PWM MWP UCM 64TH ... | Original |
1 pages, |
SCX62445XB HT46 MOV 510 HA0047T HA0047T abstract |
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| Abstract: 64th bit can be sequencially read out by adding data clock pulse. The output data is valid after a , pulse. The data are verified by making CE?VPP = V,L. The 2nd bit~the 64th bit are programmed by , The dummy bit is located after the practical use 64th bit. The address is 8 bits of 1000000-1000111. ... | OCR Scan |
6 pages, |
RF5H01 2003 8 PIN RP5H01 RF5H01/RP5H01 RF5H01 abstract |
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| Abstract: ), a buffered clock output (CO), and buffered outputs from the 64th bit position (O63, O63). The , output O63 buffered output from the 64th stage O63 Fig.2 Pinning diagram. data select input CP complementary buffered output from the 64th stage FAMILY DATA, IDD LIMITS category ... | Original |
7 pages, |
HE4000B HE4000B package hef package outlines information HEF4031B HEF4031BD HEF4031BP HEF4031BT IC04 LOCMOS HE4000B Logic Logic Package Outlines/Information HEF HEF40 The IC04 LOCMOS HE4000B Logic HE4000B abstract |
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| Abstract: Maximum Correction Time The maximum high side and low side correction times are expressed as 1/64th , from 1 to 7 of these 1/64th switching period fractions independently. Blanking When an NLR , Â Vout and for low side corrections VL is Vout. The blanking time units are VL times 1/64th ... | Original |
4 pages, |
ZL2005 AN2017 A-100 AN2017 abstract |
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| Abstract: 4731B/4731BX 4731B/4731BX QUAD 64-BIT 64-BIT STATIC SHIFT REGISTER DESCRIPTION - The 4731 B/4731 B/4731 BX_is a Quad 64-Bit Shift Register each with separate Serial Data Inputs (D^-Dq), Clock Inputs (CP^-CPd) and Data Outputs (Q63A"Q63D^ from the 64th register position. Information present on the Serial Data Inputs is shifted into the first register position and all the data in the register is shifted one position to the right on a , from the 64th Register Position LOGIC DIAGRAM 1/4 OF A 4731 B/4731 B/4731 BX ©o,©o,©cr© ©or®or(T>© Vpo= ... | OCR Scan |
2 pages, |
ZZJ15 4731B 4000B 4731B 4 bit 4731BX 4731B/4731BX 64-BIT B/4731 4731B/4731BX abstract |
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| Abstract: FIFO has valid data on its outputs. 5. The process is repeated through the 64th data word. IR goes LOW on the falling edge of the 64th SI and remains LOW indicating a full FIFO. Any further shift-ins are , output stage is busy. 4. Repeat process through the 64th SO pulse. OR stays LOW after 64th SO indicating , results in no change in the data on the outputs as the 64th word stays latched. 3. SO goes LOW, new data , tOR tFT O0 - 08 1st WORD tSOL tSOH 33rd PULSE 64th PULSE tOR / tD -ih X2nd WORD> ... | OCR Scan |
16 pages, |
SO-64 DO-8 ac723 74AC TRW1030 AC723 ACT723 54AC/74AC723 54ACT/74ACT723 AC723 abstract |
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| Abstract: Input or output is selected by SHLi terminal. B Data input/output terminals for 33rd tp 64th bits , input/putpyt control terminal(Pull-up R). H* or Open : Shift direction is from 33rd bit to 64th bit. "L" : Shift direction is from 64th bit to 33rd bit. 54 NC Non connection. 0005333 77T This Mate 10-268 ed ... | OCR Scan |
8 pages, |
NJU6417BF NJU6408B IOA2 7 segment display 542 application note NJU6417B JRC 8 pin NJU641 64-OUT NJU641 abstract |
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| Abstract: I OB 1 lOBz |hta input/output terminals for 33rd to 64th bits shift register. Display data is input , I{Pull-up R). "H or Open : Shift direction is from 33rd bit to 64th bit. "L" : Shift direction is from 64th bit to 33rd bit. 54 HC Non connection. NewdapanRadio Co.Ud. m bSb^flflB â-¡â-¡â-¡b33fi mi â- ... | OCR Scan |
8 pages, |
NJU6417CF NJU6417C NJU6408B NJU6407C LM 4088 32-bit shift register 64-OUT NJU6417C abstract |
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| Abstract: selected by SHLi terminal. 32 74 ! OB, IOB2 Data input/output terminals for 33rd to 64th bits shift , direction and input/output control terminal(PulI-up R). H or Open : Shift direction is from 33rd bit to 64th bit. "L" : Shift direction is from 64th bit to 33rd bit. 54 NC Non connection. New gapa* Radio ... | OCR Scan |
8 pages, |
NJU6417CF NJU6417C NJU6408B LM driver 100PF LF 1/16A 32-bit shift register 64-OUT NJU6408B- 64-OUT abstract |
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| Abstract: input reference clock rate at 1/16th client-side baud rate (625.0 to 707.5 MHz) or 1/64th client-side ... | Original |
2 pages, |
SMI10021 SMI10021 abstract |
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| Abstract: - 161 - 451 7B Dual 64 Bit Static Shift Register 1 '6 1 15 â- 8MB »a Xr-y 64t' / h X2 f Ail umi' asij x'JTMl' 7 ... | OCR Scan |
1 pages, |
UPD4517BC SCL4517B MN4517B MC14517B HEF4517BP HD14517B HCC4517B CD4517B datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| FLASH D39 CIRCLE D=27th FLASH D40 CIRCLE D=64th =104th H=44th FLASH D56 SMT W=44th H=64th 05 55th (0-15) T06 30th (0-15) T07 64th (0-15) T08 70th (0-15) Manufacturing Notes H=39th FLASH D45 SMT W=39th H=44th FLASH D46 SMT W=64th H=44th FLASH D47 SMT W=47.3th H=15.2th www.datasheetarchive.com/download/21772778-364938ZC/1652a.zip (DC1652A - CADCAM READ-ME.TXT) |
Linear | 28/07/2011 | 1973.96 Kb | ZIP | 1652a.zip |
| DRAW D34 CIRCLE D=2th DRAW D35 SMT W=44th H=64th FLASH D43 SMT W=100th H=100th FLASH D44 CIRCLE D=64th 03 94th (0-15) T04 64th (0-15) T05 40th (0-15) T06 70th (0-15) [END OF FILE] www.datasheetarchive.com/download/7268221-365403ZC/dc1699a.zip (DC1699A - CADCAM READ-ME.TXT) |
Linear | 06/10/2011 | 1998.07 Kb | ZIP | dc1699a.zip |
| FLASH D37 CIRCLE D=27th FLASH D38 CIRCLE D=64th H=84th FLASH D43 SMT W=39th H=44th FLASH D44 SMT W=64th H=44th FLASH D45 SMT W=47.3th H=15.2th www.datasheetarchive.com/download/95431500-364747ZC/1393b.zip (DC1393B - CADCAM READ-ME.TXT) |
Linear | 12/01/2010 | 906.88 Kb | ZIP | 1393b.zip |
| HEF4517B HEF4517B HEF4517B HEF4517B_CNV_3 Product information page HEF4517B HEF4517B HEF4517B HEF4517B LSI; Dual 64-bit static shift register General info The HEF4517B HEF4517B HEF4517B HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D, )parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O 16 to O 64 ). Data at www.datasheetarchive.com/files/philips/pip/hef4517b_cnv_3-v2.html |
Philips | 15/06/2005 | 3.92 Kb | HTML | hef4517b_cnv_3-v2.html |
| HEF4517B HEF4517B HEF4517B HEF4517B_CNV_3 Product information page HEF4517B HEF4517B HEF4517B HEF4517B LSI; Dual 64-bit static shift register General info The HEF4517B HEF4517B HEF4517B HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D, )parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O 16 to O 64 ). Data at the D input is entered into the first bit on the LOW to HIGH www.datasheetarchive.com/files/philips/pip/hef4517b_cnv_3.html |
Philips | 23/04/2003 | 5.05 Kb | HTML | hef4517b_cnv_3.html |
| HEF4517B HEF4517B HEF4517B HEF4517B_CNV_3 HEF4517B HEF4517B HEF4517B HEF4517B LSI Dual 64-bit static shift register The HEF4517B HEF4517B HEF4517B HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D, )parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O 16 to O 64 ). Data at the D input is entered www.datasheetarchive.com/files/philips/pip/hef4517b_cnv_3-v1.html |
Philips | 14/02/2002 | 13.14 Kb | HTML | hef4517b_cnv_3-v1.html |
| 03 64th (0-15) T04 30th (0-15) T05 35th (0-15) T06 125th (0-15) [END OF FILE] www.datasheetarchive.com/download/91914832-364534ZC/1063a.zip (6559demo - CADCAM READ-ME.TXT) |
Linear | 22/09/2009 | 26.04 Kb | ZIP | 1063a.zip |
| . T01 94th (0-15) T02 64th (0-15) T03 70th (0-15) T04 20th (0-15) [END OF FILE] www.datasheetarchive.com/download/71244800-364966ZC/1698a.zip (DC16980-gbr - CADCAM READ-ME.TXT) |
Linear | 14/01/2011 | 508.7 Kb | ZIP | 1698a.zip |
| -15) T02 20th (0-15) T03 94th (0-15) T04 64th (0-15) T05 40th (0-15) T06 70th (0-15) [END OF www.datasheetarchive.com/download/46311033-364942ZC/1659a.zip (DC1659a-gbr - CADCAM READ-ME.TXT) |
Linear | 18/08/2011 | 636.14 Kb | ZIP | 1659a.zip |
| . T01 20th (0-15) T02 55th (0-15) T03 200th (0-15) T04 30th (0-15) T05 64th (0-15) T06 70th (0 www.datasheetarchive.com/download/55898923-364937ZC/1651a.zip (DC1651A - CADCAM READ-ME.TXT) |
Linear | 28/07/2011 | 2027.6 Kb | ZIP | 1651a.zip |