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64th

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Abstract: Clock Output (CO) and buffered Outputs from the 64th bit position (Q63, Q63>- Data from the selected , COMPLEMENTARY BUFFERED OUTPUTS AVAILABLE FROM 64TH STAGE PIN NAMES DO. S CP CO °63 063 Data Inputs Data Select Input Clock Input (L->H Edge-Triggered) Buffered Clock Output Buffered Output from the 64th Stage Complementary Buffered Output from the 64th Stage TRUTH TABLE s DO D1 Data Into Flip-Flop 1 L ... OCR Scan
datasheet

2 pages,
74.51 Kb

di 765 h 4000B 4031B 40318 64-STAGE 4031B abstract
datasheet frame
Abstract: 1 ; PWM PWM: MOV A,XXH MOV PWM0,A CLR PDC.0 SET PD.0 PWM: CLR PD.0 ;PD.0 PWM ; ; PWM ; ; elbanE - MWP noitpO ksaM PWM MWP 64 T7400AH T7400AH HT46 MCU PWM MWP UCM 64TH ... Original
datasheet

1 pages,
48.95 Kb

SCX62445XB HT46 MOV 510 HA0047T HA0047T abstract
datasheet frame
Abstract: the 64th bit position (0 $ 3 , 063)« Data from the selected Data Inputs (D q or D j), as determined b , 64TH S T A G E L O G IC S Y M B O L is 1 1 1 Do 01 10- 2- S 40318 CP CO 0 63 Qß3 0- , Buffered Output from the 64th Stage Complementary Buffered Output from the 64th Stage TRUTH TABLE S L L H H ... OCR Scan
datasheet

2 pages,
148.9 Kb

40EA7S7 40EA7S7 abstract
datasheet frame
Abstract: 4031B 4031B 64-STAGE 64-STAGE STATIC SHIFT REGISTER D E S C R IP TIO N - The 4 0 3 1 B is an edge-triggered 64-Stage Static S h ift Register w ith tw o Serial Data Inputs (Dq, D } ) , a Data Select Input (S), a Clock Input (CP), a buffered Clock Output (CO) and buf fered Outputs from the 64th bit position (Q 6 3 , 0631Data from the selected Data Inputs (D q or D j ) , as determined by the state of the Select Input (S , Clock Output Buffered Output from the 64th Stage Complementary Buffered O utput from the 64th Stage T R ... OCR Scan
datasheet

2 pages,
120.74 Kb

4031B 64-STAGE 4031B abstract
datasheet frame
Abstract: ), a buffered clock output (CO), and buffered outputs from the 64th bit position (O63, O63). The , output O63 buffered output from the 64th stage O63 Fig.2 Pinning diagram. data select input CP complementary buffered output from the 64th stage FAMILY DATA, IDD LIMITS category ... Original
datasheet

7 pages,
73.81 Kb

64-STAGE HE4000B HE4000B package hef package outlines information HEF4031B HEF4031BD HEF4031BT IC04 LOCMOS HE4000B Logic Logic Package Outlines/Information HEF HEF4031BP HEF40 The IC04 LOCMOS HE4000B Logic HE4000B abstract
datasheet frame
Abstract: HEF4031B HEF4031B MSI 64-STAGE 64-STAGE STATIC SHIFT REGISTER The HEF4031B HEF4031B is an edge-triggered 64-stage static shift register with two serial data inputs (Da, Dg!, a data select input S/B, a clock input (CP), a buffered clock output (CO), and buffered outputs from the 64th bit position (0 @ 3 , 0 6 3 ). The output O53 is capable of driving one TTL load. Data from or Dg, as determined by the state of S/B, is , ) buffered clock output buffered output from the 64th stage complementary buffered output from the 64th stage ... OCR Scan
datasheet

6 pages,
151.17 Kb

HEF4031B 64-STAGE HEF4031B abstract
datasheet frame
Abstract: Maximum Correction Time The maximum high side and low side correction times are expressed as 1/64th , from 1 to 7 of these 1/64th switching period fractions independently. Blanking When an NLR , ­ Vout and for low side corrections VL is Vout. The blanking time units are VL times 1/64th ... Original
datasheet

4 pages,
115.78 Kb

ZL2005 Zilker Labs Intersil - Medical Application AN2017 A-100 AN2017 abstract
datasheet frame
Abstract: 64th bit can be sequencially read out by adding data clock pulse. The output data is valid after a , pulse. The data are verified by making CE?VPP = V,L. The 2nd bit~the 64th bit are programmed by , The dummy bit is located after the practical use 64th bit. The address is 8 bits of 1000000-1000111. ... OCR Scan
datasheet

6 pages,
126.71 Kb

RF5H01 2003 8 PIN RP5H01 datasheet abstract
datasheet frame
Abstract: 4731B/4731BX 4731B/4731BX QUAD 64-BIT 64-BIT STATIC SHIFT REGISTER DESCRIPTION - The 4731 B/4731 B/4731 BX_is a Quad 64-Bit Shift Register each with separate Serial Data Inputs (D^-Dq), Clock Inputs (CP^-CPd) and Data Outputs (Q63A"Q63D^ from the 64th register position. Information present on the Serial Data Inputs is shifted into the first register position and all the data in the register is shifted one position to the right on a , from the 64th Register Position LOGIC DIAGRAM 1/4 OF A 4731 B/4731 B/4731 BX ©o,©o,©cr© ©or®or(T>© Vpo= ... OCR Scan
datasheet

2 pages,
56.46 Kb

ZZJ15 U63A 4731B 4731 4000B a 4731 4731B 4 bit 4731BX 4731B/4731BX 64-BIT 14-PIN 4731B/4731BX abstract
datasheet frame
Abstract: FIFO has valid data on its outputs. 5. The process is repeated through the 64th data word. IR goes LOW on the falling edge of the 64th SI and remains LOW indicating a full FIFO. Any further shift-ins are , output stage is busy. 4. Repeat process through the 64th SO pulse. OR stays LOW after 64th SO indicating , results in no change in the data on the outputs as the 64th word stays latched. 3. SO goes LOW, new data , tOR tFT O0 - 08 1st WORD tSOL tSOH 33rd PULSE 64th PULSE tOR / tD -ih X2nd WORD> ... OCR Scan
datasheet

16 pages,
405.23 Kb

SO-64 DO-8 ac723 74AC723 74AC TRW1030 AC723 ACT723 54AC/74AC723 54ACT/74ACT723 AC723 abstract
datasheet frame
Abstract: input reference clock rate at 1/16th client-side baud rate (625.0 to 707.5 MHz) or 1/64th client-side ... Original
datasheet

2 pages,
278.71 Kb

SMI10021 SMI10021 abstract
datasheet frame
Abstract: - 161 - 451 7B Dual 64 Bit Static Shift Register 1 '6 1 15 - 8MB »a Xr-y 64t' / h X2 f Ail umi' asij x'JTMl' 7 ... OCR Scan
datasheet

1 pages,
35.98 Kb

UPD4517BC SCL4517B RCA H 715 MN4517B MC14517B HEF4517BP HD14517B HCC4517B CD4517B datasheet abstract
datasheet frame
Abstract: selected by SHLi terminal. 32 74 ! OB, IOB2 Data input/output terminals for 33rd to 64th bits shift , direction and input/output control terminal(PulI-up R). H or Open : Shift direction is from 33rd bit to 64th bit. "L" : Shift direction is from 64th bit to 33rd bit. 54 NC Non connection. New gapa* Radio ... OCR Scan
datasheet

8 pages,
208.53 Kb

NJU6417CF NJU6417C NJU6408B LM driver iobi 100PF LF 1/16A Jrc 5668 32-bit shift register datasheet abstract
datasheet frame

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No abstract text available
www.datasheetarchive.com/download/21772778-364938ZC/1652a.zip (DC1652A - CADCAM READ-ME.TXT)
Linear 28/07/2011 1973.96 Kb ZIP 1652a.zip
No abstract text available
www.datasheetarchive.com/download/7268221-365403ZC/dc1699a.zip (DC1699A - CADCAM READ-ME.TXT)
Linear 06/10/2011 1998.07 Kb ZIP dc1699a.zip
No abstract text available
www.datasheetarchive.com/download/95431500-364747ZC/1393b.zip (DC1393B - CADCAM READ-ME.TXT)
Linear 12/01/2010 906.88 Kb ZIP 1393b.zip
HEF4517B HEF4517B HEF4517B HEF4517B LSI Dual 64-bit static shift register The HEF4517B HEF4517B HEF4517B HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D, )parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O 16 to O 64 ). Data at the D input is entered
www.datasheetarchive.com/files/philips/pip/hef4517b_cnv_3-v3.html
Philips 06/12/2000 6.87 Kb HTML hef4517b_cnv_3-v3.html
Product information page HEF4517B HEF4517B HEF4517B HEF4517B LSI; Dual 64-bit static shift register General info The HEF4517B HEF4517B HEF4517B HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D, )parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O 16 to O 64 ). Data at
www.datasheetarchive.com/files/philips/pip/hef4517b_cnv_3-v2.html
Philips 15/06/2005 3.92 Kb HTML hef4517b_cnv_3-v2.html
No abstract text available
www.datasheetarchive.com/download/91914832-364534ZC/1063a.zip (6559demo - CADCAM READ-ME.TXT)
Linear 22/09/2009 26.04 Kb ZIP 1063a.zip
No abstract text available
www.datasheetarchive.com/download/71244800-364966ZC/1698a.zip (DC16980-gbr - CADCAM READ-ME.TXT)
Linear 14/01/2011 508.7 Kb ZIP 1698a.zip
Product information page HEF4517B HEF4517B HEF4517B HEF4517B LSI; Dual 64-bit static shift register General info The HEF4517B HEF4517B HEF4517B HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D, )parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O 16 to O 64 ). Data at the D input is entered into the first bit on the LOW to HIGH transition of the clock
www.datasheetarchive.com/files/philips/pip/hef4517b_cnv_3.html
Philips 23/04/2003 5.05 Kb HTML hef4517b_cnv_3.html
HEF4517B HEF4517B HEF4517B HEF4517B LSI Dual 64-bit static shift register The HEF4517B HEF4517B HEF4517B HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D, )parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O 16 to O 64 ). Data at the D input is entered
www.datasheetarchive.com/files/philips/pip/hef4517b_cnv_3-v1.html
Philips 14/02/2002 13.14 Kb HTML hef4517b_cnv_3-v1.html
No abstract text available
www.datasheetarchive.com/download/46311033-364942ZC/1659a.zip (DC1659a-gbr - CADCAM READ-ME.TXT)
Linear 18/08/2011 636.14 Kb ZIP 1659a.zip