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64th

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 4031B 4031B 64-STAGE 64-STAGE STATIC SHIFT REGISTER DESCRIPTION — The 4031B 4031B is an edge-triggered 64-Stage Static Shift Register with two Serial Data Inputs (Do, a Data Select Input (S), a Clock Input (CP), a buffered Clock Output (CO) and buffered Outputs from the 64th bit position (Q63, Q63>- Data from the , €¢ TRUE AND COMPLEMENTARY BUFFERED OUTPUTS AVAILABLE FROM 64TH STAGE PIN NAMES DO. S CP CO °63 063 , Output from the 64th Stage Complementary Buffered Output from the 64th Stage TRUTH TABLE s DO D1 Data ... OCR Scan
datasheet

2 pages,
74.51 Kb

di 765 h 4000B 4031B 40318 64-STAGE TEXT
datasheet frame
Abstract: causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW. When the FIFO is full, HF , process is repeated through the 64th data word. On the rising edge of the 33rd SI, FULL flag goes HIGH , rising edge of the 64th pulse indicating that the FIFO is full. Any further shift-ins are disabled. 33rd PULSE 64th PULSE _ DATA VALID DC 1st DATA WORD Note: SO and OE are LOW; MR is HIGH. FIGURE 1 , , tpj, after SO falls. Repeat process through the 64th SO pulse. FULL flag goes LOW one propagation ... OCR Scan
datasheet

13 pages,
300.12 Kb

N28B 74ACT2708PC 74ACT2708 64x9 RAM TEXT
datasheet frame
Abstract: the 64th bit position (0 $ 3 , 063)« Data from the selected Data Inputs (D q or D j), as determined b , 64TH S T A G E L O G IC S Y M B O L is 1 1 1 Do 01 10- 2- S 40318 CP CO 0 63 Qß3 0 , Buffered Output from the 64th Stage Complementary Buffered Output from the 64th Stage TRUTH TABLE S L L H H ... OCR Scan
datasheet

2 pages,
148.9 Kb

40EA7S7 TEXT
datasheet frame
Abstract: edge of the 33rd SI causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW , falls, indicating the FIFO is no longer empty. The process is repeated through the 64th data word , a half-full FIFO. HF goes LOW propagation delay tIF after the rising edge of the 64th pulse , propagation delay, tOR, after SO falls and HF rises one propa- Repeat process through the 64th SO pulse , FIFO is less than half full. On the falling edge of the 64th SO, HF goes LOW one propagation delay, t ... Fairchild Semiconductor
Original
datasheet

14 pages,
189.09 Kb

N28B 74ACT2708PC 74ACT2708 TEXT
datasheet frame
Abstract: is repeated through the 64th data word. IR goes LOW on the falling edge of the 64th SI and remains , . Repeat process through the 64th SO pulse. OR stays LOW after 64th SO indicating an empty FIFO. The SO , data on the outputs as the 64th word stays latched. 3. SO goes LOW, new data reaches output , 1st WORD tSOL tSOH 33rd PULSE 64th PULSE tOR / tD -ih X2nd WORD> ... OCR Scan
datasheet

16 pages,
405.23 Kb

Trw 1030 SO-64 DO-8 74AC 74AC723 ac723 TRW1030 AC723 ACT723 54AC/74AC723 54ACT/74ACT723 TEXT
datasheet frame
Abstract: SI causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW. Data Inputs , . The process is repeated through the 64th data word. On the rising edge of the 33rd SI, FULL flag goes , after the rising edge of the 64th pulse indicating that the FIFO is full. Any further shift-ins are , . IR is LOW. 4. Repeat process through the 64th SO pulse. FULL flag goes LOW one propagation delay , falling edge of the 64th SO, HF goes LOW one propagation delay, tOE, after SO, indicating the FIFO is ... Fairchild Semiconductor
Original
datasheet

13 pages,
93.05 Kb

N28B 74ACT2708PC 74ACT2708 DIODE HF 20 TEXT
datasheet frame
Abstract: outputs. 5. The process is repeated through the 64th data word. IR goes LOW on the falling edge of the 64th SI and remains LOW indicating a full FIFO. Any further shift-ins are disabled. Figure 1: Modes of Operation Mode 1 1st PULSE 33rd PULSE 64th PULSE tSIL tSIH SI IR D O · D8 OR O O - , process through the 64th SO pulse. OR stays LOW after 64th SO indicating an empty FIFO. The SO pulse may , the outputs as the 64th word stays latched. Figure 4: Modes of Operation Mode 4 Note: SI and 5 E ... OCR Scan
datasheet

16 pages,
391.33 Kb

TRW10 NE 5322 AC723 ACT723 54AC/74AC723 54ACT/74ACT723 TEXT
datasheet frame
Abstract: causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW. When the FIFO is full , . The process is repeated through the 64th data word. On the rising edge of the 33rd SI, FULL flag goes , after the rising edge of the 64th pulse indicating that the FIFO is full. Any further shift-ins are disabled. Figure 1: Modes of Operation Mode 1 1st PULSE ts,L 1 tSIH 33rd PULSE 64th PULSE DO - D8 , . 4. Repeat process through the 64th SO pulse. FULL flag goes LOW propagation delay tOHF after the ... OCR Scan
datasheet

18 pages,
489.99 Kb

SO-64 ACT708 TLR 308 t3f 185 ac708 74ACT708 74AC708 AC708 54AC/74AC708 54ACT/74ACT708 TEXT
datasheet frame
Abstract: expressed as 1/64th fractions of the total switching period (1/fSW). The high side and low side correction times can be set from 1 to 7 of these 1/64th switching period fractions independently. Blanking , 1/64th fractions of the total switching period (1/fSW). A minimum blanking time is set by the ... Intersil
Original
datasheet

4 pages,
115.78 Kb

ZL2005 Zilker Labs Intersil - Medical Application AN2017 A-100 TEXT
datasheet frame
Abstract: 4031B 4031B 64-STAGE 64-STAGE STATIC SHIFT REGISTER D E S C R IP TIO N - The 4 0 3 1 B is an edge-triggered 64-Stage Static S h ift Register w ith tw o Serial Data Inputs (Dq, D } ) , a Data Select Input (S), a Clock Input (CP), a buffered Clock Output (CO) and buf fered Outputs from the 64th bit position (Q , Edge-Triggered) Buffered Clock Output Buffered Output from the 64th Stage Complementary Buffered O utput from the 64th Stage T R U T H T A B LE S L L H H D0 L H X X L H X D1 X X L H = Low Level = High Levef = Don't ... OCR Scan
datasheet

2 pages,
120.74 Kb

4031B 64-STAGE TEXT
datasheet frame
Abstract: HF to go HIGH, the rising edge of the 33rd SI causes FULL to go HIGH, and the rising edge of the 64th , through the 64th data word. On the rising edge of the 33rd SI, FULL flag goes HIGH prop agation delay tiHF , 64th pulse indicating that the FIFO is full. Any further shift-ins are disabled. 33rd PULSE 64th PULSE , 4-353 2708 Functional Description (Continued) 4. Repeat process through the 64th SO pulse. FU , FIFO is less than half full. On the falling edge of the 64th SO, HF goes LOW one propagation delay, toE ... OCR Scan
datasheet

17 pages,
445.8 Kb

mr 044 74AC2708 74ACT2708 ACT2708 TEXT
datasheet frame
Abstract: , and the ris­ ing edge of th e 64th SI causes HF to go LOW. Data Inputs (D q D 8) Data inputs for , the falling edge of SI The process is repeated through the 64th data word. On th e rising edge of , propagation delay t|p after the ris­ SI goes HIGH: input stage is busy. ing edge of th e 64th pulse , e output. IR is LOW. Repeat process through the 64th S O pulse. FU LL flag goes LOW one , less than half full. On th e falling edge of th e 64th SO, HF goes LOW one propagation delay, toE- a ... OCR Scan
datasheet

13 pages,
148.68 Kb

TEXT
datasheet frame
Abstract: edge of the 33rd SI causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW , of Operation 5. The process is repeated through the 64th data word. On the rising edge of the , LOW propagation delay Hf after the rising edge of the 64th pulse indicating that the FIFO is full , through the 64th SO pulse. FULL flag goes LOW propagation delay tOHF after the rising edge of 33rd SO, indicating that the FIFO is less than half full. On the falling edge of the 64th SO, HF goes LOW ... OCR Scan
datasheet

18 pages,
537.93 Kb

AC708 ACT708 54AC/74AC708 54ACT/74ACT708 TEXT
datasheet frame
Abstract: go HIGH, the rising edge o f the 33rd SI causes FULL to go HIGH, and the rising edge o f the 64th SI , ng er em pty. 5. The process is repeated through the 64th data word. On the rising edge o f the 33rd , goes LOW propagation delay tiF a fte r the rising edge o f the 64th pulse in d ica tin g that the FIFO , tsm tslH -hh 33rd PULSE 64th PULSE th DO - Da DATA VALID / "Y W H > tIHF >! - O C D , through the 64th SO pulse. FULL flag goes LOW propagation delay tOHF after the rising edge o f 33rd SO, in ... OCR Scan
datasheet

18 pages,
457.05 Kb

T3F 07 AC708 ACT708 54AC/74AC708 54ACT/74ACT708 TEXT
datasheet frame

Archived Files

Abstract Saved from Date Saved File Size Type Download
HEF4517B HEF4517B_CNV_3 Product information page HEF4517B HEF4517B LSI; Dual 64-bit static shift register General info The HEF4517B HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D, )parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O 16 to O 64 ). Data at the D input is
/datasheets/files/philips/pip/hef4517b_cnv_3-v2.html
Philips 15/06/2005 3.92 Kb HTML hef4517b_cnv_3-v2.html
HEF4517B HEF4517B_CNV_3 Product information page HEF4517B HEF4517B LSI; Dual 64-bit static shift register General info The HEF4517B HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D, )parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O 16 to O 64 ). Data at the D input is entered into the first bit on the LOW to HIGH transition of
/datasheets/files/philips/pip/hef4517b_cnv_3.html
Philips 23/04/2003 5.05 Kb HTML hef4517b_cnv_3.html
HEF4517B HEF4517B_CNV_3 HEF4517B HEF4517B LSI     Dual 64-bit static shift register The HEF4517B HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D, )parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O 16 to O 64 ). Data at the D input is entered into
/datasheets/files/philips/pip/hef4517b_cnv_3-v1.html
Philips 14/02/2002 13.14 Kb HTML hef4517b_cnv_3-v1.html
No abstract text available
/download/52606529-223429ZC/chap08.doc
Intel 05/09/1997 151.08 Kb DOC chap08.doc
following the 16th, 32nd, 48th, and 64th stages. These taps also serve as input points allowing data to be
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/2081.htm
STMicroelectronics 20/10/2000 11.65 Kb HTM 2081.htm
, data, and write enable input and out- puts accessible at taps following the 16th, 32nd, 48th, and 64th
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/2081-v2.htm
STMicroelectronics 14/06/1999 9.22 Kb HTM 2081-v2.htm
, data, and write enable input and out- puts accessible at taps following the 16th, 32nd, 48th, and 64th
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/2081-v1.htm
STMicroelectronics 02/04/1999 9.25 Kb HTM 2081-v1.htm
64th stages. These taps also serve as input points allowing data to be inputted at the 17th, 33rd
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/2081-v3.htm
STMicroelectronics 25/05/2000 11.08 Kb HTM 2081-v3.htm
No abstract text available
/download/28598201-223430ZC/chap08.rtf
Intel 27/06/1997 346.17 Kb RTF chap08.rtf
:run djnz step_dividel,:stepper_out ;64th time through? djnz step_divideh,:stepper_out ;127th time
/datasheets/files/scenix/htdocs/virtual/vp/stepper.src
Scenix 31/03/2000 28.4 Kb SRC stepper.src