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64th

Catalog Datasheet MFG & Type PDF Document Tags

4031B

Abstract: 40318 4031B 64-STAGE STATIC SHIFT REGISTER DESCRIPTION â'" The 4031B is an edge-triggered 64-Stage Static Shift Register with two Serial Data Inputs (Do, a Data Select Input (S), a Clock Input (CP), a buffered Clock Output (CO) and buffered Outputs from the 64th bit position (Q63, Q63>- Data from the , '¢ TRUE AND COMPLEMENTARY BUFFERED OUTPUTS AVAILABLE FROM 64TH STAGE PIN NAMES DO. S CP CO °63 063 , Output from the 64th Stage Complementary Buffered Output from the 64th Stage TRUTH TABLE s DO D1 Data
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4000B 40318 di 765 h

74ACT2708

Abstract: 74ACT2708PC causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW. When the FIFO is full, HF , process is repeated through the 64th data word. On the rising edge of the 33rd SI, FULL flag goes HIGH , rising edge of the 64th pulse indicating that the FIFO is full. Any further shift-ins are disabled. 33rd PULSE 64th PULSE _ DATA VALID DC 1st DATA WORD Note: SO and OE are LOW; MR is HIGH. FIGURE 1 , , tpj, after SO falls. Repeat process through the 64th SO pulse. FULL flag goes LOW one propagation
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74ACT2708 74ACT2708PC N28B trw1030 64x9 RAM ACT2708 MS-010

d31s

Abstract: the 64th bit position (0 $ 3 , 063)« Data from the selected Data Inputs (D q or D j), as determined b , 64TH S T A G E L O G IC S Y M B O L is 1 1 1 Do 01 10- 2- S 40318 CP CO 0 63 Qß3 0 , Buffered Output from the 64th Stage Complementary Buffered Output from the 64th Stage TRUTH TABLE S L L H H
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d31s 40EA7S7 GD4031B

N28B

Abstract: 74ACT2708 edge of the 33rd SI causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW , falls, indicating the FIFO is no longer empty. The process is repeated through the 64th data word , a half-full FIFO. HF goes LOW propagation delay tIF after the rising edge of the 64th pulse , propagation delay, tOR, after SO falls and HF rises one propa- Repeat process through the 64th SO pulse , FIFO is less than half full. On the falling edge of the 64th SO, HF goes LOW one propagation delay, t
Fairchild Semiconductor
Original

DIODE HF 20

Abstract: 74ACT2708 SI causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW. Data Inputs , . The process is repeated through the 64th data word. On the rising edge of the 33rd SI, FULL flag goes , after the rising edge of the 64th pulse indicating that the FIFO is full. Any further shift-ins are , . IR is LOW. 4. Repeat process through the 64th SO pulse. FULL flag goes LOW one propagation delay , falling edge of the 64th SO, HF goes LOW one propagation delay, tOE, after SO, indicating the FIFO is
Fairchild Semiconductor
Original
DIODE HF 20

TRW1030

Abstract: ac723 is repeated through the 64th data word. IR goes LOW on the falling edge of the 64th SI and remains , . Repeat process through the 64th SO pulse. OR stays LOW after 64th SO indicating an empty FIFO. The SO , data on the outputs as the 64th word stays latched. 3. SO goes LOW, new data reaches output , 1st WORD tSOL tSOH 33rd PULSE 64th PULSE tOR / tD -ih X2nd WORD>
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ac723 74AC723 Trw 1030 74AC DO-8 SO-64 AC723 ACT723 54AC/74AC723 54ACT/74ACT723 54/74AC/ACT

AC723

Abstract: TRW10 outputs. 5. The process is repeated through the 64th data word. IR goes LOW on the falling edge of the 64th SI and remains LOW indicating a full FIFO. Any further shift-ins are disabled. Figure 1: Modes of Operation Mode 1 1st PULSE 33rd PULSE 64th PULSE tSIL tSIH SI IR D O · D8 OR O O - , process through the 64th SO pulse. OR stays LOW after 64th SO indicating an empty FIFO. The SO pulse may , the outputs as the 64th word stays latched. Figure 4: Modes of Operation Mode 4 Note: SI and 5 E
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TRW10 NE 5322 74ACT 54ACT

74AC708

Abstract: 74ACT708 causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW. When the FIFO is full , . The process is repeated through the 64th data word. On the rising edge of the 33rd SI, FULL flag goes , after the rising edge of the 64th pulse indicating that the FIFO is full. Any further shift-ins are disabled. Figure 1: Modes of Operation Mode 1 1st PULSE ts,L 1 tSIH 33rd PULSE 64th PULSE DO - D8 , . 4. Repeat process through the 64th SO pulse. FULL flag goes LOW propagation delay tOHF after the
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ACT708 74AC708 74ACT708 ac708 t3f 185 TLR 308 AC708 54AC/74AC708 54ACT/74ACT708 54/74AC

Zilker Labs

Abstract: A-100 expressed as 1/64th fractions of the total switching period (1/fSW). The high side and low side correction times can be set from 1 to 7 of these 1/64th switching period fractions independently. Blanking , 1/64th fractions of the total switching period (1/fSW). A minimum blanking time is set by the
Intersil
Original
AN2017 Zilker Labs A-100 ZL2005 Intersil - Medical Application
Abstract: 4031B 64-STAGE STATIC SHIFT REGISTER D E S C R IP TIO N - The 4 0 3 1 B is an edge-triggered 64-Stage Static S h ift Register w ith tw o Serial Data Inputs (Dq, D } ) , a Data Select Input (S), a Clock Input (CP), a buffered Clock Output (CO) and buf fered Outputs from the 64th bit position (Q , Edge-Triggered) Buffered Clock Output Buffered Output from the 64th Stage Complementary Buffered O utput from the 64th Stage T R U T H T A B LE S L L H H D0 L H X X L H X D1 X X L H = Low Level = High Levef = Don't -
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0631D

RP5H01

Abstract: RF5H01 . The first bit can be read out by adding reset pulse after CE/VP1. = V,. The 2nd bit â'"the 64th bit , pulse. The data are verified by making CE?VPP = V,L. The 2nd bit~the 64th bit are programmed by , . The dummy bit is located after the practical use 64th bit. The address is 8 bits of 1000000-1000111
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RF5H01 RP5H01 2003 8 PIN RF5H01/RP5H01

100MS

Abstract: DS1869 will cause the wiper position to move 1/64th of the total resistance. A transition from a high to low , CONTACT CLOSURE (D OR UC) INCREMENT/DECREMENT 1/64TH NO CONTACT CLOSED CONTINUOUSLY > 1 SEC ? , AT UPPER LIMIT? YES BOTH CONTACTS OPEN? YES NO NO INCREMENT 1/64TH CONTACT CLOSED CONTINUOUSLY >1 SEC? DECREMENT 1/64TH NO NO DECREMENT ON 100MS INTERVALS
Dallas Semiconductor
Original
DS1869

3 volt dimmer circuit

Abstract: DS1869-100 will cause the wiper position to move 1/64th of the total resistance. A transition from a high to low , CONTACT CLOSURE (D OR UC) INCREMENT/DECREMENT 1/64TH NO CONTACT CLOSED CONTINUOUSLY > 1 SEC ? , AT UPPER LIMIT? YES BOTH CONTACTS OPEN? YES NO NO INCREMENT 1/64TH CONTACT CLOSED CONTINUOUSLY >1 SEC? DECREMENT 1/64TH NO NO DECREMENT ON 100MS INTERVALS
Dallas Semiconductor
Original
3 volt dimmer circuit DS1869-100 4 pin push on button push button datasheet ac dimmer Control Digital Potentiometer

DS1869

Abstract: 100MS , or D input terminals will cause the wiper position to move 1/64th of the total resistance. A , ELECTRICAL CONTROL Figure 3 CONTACT CLOSURE (D OR UC) INCREMENT/DECREMENT 1/64TH NO CONTACT , NO INCREMENT 1/64TH CONTACT CLOSED CONTINUOUSLY >1 SEC? DECREMENT 1/64TH NO NO
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The IC04 LOCMOS HE4000B Logic

Abstract: HEF40 ), a buffered clock output (CO), and buffered outputs from the 64th bit position (O63, O63). The , output O63 buffered output from the 64th stage O63 Fig.2 Pinning diagram. data select input CP complementary buffered output from the 64th stage FAMILY DATA, IDD LIMITS category
Philips Semiconductors
Original
HE4000B HEF4031B The IC04 LOCMOS HE4000B Logic HEF40 HEF4031BP HE4000B package hef package outlines information IC04 LOCMOS HE4000B Logic

32-bit shift register

Abstract: Jrc 5668 /output terminals for 33rd to 64th bits shift register. Display data is input (output) synchroni?ed with , ). H or Open : Shift direction is from 33rd bit to 64th bit. "L" : Shift direction is from 64th bit
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NJU6417C NJU6417CF 100PF NJU6408B 32-bit shift register Jrc 5668 LF 1/16A iobi 64-OUT NJU6408B- NJU641

32-bit shift register

Abstract: m 5672 selected by SHLi terminal. 32 74 I OB 1 lOBz |hta input/output terminals for 33rd to 64th bits shift , 64th bit. "L" : Shift direction is from 64th bit to 33rd bit. 54 HC Non connection. NewdapanRadio
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NJU6407C m 5672 LM 4088 32 bit shift register LM 733 CN L-5-673 5-674-N MJU6417C
Abstract: d ata c lo c k pulse. 2nd b it~ th e 64th bit can be seq uencially read out T h e output d a ta , r after the p ractical use 64th bit. bits of 1000000 - 1000111. operates as a 7-bit counter when , 0000000 to 1111111, and then returns to 0000000. 64th b it a re p ro g ra m m e d by p r o g r e s s in -
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RF/RP5H01 01/RP5H

40NS120

Abstract: HEF4031B MSI 64-STAGE STATIC SHIFT REGISTER The HEF4031B is an edge-triggered 64-stage static shift register with two serial data inputs (Da, Dg!, a data select input S/B, a clock input (CP), a buffered clock output (CO), and buffered outputs from the 64th bit position (0 @ 3 , 0 6 3 ). The output O53 is capable of driving one TTL load. Data from or Dg, as determined by the state of S/B, is , ) buffered clock output buffered output from the 64th stage complementary buffered output from the 64th stage
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40NS120 7Z69834 7Z7459S

JRC 8 pin

Abstract: NJU6417B Data input/output terminals for 33rd tp 64th bits shift register. Display data is input (output , ). H* or Open : Shift direction is from 33rd bit to 64th bit. "L" : Shift direction is from 64th bit
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NJU6417B NJU6417BF JRC 8 pin NJU6417 IOA2 7 segment display 542 application note NJU64 QQS33 UH-10-271 QQS337

mr 044

Abstract: HF to go HIGH, the rising edge of the 33rd SI causes FULL to go HIGH, and the rising edge of the 64th , through the 64th data word. On the rising edge of the 33rd SI, FULL flag goes HIGH prop agation delay tiHF , 64th pulse indicating that the FIFO is full. Any further shift-ins are disabled. 33rd PULSE 64th PULSE , 4-353 2708 Functional Description (Continued) 4. Repeat process through the 64th SO pulse. FU , FIFO is less than half full. On the falling edge of the 64th SO, HF goes LOW one propagation delay, toE
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mr 044 74AC2708
Abstract: , and the ris­ ing edge of th e 64th SI causes HF to go LOW. Data Inputs (D q D 8) Data inputs for , the falling edge of SI The process is repeated through the 64th data word. On th e rising edge of , propagation delay t|p after the ris­ SI goes HIGH: input stage is busy. ing edge of th e 64th pulse , e output. IR is LOW. Repeat process through the 64th S O pulse. FU LL flag goes LOW one , less than half full. On th e falling edge of th e 64th SO, HF goes LOW one propagation delay, toE- a -
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T2708
Abstract: edge of the 33rd SI causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW , of Operation 5. The process is repeated through the 64th data word. On the rising edge of the , LOW propagation delay Hf after the rising edge of the 64th pulse indicating that the FIFO is full , through the 64th SO pulse. FULL flag goes LOW propagation delay tOHF after the rising edge of 33rd SO, indicating that the FIFO is less than half full. On the falling edge of the 64th SO, HF goes LOW -
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T3F 07

Abstract: go HIGH, the rising edge o f the 33rd SI causes FULL to go HIGH, and the rising edge o f the 64th SI , ng er em pty. 5. The process is repeated through the 64th data word. On the rising edge o f the 33rd , goes LOW propagation delay tiF a fte r the rising edge o f the 64th pulse in d ica tin g that the FIFO , tsm tslH -hh 33rd PULSE 64th PULSE th DO - Da DATA VALID / "Y W H > tIHF >! - O C D , through the 64th SO pulse. FULL flag goes LOW propagation delay tOHF after the rising edge o f 33rd SO, in
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T3F 07 54T74AC
Abstract: , the rising edge of the 33rd SI causes FULL to go HIGH, and the rising edge of the 64th SI causes HF , PULSE The process is repeated through the 64th data word. On the rising edge of the 33rd SI, FULL , delay t|F after the ris­ ing edge of the 64th pulse indicating that the FIFO is full. Any further , Operation Mode 1 www.fairchildsemi.com 4 64th PULSE Functional Description 3. 4. Mode 2 , Repeat process through the 64th SO pulse. FULL flag goes LOW one propagation delay, t O H F. after the -
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KSC-1000

Abstract: KSC-1000TG Register Variable width adjustment from 1/4th duty cycle to 47/64th duty cycle Variable offset in steps of 1/64th pixel clock period 12 or 24mA output drive current capability Selectable polarity Used , drive current capability. Variable width adjustment from 1/64th duty cycle to 31/64th duty cycle Variable offset in steps of 1/64th pixel clock period Enabled in General Setup Register Selectable , /64th duty cycle to 31/64th duty cycle Variable offset in steps of 1/64th pixel clock period 12 or
Kodak
Original
KSC-1000 KSC-1000TG KSC capacitors cmos SENSOR "global shutter" HD P46AB kodak kai MTD/PS-0612 4H0686 4H0687
Abstract: causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW. W hen the FIFO is full , lon g e r empty. The process is repeated through the 64th data w ord. On the rising edge of the , propagation d elay t IF after the ris ing edge of the 64th pulse indicating that the FIFO is full. Any further shift-ins are disabled. 3 3 r d PU LS E 64th PU LS E N o lo : SO and O E ar e L O W , through the 64th SO pulse. FULL tlag goes LOW one propagation delay, t OHF, a lte r the rising edge ot -
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ac723

Abstract: through the 64th data word. IR goes LOW on the falling edge of the 64th SI and remains LOW indicating a , . 4. Repeat process through the 64th SO pulse. OR stays LOW after 64th SO indicating an empty FIFO , change in the data on the outputs as the 64th word stays latched. 2. SO goes HIGH, resulting in OR
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Design of 4-digit numeric display circuit

Abstract: BAW56 INTENSITY SETTINGS DIGIT 2 DIGIT 3 DIGIT 0 DIGIT 0's 320µs MULTIPLEX TIMESLOT LOW 1/64th (MIN ON) 2/64th DIGIT 1 HIGH-Z HIGH-Z LOW HIGH-Z 3/64th LOW 61/64th LOW 62/16th LOW 63/64th LOW 63/64th (MAX ON) LOW HIGH-Z HIGH-Z HIGH-Z HIGH-Z , modulation from 1/64th to 63/64th for intensity control. The timing diagram (Figure 14) shows the typical
Maxim Integrated Products
Original
MAX6959 MAX6958AAEE MAX6958AAPE Design of 4-digit numeric display circuit BAW56 MAX695 MAX6958 MAX6958/ MAX6958/MAX6959
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