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Part : 54LS74LMQB Supplier : National Semiconductor Manufacturer : Rochester Electronics Stock : 1,775 Best Price : $6.03 Price Each : $6.03
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54LS/74LS175

Catalog Datasheet MFG & Type PDF Document Tags

ci 74174

Abstract: D flip-flop 74175 pin 9 11 13 17 19 21 23 I I I I D150 54/74175, 54S/74S175, 54LS/74LS175 4 5 12 13 14 13 9 8 Vcc = , 11 300 D150 4L,7B,9B 12 Parallel-in/Parallel-out 54LS/74LS175 4 â'" 4S 40 21 45 D150 4L,6B,9B 13 , /74175 4xD L KJ-) 20 20 â'" 150 D150 4L,6B,9B 3 4-Bit D Flip-Flop 54LS/74LS175 4xD L K-T) 20 21 â'" 55 , /74279, 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 , /7475, 54LS/74LS75 Di O2 D3 DA 13 â'"O E0-1 4 â'"0 E2-3 Qi 02 03 04 VI Â¥ IVIY 16 1 15 14
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OCR Scan
93L38 ci 74174 D flip-flop 74175 pin 7475 D flip-flop 74ls175 pin diagram 9374 74175 ttl pin diagram 93L14 54LS/74LS279 54LS/74LS75 93L08 54LS/74LS77 54LS/74LS175

7475 d-flip flop

Abstract: 7475 D flip-flop 9 11 13 17 19 21 23 I I I I D150 54/74175, 54S/74S175, 54LS/74LS175 4 5 12 13 14 13 9 8 Vcc = , Flip-Flop 54/74175 4xD L KJ-) 20 20 â'" 150 D150 4L,6B,9B 3 4-Bit D Flip-Flop 54LS/74LS175 4xD L K-T) 20 21 , /74279, 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 , /7475, 54LS/74LS75 Di O2 D3 DA 13 â'"O E0-1 4 â'"0 E2-3 Qi 02 03 04 VI Â¥ IVIY 16 1 15 14 , /7477, 54LS/74LS77 12 5 6 12 â'"O 3 2 3 4 6 8 10 Eoi IE, BINI "tí 14 15 16 18 20 22 Eoi I El I
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OCR Scan
7475 d-flip flop ci 7475 D134 74LS573 D145 D147 54S/74S174 54LS/74LS174 54LS/74LS298 54LS/74LS256

7475 D flip-flop

Abstract: quad D flip-flop 74175 pin 9 11 13 17 19 21 23 I I I I D150 54/74175, 54S/74S175, 54LS/74LS175 4 5 12 13 14 13 9 8 Vcc = , Flip-Flop 54LS/74LS175 4xD L K-T) 20 21 â'" 55 D150 4L,6B,9B 4 4-Bit D Flip-Flop 54S/74S175 4xD L 1U~) 7.0 , /74279, 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 , /7475, 54LS/74LS75 Di O2 D3 DA 13 â'"O E0-1 4 â'"0 E2-3 Qi 02 03 04 VI Â¥ IVIY 16 1 15 14 , /7477, 54LS/74LS77 12 5 6 12 â'"O 3 2 3 4 6 8 10 Eoi IE, BINI "tí 14 15 16 18 20 22 Eoi I El I
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OCR Scan
quad D flip-flop 74175 pin 4 bit shift register 7494 pin diagram latch 74ls574 7477 D latch 74174 shift register 74LS173 4 bit 3 state quad register 93L34 54LS/74LS259 54LS/74LS170

74ls373 parallel port

Abstract: d92 02 â'" 4S _r 110 11 300 D150 4L,7B,9B 12 Parallel-in/Parallel-out 54LS/74LS175 4 â'" 4S 40 21 45 D150 , Flip-Flop 54/74175 4xD L KJ-) 20 20 â'" 150 D150 4L,6B,9B 3 4-Bit D Flip-Flop 54LS/74LS175 4xD L K-T) 20 21 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi
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OCR Scan
74ls373 parallel port d92 02 74198 74198 ttl 74LS194 74LS3-73 54LS/74LS541 54LS/74LS78 54LS/74LS168 54LS/74LS169 54LS/74LS490 54LS/74LS373

MUX 74157

Abstract: 74157 mux /Parallel-out 54S/74S175 4 â'" 4S _r 110 11 300 D150 4L,7B,9B 12 Parallel-in/Parallel-out 54LS/74LS175 4 â'" 4S , Flip-Flop 54/74175 4xD L KJ-) 20 20 â'" 150 D150 4L,6B,9B 3 4-Bit D Flip-Flop 54LS/74LS175 4xD L K-T) 20 21 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS D154 54/74170, 54LS/74LS170, 54LS/74LS670 12 15 1 2 3 , 54/74298, 54LS/74LS298 3 2 4 1 9 5 7 6 ioli - loa Ila lob lib s toc 11 c lOd lld CP Oa Ob Oc Od 15 14 13 12 Vcc = Pin 16 GND = Pin 8 D157 9322, 93L22, 54/74157, 54S/74S157, 54LS/74LS157, 54S
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OCR Scan
93L09 MUX 74157 74157 mux 74153 mux mux 74153 74298 quad 2 in mux TTL 74153 54LS/74LS670 54LS/74LS157 54S/74S158 54LS/74LS158 54S/74S257

ci 7475

Abstract: 74175 pin 9 11 13 17 19 21 23 I I I I D150 54/74175, 54S/74S175, 54LS/74LS175 4 5 12 13 14 13 9 8 Vcc = Pin 4 GND = Pin 11 NC = Pins 7, 10 D152 54/74174, 54S/74S174, 54LS/74LS174 3 4 6 11 13 14 Do Di D2 , /74279, 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 , /7475, 54LS/74LS75 Di O2 D3 DA 13 â'"O E0-1 4 â'"0 E2-3 Qi 02 03 04 VI Â¥ IVIY 16 1 15 14 , /7477, 54LS/74LS77 12 5 6 12 â'"O 3 2 3 4 6 8 10 Eoi IE, BINI "tí 14 15 16 18 20 22 Eoi I El I
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OCR Scan
74175 pin 74LS75 74LS77 9370 DA 9370 TTL 7475

d92 02

Abstract: 74LSS02 /Parallel-out 54LS/74LS175 4 â'" 4S 40 21 45 D150 4L,6B,9B 13 Parallel-in/Parallel-out 54/74298 4 2D Mux ~L , FAIRCHILD LOGIC/CONNECTION DIAGRAMS D93 54LS/74LS379 1 A 4 5 12 13 | E D0 Di D2 D3 CP , , 74LS266, 54LS/74LS386 Vcc raianangnnnn 111 III Iii Lil liJ 111 III GND D95 54LS/74LS398 4 5 7 6 , = Pin 20 GND = Pin 10 D96 54LS/74LS399 3 4 6 5 11 12 14 13 Ila lob lib loc lie lod lid S CP Ob Vcc = Pin 16 GND = Pin 8 Od 10 15 D97 54LS/74LS574 2 3 4 5 11 â  1 â  Do CP Di d2 D3 04 ds De
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OCR Scan
74LSS02 D174 74LS164 74LS164 PIN DIAGRAM D172 ttl 74175 54LS/74LS379 54LS/74LS386 54LS/74LS398 54LS/74LS399 54LS/74LS574 54LS/74LSS02

74198

Abstract: 74LS194 â'" 4S _r 110 11 300 D150 4L,7B,9B 12 Parallel-in/Parallel-out 54LS/74LS175 4 â'" 4S 40 21 45 D150 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL 088 54LS/74LS299 1 â  19-12- 50 51 CP , QND = Pin 10 1 â  19- 12-2- D89 54LS/74LS323 1 18 DSo DS7 So Si CP 07 OE I MR Qo , D90 54LS/74LS273 3 4 7 8 13 14 17 18 D0 D, D, D3 D4 D5 06 D7 CP MR Q0 Qì Q; 03 Q4 Q5 06 Q7 t I I I I I I I I 1 2 5 6 9 12 15 16 19 Vcc = Pin 20 GND = Pin 10 D91 54LS/74LS377 1 3 4 7 8 13 14 17
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OCR Scan
74198 pin diagram 74LS273 74LS398 74LS323 54LS D173 54LS/74LS299 54LS/74LS323 54LS/74LS273 54LS/74LS377 54LS/74LS378 54LS/74LS194

d92 02

Abstract: ttl 7497 /Parallel-out 54S/74S175 4 â'" 4S _r 110 11 300 D150 4L,7B,9B 12 Parallel-in/Parallel-out 54LS/74LS175 4 â'" 4S , 6 Vcc = Pin 16 GND = Pin 8 I ? I 13 5 6 Vcc = Pin 16 GND = Pin 8 0189 54LS/74LS173 9 10 14 13 , » . Oz Oy MR Oo 0i 02 03 MR 15 3 4 5 8 Vcc = Pin 16 GND = Pin 8 D190 54LS/74LS375 D194 54LS , Pin 8 D195 54LS/74LS393 (each half) 1, 13- CP MR Oo 0i 02 03 2, 12 4, 10 6, I 3, 11 5, 9 Vcc = Pin 14 GND = Pin 7 2-10- D196 54LS/74LS395 7 3 4 5 6 I I I I I a Po Pi Pi p3 t>s CP OE MR O0 O
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OCR Scan
ttl 7497 D187 D188 D190 D194 D195 54LS/74LS173 54LS/74LS375 54LS/74LS390 54LS/74LS393 54LS/74LS395 2/74LS299

D flip-flop 74175 pin

Abstract: 74175 D flip flop Flip-Flop 54LS/74LS175 4xD L K-T) 20 21 â'" 55 D150 4L,6B,9B 4 4-Bit D Flip-Flop 54S/74S175 4xD L 1U~) 7.0 , 6 Vcc = Pin 16 GND = Pin 8 I ? I 13 5 6 Vcc = Pin 16 GND = Pin 8 0189 54LS/74LS173 9 10 14 13 , » . Oz Oy MR Oo 0i 02 03 MR 15 3 4 5 8 Vcc = Pin 16 GND = Pin 8 D190 54LS/74LS375 D194 54LS , Pin 8 D195 54LS/74LS393 (each half) 1, 13- CP MR Oo 0i 02 03 2, 12 4, 10 6, I 3, 11 5, 9 Vcc = Pin 14 GND = Pin 7 2-10- D196 54LS/74LS395 7 3 4 5 6 I I I I I a Po Pi Pi p3 t>s CP OE MR O0 O
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OCR Scan
74175 D flip flop 8-bit ttl latch latch 74LS374 D196 D154 224X4 54ILS/74LS670

D flip-flop 74175 pin

Abstract: 74LS78 54LS/74LS175 4xD L K-T) 20 21 â'" 55 D150 4L,6B,9B 4 4-Bit D Flip-Flop 54S/74S175 4xD L 1U~) 7.0 10 â , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12
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OCR Scan
74LS78 74LS374 74ls373 D150 D Flip-Flop 74ls373 fairchild 54LS/74LS374

TTL 74ls194

Abstract: 74LS194 â'" 4S _r 110 11 300 D150 4L,7B,9B 12 Parallel-in/Parallel-out 54LS/74LS175 4 â'" 4S 40 21 45 D150 , PE Po Pi J P2 P3 P4 P5 Pe P7 K CP MR Qo Qi Û2 Q3 04 05 06 Û7 n DIGITAL-TTL D171 D172 54LS/74LS295, 54LS/74LS295A 54/74194, 54S/74S194, 54LS/74LS194 6 2 3 4 5 u PE Po Pi P2 P3 Ds CP OE , = Pin 16 GND = Pin 8 D173 54/74198 D174 54/74164, 54LS/74LS164 15 17 19 21 .M ï I II I I , Vcc = Pin 24 GND = Pin 12 Vcc = Pin 14 GND = Pin 7 D175 54/74165, 54LS/74LS165 D176 54/74166 125
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OCR Scan
TTL 74ls194 74LS165 74ls273 fairchild TTL 74194 74194 pin diagram ttl 74198 54LS/74LS295 54LS/74LS295A 54LS/74LS164 54LS/74LS165

ci 7475

Abstract: D147 9 11 13 17 19 21 23 I I I I D150 54/74175, 54S/74S175, 54LS/74LS175 4 5 12 13 14 13 9 8 Vcc = Pin 4 GND = Pin 11 NC = Pins 7, 10 D152 54/74174, 54S/74S174, 54LS/74LS174 3 4 6 11 13 14 Do Di D2 , /74279, 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 , /7475, 54LS/74LS75 Di O2 D3 DA 13 â'"O E0-1 4 â'"0 E2-3 Qi 02 03 04 VI Â¥ IVIY 16 1 15 14 , /7477, 54LS/74LS77 12 5 6 12 â'"O 3 2 3 4 6 8 10 Eoi IE, BINI "tí 14 15 16 18 20 22 Eoi I El I
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OCR Scan
74LS109 74L576 fairchild 9314 rs latch pin diagram 7475 74279 54S/74S109 54LS/74LS109 54LS/74LS76 54LS/74LS107 54LS/74LS196 54LS/74LS197

74LS573

Abstract: 74LS573 "LATCH" 54LS/74LS175 4xD L K-T) 20 21 â'" 55 D150 4L,6B,9B 4 4-Bit D Flip-Flop 54S/74S175 4xD L 1U~) 7.0 10 â , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D177 9328, 93L28 D178 54/7491 D179 54LS , ~ GND Pin 5 = Pin 10 Vcc = Pin 20 GND = Pin 10 0180 54LS/74LS352 D181 54LS/74LS353 1 6 5 4 3 10 11 , (Typ) Logic/Connection Diagram Package(s) 1 4-Bit D Latch 54LS/74LS375 4xD â'" 2(H) 20 10 10 32 D190 , Flip-Flop 54LS/74LS298 4x2 â'" 1 ("L) 20 20 â'" 65 D156 4L,6B,9B 7 Dual 4-Bit D Latch 9308 8xD 2xL 2x2 AND
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OCR Scan
74LS573 "LATCH" 74LS573 latch 7491 8-bit 7491 fairchild D177 D178 54LS/74LS573 54LS/74LS352 54LS/74LS353

decoder 7448

Abstract: BCD D147 16 GND = Pm 8 D149 54/7477, 54LS/74LS77 1 2 5 6 D150 54/74175, 54S/74S175, 54LS/74LS175 4 5 12 , Blanking o Item I > U J Q 54LS/ 74LS48 5449 54LS/ 74LS49 9302 9307 9315 9317B 9317C 9368 9370 , 9302 54/7445 54/74145 9307 54/7448 5449 9315 9317B 9317C 54/7446 54/7447 54LS/74LS47 54LS/74LS48 54LS/74LS49 54LS/74LS247 54LS/74LS248 54LS/74LS249 9368 9370 9374 70 70 16 80 80 11 80 96 70 40 20 40 40 12 , 14 D147 54/74279, 54LS/74LS279 7 11 Vcc 2 6 6 5 Ao I I I I ¿ A Ai Ä2 A3 El RBI
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OCR Scan
decoder 7448 BCD D147 7448 decoder D142 decoder 74LS47 7-seg 54LS/

74191 8 bit

Abstract: 7443 Flip-Flop 54LS/74LS175 4xD L K-T) 20 21 â'" 55 D150 4L,6B,9B 4 4-Bit D Flip-Flop 54S/74S175 4xD L 1U~) 7.0 10 â , 9321, 93L21, 54/74S139, 54LS/74LS139 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 11 15 1 10 9 , 12 Vcc = Pin 16 GND = Pin 8 D133 9301, 93L01, 9302 D134 9334, 93L34, 54LS/74LS259 TTTTTTTTTT 13 , D135 54/7442, 54LS/74LS42, 54/7443, 54/7444, 54/7445 54/74145, 54LS/74LS145 15 14 13 12 TTTTTTTTTT 1 23456 79 10 11 Vcc = Pin 16 GND = Pin 8 D136 54S/74S138, 54LS/74LS138 1 2 3 4 5C â Iii- e
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OCR Scan
74LS190 74LS191 74191 8 bit 7443 Flip-Flop 7443 d Flip-Flop 74LS42 D135 93L11 54LS/74LS139 54LS/74LS155 54LS/74LS156 54LS/74LS42

74198

Abstract: 74LS194 O -P ^ P a ra lle l-in /P a ra lle l-o u t f t C O 54LS/74LS174 h cn cn cn O 54/74175 54S/74S175 54LS/74LS175 | c 1 x 3 x a jk. 1 h o I O C O cn 03 00 00 , 54LS/74LS194 54/74198 i f U r~ (0 ro , lle l-o u t 2D C O cn cn to -1 I P a ra lle l-in /P a ra lle l-o u t C D to o> 54LS/74LS164 54 , > C O 03 54LS/74LS378 54LS/74LS379 ^1 A I(/) u
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OCR Scan
20GND S4LS/74LS299

74153 mux

Abstract: MUX 74157 â'" 150 D150 4L,6B,9B 3 4-Bit D Flip-Flop 54LS/74LS175 4xD L K-T) 20 21 â'" 55 D150 4L,6B,9B 4 4 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS D154 54/74170, 54LS/74LS170, 54LS/74LS670 12 15 1 2 3 , 54/74298, 54LS/74LS298 3 2 4 1 9 5 7 6 ioli - loa Ila lob lib s toc 11 c lOd lld CP Oa Ob Oc Od 15 14 13 12 Vcc = Pin 16 GND = Pin 8 D157 9322, 93L22, 54/74157, 54S/74S157, 54LS/74LS157, 54S/74S158, 54LS/74LS158, 54S/74S257,54LS/74LS257, 54S/74S258, 54LS/74LS258 15 2 3 5 6 14 13 11 10 E loa
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OCR Scan
CI 74151 74LS152 MUX 74151 74152 mux 74157 74LS502 54LS/74LS257 54LS/74LS258 54S/74S153 54LS/74LS153 54S/74S253 54LS/74L8253

74191 8 bit

Abstract: 74155 PIN DIAGRAM /74175 4xD L KJ-) 20 20 â'" 150 D150 4L,6B,9B 3 4-Bit D Flip-Flop 54LS/74LS175 4xD L K-T) 20 21 â'" 55 , 9321, 93L21, 54/74S139, 54LS/74LS139 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 11 15 1 10 9 , 12 Vcc = Pin 16 GND = Pin 8 D133 9301, 93L01, 9302 D134 9334, 93L34, 54LS/74LS259 TTTTTTTTTT 13 , D135 54/7442, 54LS/74LS42, 54/7443, 54/7444, 54/7445 54/74145, 54LS/74LS145 15 14 13 12 TTTTTTTTTT 1 23456 79 10 11 Vcc = Pin 16 GND = Pin 8 D136 54S/74S138, 54LS/74LS138 1 2 3 4 5C â Iii- e
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OCR Scan
74155 PIN DIAGRAM D133 7442 logic diagram 74155 D132 pin diagram of 74LS191 54LS/74LS145 54LS/74LS138 93S138 93S137 54/74151A

CI 7446

Abstract: CI 74141 9 11 13 17 19 21 23 I I I I D150 54/74175, 54S/74S175, 54LS/74LS175 4 5 12 13 14 13 9 8 Vcc = Pin 4 GND = Pin 11 NC = Pins 7, 10 D152 54/74174, 54S/74S174, 54LS/74LS174 3 4 6 11 13 14 Do Di D2 , /74279, 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 , /7475, 54LS/74LS75 Di O2 D3 DA 13 â'"O E0-1 4 â'"0 E2-3 Qi 02 03 04 VI Â¥ IVIY 16 1 15 14 , /7477, 54LS/74LS77 12 5 6 12 â'"O 3 2 3 4 6 8 10 Eoi IE, BINI "tí 14 15 16 18 20 22 Eoi I El I
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OCR Scan
CI 7446 CI 74141 cI 74ls47 CI 7447 CI 7448 ci 7445 54LS/74LS47 54LS/74LS48 54LS/74LS49 54LS/74LS247 54LS/74LS248

74175PC

Abstract: IC 74175 NATIONAL SEtlICOND {LOGIC} 02E D I bSDllSE Dat3öfi7 T I - ^46-07-09 175 C O N N E C T IO N D IA G R A M P IN O U T A 54/74175 54S/74S175 54LS/74LS175 QUAD D FLIP-FLOP M f l[ 7 O o [T Q oU Do [4 D i[ ? öl [7 Qi [ T 16] Vcc H ]Q 3 14103 T |]d3 12] d 2 ÏT ] 02 Tol Os T ] cp D E S C R IP T IO N - T h e '175 is a high speed quad D flip-flop. T h e device is use ful for general flip-flop requirements where clock and clear inputs are com m on. T h e inform ation on the D inputs is
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OCR Scan
74175PC 74LS175PC 74175D IC 74175 ic 175d 74S175PC 74S175DC 74175FC
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