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Part : 54LS74LMQB Supplier : National Semiconductor Manufacturer : Rochester Electronics Stock : 1,775 Best Price : $6.03 Price Each : $6.03
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54LS/74LS162

Catalog Datasheet MFG & Type PDF Document Tags

74LS160

Abstract: Synchronous 74163 Up/Down U p/D own 93L16 93S16 54/74160 54LS/74LS160 54/74161 54LS/74LS161 54/74162 54LS/74LS162 54/74163 54LS/74LS163 54LS/74LS168 54LS/74LS169 54/74192 54LS/74LS192 54/74193 54LS/74LS193 54/74190 , , 54LS/74LS162, 54/74163, 54LS/74LS163 D129 54/74192, 54LS/74LS192, 54/74193, 54LS/74LS193 i 7 , /7490A, 54LS/74LS90 6 7 D122 54/7492, 74LS92 D123 54/74293, 54LS/74LS293 CPo CP, MR Qo Qi 0 2 0 , Pin 10 NC = 2, 3, 4, 13 Vcc = Pin 14 GND = Pin 7 NC = Pins 1, 2, 3, 6 D124 54/7493A, 54LS/74LS93
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OCR Scan
93S05 74LS160 Synchronous 74163 74192 74LS190 pins 74LS193 74LS191 pins 54LS/74LS160 54LS/74LS161 54LS/74LS162 54LS/74LS163 54LS/74LS168 54LS/74LS169

74LS190 pins

Abstract: 74LS192 PIN diagram /74LS162, 54/74163, 54LS/74LS163 9 3 4 5 6 Alili 7-10-2- PE Po Pi P2 P3 CEP CET TC CP sn Oo Qi 02 , 7 Synchronous 54/74162 10 Presettable s _r 32 17 315 D128 4L,7B,9B 8 Synchronous 54LS/74LS162 10 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D121 54/7490A, 54LS/74LS90 14-1- 6 7 ü MS , , 74LS92 14- 1 - Vcc = Pin 5 GND = Pin 10 NC = 2, 3, 4, 13 D123 S4/74293, 54LS/74LS293 ioli» CPo , , 54LS/74LS93 IT 2 3 12 9 8 11 Vcc Pin 5 GND = Pin 10 NC = Pins 4, 6, 7, 13 D127 9310, 93L10, 93S10
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OCR Scan
74LS192 PIN diagram 74LS183 TTL 74ls163 74LS192 pins 74LS161 74160 54LS/74LS90 54LS/74LS293 S4/7493A 54LS/74LS93 54LS/74LS196 54LS/74LS197

74LS183

Abstract: 74LS193 /74LS162, 54/74163, 54LS/74LS163 9 3 4 5 6 Alili 7-10-2- PE Po Pi P2 P3 CEP CET TC CP sn Oo Qi 02 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D121 54/7490A, 54LS/74LS90 14-1- 6 7 ü MS , , 74LS92 14- 1 - Vcc = Pin 5 GND = Pin 10 NC = 2, 3, 4, 13 D123 S4/74293, 54LS/74LS293 ioli» CPo , , 54LS/74LS93 IT 2 3 12 9 8 11 Vcc Pin 5 GND = Pin 10 NC = Pins 4, 6, 7, 13 D127 9310, 93L10, 93S10, 9316, 93L16, 93S16 54/74160, 54LS/74LS160, 54/74161, 54LS/74LS161 9 3 4 5 6 PE Po Pi P2 P3 7- CEP
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OCR Scan
sn 7492 ttl TTL 74293 TTL 7490 54LS TTL 74LS93 74ls90 54L8/74LS192 54LS/74LS193

74LS191

Abstract: D129 _r 32 17 315 D128 4L,7B,9B 8 Synchronous 54LS/74LS162 10 Presettable s s 45 15 95 D128 4L,7B,9B 9 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12
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OCR Scan
74LS191 D129 74162 pin diagram of 74163 74160 pin TTL 93S16 54LS/74LS541 54LS/74LS78 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256

74LS190 PIN diagram

Abstract: presettable digital clock /74162 10 Presettable s _r 32 17 315 D128 4L,7B,9B 8 Synchronous 54LS/74LS162 10 Presettable s s 45 15 , 9321, 93L21, 54/74S139, 54LS/74LS139 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 11 15 1 10 9 , 12 Vcc = Pin 16 GND = Pin 8 D133 9301, 93L01, 9302 D134 9334, 93L34, 54LS/74LS259 TTTTTTTTTT 13 , D135 54/7442, 54LS/74LS42, 54/7443, 54/7444, 54/7445 54/74145, 54LS/74LS145 15 14 13 12 TTTTTTTTTT 1 23456 79 10 11 Vcc = Pin 16 GND = Pin 8 D136 54S/74S138, 54LS/74LS138 1 2 3 4 5C â Iii- e
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OCR Scan
74LS190 74LS190 PIN diagram presettable digital clock ttl 74191 Fairchild 74190 74155 74191 54LS/74LS139 54LS/74LS155 54LS/74LS156 54LS/74LS259 54LS/74LS42

sn 7492 ttl

Abstract: 74293 pin diagram /74LS162, 54/74163, 54LS/74LS163 9 3 4 5 6 Alili 7-10-2- PE Po Pi P2 P3 CEP CET TC CP sn Oo Qi 02 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D121 54/7490A, 54LS/74LS90 14-1- 6 7 ü MS , , 74LS92 14- 1 - Vcc = Pin 5 GND = Pin 10 NC = 2, 3, 4, 13 D123 S4/74293, 54LS/74LS293 ioli» CPo , , 54LS/74LS93 IT 2 3 12 9 8 11 Vcc Pin 5 GND = Pin 10 NC = Pins 4, 6, 7, 13 D127 9310, 93L10, 93S10, 9316, 93L16, 93S16 54/74160, 54LS/74LS160, 54/74161, 54LS/74LS161 9 3 4 5 6 PE Po Pi P2 P3 7- CEP
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OCR Scan
74293 pin diagram TTL 7493A 7493A 74LS93 7490A ttl 7492 54LS/74LS290 54LS/74LS390 54LS/74LS393

CI 74LS90

Abstract: ci 74193 /74LS162, 54/74163, 54LS/74LS163 9 3 4 5 6 Alili 7-10-2- PE Po Pi P2 P3 CEP CET TC CP sn Oo Qi 02 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D121 54/7490A, 54LS/74LS90 14-1- 6 7 ü MS , , 74LS92 14- 1 - Vcc = Pin 5 GND = Pin 10 NC = 2, 3, 4, 13 D123 S4/74293, 54LS/74LS293 ioli» CPo , , 54LS/74LS93 IT 2 3 12 9 8 11 Vcc Pin 5 GND = Pin 10 NC = Pins 4, 6, 7, 13 D127 9310, 93L10, 93S10, 9316, 93L16, 93S16 54/74160, 54LS/74LS160, 54/74161, 54LS/74LS161 9 3 4 5 6 PE Po Pi P2 P3 7- CEP
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OCR Scan
CI 74LS90 ci 74193 ci 74ls193 CI 74196 ci 7492 CI 74176 54S/74S109 54LS/74LS109 54LS/74LS76 54LS/74LS107 93L14 54LS/74LS279

74162

Abstract: counter 74162 Q Q Di (4) E Q E5 PR K X J CP Q O Q 35 LOGIC DIAGRAM 54LS/74LS162 A Vcc = Pin 16 GND = , 54/74162 54LS/74LS162A LOGIC SYMBOL DESCRIPTION The "162" is a high-speed BCD decade counter , INPUT AND OUTPUT LOADING AND FAN-OUT TABLED) PINS DESCRIPTION 54/74 54S/74S 54LS/74LS CP Clock , CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE«®) PARAMETER TEST CONDITIONS 54/74 54S/74S 54LS/74LS UNIT , CHARACTERISTICS: TA=25°C (See Section 4 for Test Circuits and Conditions) 54/74 54S/74S 54LS/74LS
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OCR Scan
N74162N N74LS162AN N74162F N74LS162AF S54162F S54LS162AF counter 74162 pin diagram of 74162 74LS162 parallel counter 74162 LOAD 54LS/74LS162A

74ls161 counter pin configuration

Abstract: 74LS161 SPEED/PACKAGE AVAILABILITY 54 F,W 54LS F,W 74 B,F 74LS B,F PIN CONFIGURATION B,F,W PACKAGE C L , AVAILABILITY 54 F.W 54LS F,W 74 B,F 74LS B,F PIN CONFIGURATION B,F,W PACKAGE DESCRIPTION This , circuit and typical waveforms shown at the front of section. SPEED/PACKAGE AVAILABILITY 54 F.W 54LS F , enable inputs. The clear function for the 54/74LS162 is synchronous and a low level at the clear Input , level of the clock input. The 54/74LS162 features a fully independent clock circuit. Changes made to
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OCR Scan
74ls161 counter pin configuration 54/74LS160 54/74LS162

74LS115

Abstract: 74LS273 reference to 54LS/74LS75. Refer to Page 5-48 for DC footnotes. Iih at Max Input Voltage, Vcc=Max _ _ =0.1 , Power TTL, 93L00 (MSI) Schottky T TL 54S/74S, 93S00 Low Power Schottky T TL 54LS/74LS V|L 0.8 0.8 , CATIONS B Device 5 4LS /74LS 00 5 4LS /74LS 02 5 4LS /74LS 03 5 4LS /74LS 04 54LS /74LS 05 54L S /7 4 LS 0 8 5 4 LS /74LS 09 5 4 LS /74LS 10 54LS/74LS 11 5 4 LS /74LS 13 54L S /7 4 LS 1 4 5 4 LS /74LS 15 5 4 LS /74LS 20 54LS/74LS 21 54LS /74LS 22 5 4 LS /74LS 26 5 4 LS /74LS 27 5 4 LS /74LS 28 54L
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OCR Scan
74LS115 74LS273 74LS00 QUAD 2-INPUT NAND GATE 74LS189 equivalent 74LS265 74LS93A

74160PC

Abstract: 74LS160 parallel counter 160 â'¢ 162 /m 0 " 54/74160 ^^4/74162 ^SYNCHRONOUS PRESETTABLE BCD DECADE COUNTERS yÃ"/Ã"Ã"^O 54LS/74LS160 S4LS/74LS162 DESCRIPTIONâ'"The '160 and '162 are high speed synchronous decade counters operating in the BCD (8421) sequence. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The '160 has an asynchronous Master Reset input that overrides
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OCR Scan
74160PC 74LS160PC 74LS162PC 74LS160DC 74162DC 74160FC 74LS160 parallel counter BCD Decade logic diagram 74160 74LS160D logic diagram of 74ls160 S4LS/74LS162 74162PC 74160DC

74LS160D

Abstract: 74LS160PC 160 · 162 CONNECTION DIAGRAM 0 54/74160 · 54LS/74LS160 ¿ ,6 ^ /7 4 1 6 2 · 94LS/74LS162 0/co4^SYNCHRONOUS PRESETTABLE BCD DECADE COUNTERS \ftoic oïb PINOUT A / H E C P |7 Po [ I P l[ 4 îfilv c c î ï I tc 14] Qo T 3 [Q i DESCRIPTION - The '160 and '162 are high speed synchronous decade counters operating in the BCD (8421) sequence. They are synchronously presettable for application in program mable dividers and have tw o types of Count Enable inputs plus a Terminal Count ou tput fo
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OCR Scan
IC 74LS160 Ls 74160 74LS160P 74162FC 74LS162D TC 9310 IC 94LS/74LS162 74LS162DC 54/74LS

74ls373 parallel port

Abstract: d92 02 FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12 , ,10 Vcc = Pin 16 GND = Pin 8 D85 54LS/74LS373 3 4 7 8 13 14 17 18 INN 11- Do LE Di D2 D3 D4 Ds De
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OCR Scan
74ls373 parallel port d92 02 74175 ttl pin diagram 74ls175 pin diagram 74198 74198 ttl 54LS/74LS194 54LS/74LS298 93L08 54S/74S174 54LS/74LS174

MUX 74157

Abstract: 74157 mux FAIRCHILD LOGIC/CONNECTION DIAGRAMS D154 54/74170, 54LS/74LS170, 54LS/74LS670 12 15 1 2 3 , 54/74298, 54LS/74LS298 3 2 4 1 9 5 7 6 ioli - loa Ila lob lib s toc 11 c lOd lld CP Oa Ob Oc Od 15 14 13 12 Vcc = Pin 16 GND = Pin 8 D157 9322, 93L22, 54/74157, 54S/74S157, 54LS/74LS157, 54S/74S158, 54LS/74LS158, 54S/74S257,54LS/74LS257, 54S/74S258, 54LS/74LS258 15 2 3 5 6 14 13 11 10 E loa , /74153, 54S/74S153, 54LS/74LS153, 54S/74S253, 54LS/74L8253 1 6 5 4 3 10 11 12 13 15 JM I I I I I I U
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OCR Scan
MUX 74157 74157 mux 74153 mux mux 74153 74298 quad 2 in mux TTL 74153 54LS/74LS170 54LS/74LS670 93L09 54LS/74LS157 54LS/74LS158 54LS/74LS257

74153 mux

Abstract: MUX 74157 FAIRCHILD LOGIC/CONNECTION DIAGRAMS D154 54/74170, 54LS/74LS170, 54LS/74LS670 12 15 1 2 3 , 54/74298, 54LS/74LS298 3 2 4 1 9 5 7 6 ioli - loa Ila lob lib s toc 11 c lOd lld CP Oa Ob Oc Od 15 14 13 12 Vcc = Pin 16 GND = Pin 8 D157 9322, 93L22, 54/74157, 54S/74S157, 54LS/74LS157, 54S/74S158, 54LS/74LS158, 54S/74S257,54LS/74LS257, 54S/74S258, 54LS/74LS258 15 2 3 5 6 14 13 11 10 E loa , /74153, 54S/74S153, 54LS/74LS153, 54S/74S253, 54LS/74L8253 1 6 5 4 3 10 11 12 13 15 JM I I I I I I U
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OCR Scan
74174 shift register CI 74151 74LS152 MUX 74151 D flip-flop 74175 pin quad D flip-flop 74175 pin 54LS/74LS258 54LS/74LS153 54LS/74L8253 93L12 93S12 54/74151A

ci 74174

Abstract: D flip-flop 74175 pin /74279, 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 , /7475, 54LS/74LS75 Di O2 D3 DA 13 â'"O E0-1 4 â'"0 E2-3 Qi 02 03 04 VI Â¥ IVIY 16 1 15 14 , /7477, 54LS/74LS77 12 5 6 12 â'"O 3 2 3 4 6 8 10 Eoi IE, BINI "tí 14 15 16 18 20 22 Eoi I El I , 9 11 13 17 19 21 23 I I I I D150 54/74175, 54S/74S175, 54LS/74LS175 4 5 12 13 14 13 9 8 Vcc = Pin 4 GND = Pin 11 NC = Pins 7, 10 D152 54/74174, 54S/74S174, 54LS/74LS174 3 4 6 11 13 14 Do Di D2
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OCR Scan
ci 74174 7475 D flip-flop 9374 74116 74174 7477 D latch 54LS/74LS75 54LS/74LS77 54LS/74LS175 93L38

trigger 74114

Abstract: 74114 FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D65 54/7413, 54LS/74LS13 Vcc NC HKiEiraiaram 3 LlI lil Id li] li] LàJ Ui NC QND D66 54/74125, 54LS/74LS125 Vcc E D O E D O ism a ra a in ~?i r?i Lj ui lii y ili iii u E D O E D O QND D67 54/74126, 54LS/74LS126 Vcc E D O E DO ZrhTrh liiiiiiiiiiiiiiiijiij E D O E D O GND D68 54LS/74LS365 Vcc I2 |i«l Fsl [i«l [wl Fai R |io| f»l rih yrrrr lil liJ LiJ U liJ LsJ lil Id Ei GND D69 54LS/74LS366 Vcc E2 EI EI ra ra EI R
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OCR Scan
9S05A trigger 74114 74114 IC 7404 74ls04 hex inverter gates 74LS13 IC 7413 54LS/74LS13 54LS/74LS125 54LS/74LS126 54LS/74LS365 54LS/74LS366 54LS/74LS367

IC TTL 7432

Abstract: 74LS86 gate diagram FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 Vcc ) EI EI na fri EI iyi FI ¿J a lil liJ Li] Iii liJ 111 llJ OND D19 54/7421, 54H/74H21 54LS/74LS21 Vcc NC s J â'" D17 9S41 Vcc RRPIIiRRRR lillkililliJliJlilliJliJ GND D20 54/7432, 54S/74S32 54LS/74LS32 ei ei ei m ei iti fi Elfi LlJ liJ LiJ LiJ Iii Iii Lü D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 Vcc El El El [il El FI
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OCR Scan
74LS266 IC TTL 7432 74LS86 gate diagram 7411 3 INPUT AND gate IC 7432 7411 pin diagram IC 7486 54LS/74LS08 54LS/74LS09 54LS/74LS21 54LS/74LS32 54LS/74LS11 54LS/74LS15

ALU IC 74181

Abstract: 74181 ic pin diagram FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 Vcc ) EI EI na fri EI iyi FI ¿J a lil liJ Li] Iii liJ 111 llJ OND D19 54/7421, 54H/74H21 54LS/74LS21 Vcc NC s J â'" D17 9S41 Vcc RRPIIiRRRR lillkililliJliJlilliJliJ GND D20 54/7432, 54S/74S32 54LS/74LS32 ei ei ei m ei iti fi Elfi LlJ liJ LiJ LiJ Iii Iii Lü D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 Vcc El El El [il El FI
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OCR Scan
ALU IC 74181 74181 ic pin diagram DS 7409 7480 full adder 1 bit 74LS86 full adder IC 74181 54S/74S86 54LS/74LS86 54LS/74LS136 54S/74S135 54LS/74LS379 54LS/74LS386

IC 7404 7406

Abstract: 74LS00 7400 74S00 , 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS/74LS03, 7426, 54LS/74LS26 54/7437, 54LS/74LS37, 54/7438, 74LS38, 54/74132, 54S/74S132, 74LS132 03 54 , /74S10, 54LS/74LS10, 54/7412 Vcc L_l Lil lil LiJ LiJ LiJ Lü QND D5 9004, 54/7420, 54H/74H20, 54S/74S20, 54LS/74LS20, 54/7422, 54H/74H22, 74S22, 54LS/74LS22, 9009, 54/7440, 54H/74H40, 54S/74S40, 54LS
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OCR Scan
IC 7404 7406 74LS00 7400 74S00 IC TTL 74LS00 ic 74132 Fairchild 9002 TTL 74h04 54H/74H04 54S/74S04 54LS/74LS04 54LS/74LS14 54LS/74LS00 54LS/74LS03
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