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Part : 54LS74LMQB Supplier : National Semiconductor Manufacturer : Rochester Electronics Stock : 1,775 Best Price : $6.03 Price Each : $6.03
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54LS/74L Datasheet

Part Manufacturer Description PDF Type
54LS74LMQB National Semiconductor Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Original
54LS74LMQB Fairchild Semiconductor Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Scan
54LS74LMQB N/A Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Scan
54LS74LMQB National Semiconductor Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Scan

54LS/74L

Catalog Datasheet MFG & Type PDF Document Tags

74LS191

Abstract: D129 Synchronous 54/74160 10 Presettable S s 32 17 315 D127 4L,7B,9B 4 Synchronous 54LS/74L.S160 10 Presettable s , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12
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93L16 93S16 74LS191 D129 74162 74192 pin diagram of 74163 74160 pin 54LS/74LS541 54LS/74LS78 54LS/74LS168 54LS/74LS169 54LS/74LS490 54LS/74LS373

74LS190 PIN diagram

Abstract: presettable digital clock 4L,7B,9B 3 Synchronous 54/74160 10 Presettable S s 32 17 315 D127 4L,7B,9B 4 Synchronous 54LS/74L , 9321, 93L21, 54/74S139, 54LS/74LS139 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 11 15 1 10 9 , 12 Vcc = Pin 16 GND = Pin 8 D133 9301, 93L01, 9302 D134 9334, 93L34, 54LS/74LS259 TTTTTTTTTT 13 , D135 54/7442, 54LS/74LS42, 54/7443, 54/7444, 54/7445 54/74145, 54LS/74LS145 15 14 13 12 TTTTTTTTTT 1 23456 79 10 11 Vcc = Pin 16 GND = Pin 8 D136 54S/74S138, 54LS/74LS138 1 2 3 4 5C â Iii- e
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74LS190 74LS190 PIN diagram presettable digital clock ttl 74191 Fairchild 74190 74155 74191 54LS/74LS139 54LS/74LS155 54LS/74LS156 54LS/74LS259 54LS/74LS42

74LS190 pins

Abstract: 74LS192 PIN diagram 4 Synchronous 54LS/74L.S160 10 Presettable s s 45 15 95 D127 4L,7B,9B 5 Synchronous 54/74161 16 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D121 54/7490A, 54LS/74LS90 14-1- 6 7 ü MS , , 74LS92 14- 1 - Vcc = Pin 5 GND = Pin 10 NC = 2, 3, 4, 13 D123 S4/74293, 54LS/74LS293 ioli» CPo , , 54LS/74LS93 IT 2 3 12 9 8 11 Vcc Pin 5 GND = Pin 10 NC = Pins 4, 6, 7, 13 D127 9310, 93L10, 93S10, 9316, 93L16, 93S16 54/74160, 54LS/74LS160, 54/74161, 54LS/74LS161 9 3 4 5 6 PE Po Pi P2 P3 7- CEP
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74LS190 pins 74LS192 PIN diagram 74LS183 TTL 74ls163 74LS192 pins Synchronous 74163 54LS/74LS90 54LS/74LS293 S4/7493A 54LS/74LS93 54LS/74LS160 54LS/74LS161
Abstract: ) 5 4 /7 4 PARAMETER ICC Supply current 5 4 S /7 4 S Min Max 54LS /74L S Min Max 13 UNIT mA , ) 5 4 /7 4 80 -3 .2 160 -6 .4 160 -6 .4 -4 0 0 16 5 4 S /7 4 S 54LS /74LS 20 -0 .4 80 -1 .6 80 , Test Circuits and Conditions) 5 4 /7 4 5 4 S /7 4 S 54LS /74LS Min tPLH *PHL tPLH tPHL Propagation , Circuits and Conditions) 5 4 /7 4 TEST CONDITIONS Min 20 5 4 S /7 4 S Min Max 54LS /74LS Min 20 , back cover fo r 54S / 74S and 54LS / 74LS specifications. signDtics 117 AC WAVEFORMS -
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54LS77 S5477W S54LS77W
Abstract: (Ä) M O T O R O L A D E S C R IP T IO N - The TT L /M S I S N 54LS /74L S 670 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation. The 3-state outputs make it possible to connect up to 128 outputs to increase the word capacity up to 512 words. Any number of these devices can-be operated in parallel to generate an n-bit length. The S N 54 L S /7 4L S 1 7 0 provides a similar -
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SN54LS670 SN74LS670

74ls604

Abstract: 74LS605 (M ) M O T O R O L A D E S C R IP T IO N - The S N 54LS /74L S 604thru S N 54LS /74LS 607 are multiplexed latches designed for storing data from two input buses, A and B, and providing the stored data from either the A or B register to the output bus. Data is loaded by the clock on the positive going transition (low-level to high-level). Control of the active and high impedance states of the outputs is also on the clock pin. The outputs are in the HIGH impedance or OFF state when
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SN54LS/74LS604 74ls604 74LS605 2088I 74LS607 SN54LS/74LS606 SN54LS/74LS SN54LS/74LS605 SN54LS/74LS607

features of decade counter 74196

Abstract: pin diagram decade counter 74196 Min Max 5 4 S /7 4 S Min Max 54LS /74L S Min Max UNIT 2 0 ns 30 ns , 54/74196 - See 8290 54S/74S196 - See 82S90 54LS/74LS196 DESCRIPTION FEATURES The 'â'˜ 196" is an asynchronously p resetta ble Decade Ripple Counter. It ¡s pa rtitioned into divide-by-2 and divide-by-5 sections w hich can be com bined to count in either BCD (8421) mode or bi-quinary mode , FAN-OUT TABLE(a) PINS DESCRIPTION 5 4 /7 4 5 4 S /7 4 S 54LS /74LS CP 0 C lock (a ctive
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features of decade counter 74196 pin diagram decade counter 74196 74S196 54LS/74LS196 N74LS196N N74LS196F 54LS196F 54LS196W

74LS153

Abstract: LS153 (g) MOTOROLA D E S C R IP T IO N - The LSTTL/M SI S N 54LS /74L S 153 is a very high speed Dual 4-Input Multiplexer with common select inputs and individual enable inputs for each section. It can select tw o bits of data from four sources. The two buffered outputs present data in the true (non-inverted) form. In addition to multiplexer operation, the LS153 can generate any two functions of three variables. The LS1 S3 is fabricated w ith the Schottky barrier diode process for high speed and is
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74LS153 SN54LS153 SN74LS153 SN54LS/74LS153

74LS251

Abstract: 54LS /74L S 25 1 DC CHARACTERISTICS OVER OPERATING TEMPERATURE HAWSE (unless otherwise specified , (M ) MOTOROLA D E S C R IP T IO N - The T T L/M S I SN 54LS /74LS 251 is a high speed 8 -In p ut Digital M ultiplexer. It provides, in one package, the ability to select one bit o f data from up to eight sources. The LS251 can be used as a universal fu n ction generator to generate any logic function of four variables. Both assertion and negation outputs are provided. · · · · · S C H O TTKY PR O C ESS FOR H IG H
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74LS251 SN54LS251 SN74LS251 SN54LS/74LS251

N9334N

Abstract: N9334F See 54LS /74L S 259 for low power version · See the NE590 for 250mA output version LOGIC SYMBOL
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N9334N N9334F S9334F S9334W

74LS674

Abstract: SHIFT REGISTER SN 54LS 74L S 674 h (5) .sMODE STRCLK-s" t ~fc"lr t > MODE SrM :N Ql
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74LS674 Y0-Y15 LS673 LS674 P0-P15

74LS181

Abstract: M O T O R O L A D E S C R IP T IO N - The S N 54LS /74L S 181 is a 4-bit Arithmetic Logic Unit (ALU) which can perform all the possible 16 logic, operations on two variables and a variety of arithmetic operations. · P R O V ID E S 1 0 A R ITH M E TIC OPER A TIO NS A D O . SU BTRA C T , MOTOROLA SCHOTTKY TTL DEVICES 4-168 S N 54L S /74L S 1 81 GUARANTEED OPERATING RANGES SYMBOL vcc , MOTOROLA SCHOTTKY TTL DEVICES 4-171 S N 5 4L S /74L S 1 81 SUM MODE TEST TABLE I
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74LS181 SN54LS181 SN74LS181

ttl 741

Abstract: 1. IC 74IS244 Quad Inverting Bus Transceiver 54L.S/ 74L.S242 Any TTL 5.0 2.4 0.4 12 175 D75 3I,6A,9A 10 Quad , ) 54l.S(2)/ 74L.S241 Any TTL 5.0 2.4 0.4 12 180 D74 9Z 13 Octal Non-inverting Bus Driver (3S) 54I , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi
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74S140 74S40 ttl 741 1. IC 74IS244 74LS244 diagram Fairchild 96106 54LS/74LS374 54LS/74LS256 90CI9 54H/74H40

ttl 7447

Abstract: TTL 7446 Quad Inverting Bus Transceiver 54L.S/ 74L.S242 Any TTL 5.0 2.4 0.4 12 175 D75 3I,6A,9A 10 Quad , ) 54l.S(2)/ 74L.S241 Any TTL 5.0 2.4 0.4 12 180 D74 9Z 13 Octal Non-inverting Bus Driver (3S) 54I , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D73 54LS/74LS240 Vcc E2 SI R r fl r r r r r Iii U Iii liJ Iii Iii LiJ Lü Lü Iii bsl I, OND D74 54LS/74LS241 Vcc Ei isirrrrrrrrr I II Lü LiJ Là lì] Là LiJ Iii lü liJ bsl F, GND D7S 54LS/74LS242 vcc e.2 NC HKiEmEinm
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74LS245 74ILS540 ttl 7447 TTL 7446 TTL 7448 7447 ttl logic diagram of 74LS245 54LS/74LS240 54LS/74LS241 54LS/74LS242 54LS/74LS243 54LS/74LS244 54LS/74LS245

74LS244 diagram

Abstract: fairchild 741 2.0 0.5 4.0 88 D5 3I,6A,9A 9 Quad Inverting Bus Transceiver 54L.S/ 74L.S242 Any TTL 5.0 2.4 0.4 12 , Non-inverting Bus Driver (3S) 54l.S(2)/ 74L.S241 Any TTL 5.0 2.4 0.4 12 180 D74 9Z 13 Octal Non-inverting Bus , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D73 54LS/74LS240 Vcc E2 SI R r fl r r r r r Iii U Iii liJ Iii Iii LiJ Lü Lü Iii bsl I, OND D74 54LS/74LS241 Vcc Ei isirrrrrrrrr I II Lü LiJ Là lì] Là LiJ Iii lü liJ bsl F, GND D7S 54LS/74LS242 vcc e.2 NC HKiEmEinm
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74LS244 fairchild 741 TTL 74LS244 E105 IL 741 54LS/74LS540 54LS/ 74LS240 74LS241 74ILS541

74LS687

Abstract: IC 74l (M) M O T O R O L A DESCRIPTION -T heS N 54LS/74LS682thruS N 54LS/74LS 689are 8-bit magnitude , a n t CONNECTION DIAGRAMS (TOP VIEW ) SN54LS/74LS682 THRU S N 54LS/74LS686 SN64LS/74LS686 , DEVICES 4-347 S N 54L S /74L S 683 · SIM54LS/74LS685 S N 54L S /74L S 687 · S N 54L S /74L S 689 , I MOTOROLA SCHOTTKY TTL DEVICES S N 54L S /74L S 683 · S N 54L S /74L S 685 S N 54L S /74L S 687 · S N 54L S /74L S 689 BLOCK DIAGRAM MOTOROLA SCHOTTKY TTL DEVICES 4-349 S N54LS
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74LS687 IC 74l ls689 74LS682 74ls683 74ls689 54LS/74LS682 54LS/74LS LS682 LS687 LS684 LS686

TTL 7404

Abstract: 7404 TTL Quad Inverting Bus Transceiver 54L.S/ 74L.S242 Any TTL 5.0 2.4 0.4 12 175 D75 3I,6A,9A 10 Quad , ) 54l.S(2)/ 74L.S241 Any TTL 5.0 2.4 0.4 12 180 D74 9Z 13 Octal Non-inverting Bus Driver (3S) 54I , , 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS/74LS03, 7426, 54LS/74LS26 54/7437, 54LS/74LS37, 54/7438, 74LS38, 54/74132, 54S/74S132, 74LS132 03 54
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TTL 7404 7404 TTL TTL 7401 nand ttl 7400 TTL 7414 CI 74LS04 54H/74H04 54S/74S04 54LS/74LS04 54LS/74LS14 54LS/74LS00 54LS/74LS03

rs flip-flop IC 7400

Abstract: 74ls105 /74 and 54L/74L can be immediately upgraded with 54LS/74LS resulting in little or no increase in power , /7400 functtions where 54LS/74LS functions aren't yet available. The low input currents of Low Power , this technique. A comparison of 5400/7400 geometries versus 54LS/74LS geometries is shown in Figure 2 , equivalent 5400/7400 function. For example, the die size of the 54LS/74LS181 4-bit ALU is: 72 mils by 84 mils , allowable power dissipation Maximum numbers of 5400 gates (at 10 mw/gate) Maximum number of 54LS gates (at 2
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rs flip-flop IC 7400 74ls105 TTL LS 7400 74LS series logic gates 7400 fan-out 74LS 3 input AND gate 54/74XX

TTL 7410

Abstract: TTL 7401 Quad Inverting Bus Transceiver 54L.S/ 74L.S242 Any TTL 5.0 2.4 0.4 12 175 D75 3I,6A,9A 10 Quad , ) 54l.S(2)/ 74L.S241 Any TTL 5.0 2.4 0.4 12 180 D74 9Z 13 Octal Non-inverting Bus Driver (3S) 54I , , 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS/74LS03, 7426, 54LS/74LS26 54/7437, 54LS/74LS37, 54/7438, 74LS38, 54/74132, 54S/74S132, 74LS132 03 54
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TTL 7410 TTL 7420 74LS00 TTL TTL 7404 fairchild 9016 IC TTL 74LS00 TTL 74LS04 54LS/74LS26 54LS/74LS37 54H/74H10 54S/74S10 54LS/74LS10 54H/74H20

7404 TTL CMOS

Abstract: TTL 74h04 / 748140 Any TTL 5.0 2.0 0.5 4.0 88 D5 3I,6A,9A 9 Quad Inverting Bus Transceiver 54L.S/ 74L.S242 Any TTL , 175 D73 9Z 12 Octal Non-inverting Bus Driver (3S) 54l.S(2)/ 74L.S241 Any TTL 5.0 2.4 0.4 12 180 D74 , , 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS/74LS03, 7426, 54LS/74LS26 54/7437, 54LS/74LS37, 54/7438, 74LS38, 54/74132, 54S/74S132, 74LS132 03 54
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7404 TTL CMOS TTL 74h04 TTL 7400 fairchild 7404 ttl inverter CI 74LS00 TTL 7404 fairchild 54S/74S20 54LS/74LS20 54H/74H22 74S22 54LS/74LS22 54S/74S40

74ls21 IC

Abstract: SHIFT REGISTER SN 54LS 74L S 674 h (5) .sMODE STRCLK-s" t ~fc"lr t > MODE SrM :N Ql
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74ls21 IC LC74HC21 1743C LC74HC 74LS21 54LS/74

lc74hc139

Abstract: M O T O R O L A D E S C R IP T IO N - The S N 54LS /74L S 181 is a 4-bit Arithmetic Logic Unit (ALU) which can perform all the possible 16 logic, operations on two variables and a variety of arithmetic operations. · P R O V ID E S 1 0 A R ITH M E TIC OPER A TIO NS A D O . SU BTRA C T. C O M P A R E . DOUBLE, PLUS TW ELVE OTHER A R ITH M E TIC OPER A TIO NS · P R O V ID E S ALL 1 6 LO GIC O P E R A TIO N S OF TW O VA RIABLES EXC LU SIVE-O R . C O M P A R E . A N D . N A N D . OR. N O
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lc74hc139 LC74HCT39 74LS139 LC74HC139
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