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50-pin lvds

Catalog Datasheet MFG & Type PDF Document Tags

SIO1007-JV

Abstract: SIO1007 . 3.4.1.3.2 LVDS Flat Panel Interface The development board provides one 50-pin LVDS video interface , abbreviation, a period, and the pin number (e.g., P1.0). 316704-001 / Development Kit User's Manual 7 , defined as: The time difference between a signal at the input pin of a receiving agent crossing the , specifications; i.e., ringback, etc.) and the output pin of the driving agent crossing the switching voltage , the package substrate. A pad is only observable in simulations. Pin The contact point of a
Intel
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DIODE 1334 smd

Abstract: k1306 datasheet . Typ. Max. Units Data Pin Diode Array Amplifier Gain Amplifier LVDS Output Stage , spacing (250 µm) and alignment pin spacing (4600 µm) 52 DO10N LVDS Out Data Output #10 , FEATURES · Power supply 3.3 V · Low voltage differential signal electrical interface (LVDS) · 12 , Receiver: 840 nm PIN diode array · Fiber ribbon: 62.5 µm graded index multimode fiber · MT based optical , (VIN)(1) . ­0.5 V to VCC+0.5 V LVDS Input Differential Voltage (|VID|)(2
Siemens
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V23814-K1306-M130 V23815-K1306-M130 DIODE 1334 smd k1306 datasheet M130 DIODE 709 1334 JD smd diodes 50-pin lvds V23814/15-K1306-M130 D-13623

altlvds_tx

Abstract: vhdl code for lvds receiver 1100 7 0011100 8 00111100 Driving the dual-function DESKEW pin high places the LVDS , diagram of the APEX 20KE LVDS PLLs, including LVDS-specific pin names. 23 AN 120: Using LVDS in , output pin can be placed within two pads of LVDS pins unless separated by a power or ground pin. Use the , software will give an error message for illegal output or bidirectional pin placement next to the LVDS pin , space. LVDS Paired Pin Labeling Information on the dual-purpose paired LVDS pins are displayed in
Altera
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EP20K400E EP20K600E altlvds_tx vhdl code for lvds receiver 10226-1A10VE EP20K1000E ANSI/TIA/EIA-644 800-EPLD EP20K200E EP20K300E

4 pin crystal oscillator

Abstract: 3 pin crystal oscillator ICS556-03 QUAD LVDS OSCILLATOR/BUFFER LVDS CRYSTAL BUFFER Pin Assignment EN1 1 16 EN4 , OSCILLATOR/BUFFER Pin Description 2 ICS556-03 REV D 051310 ICS556-03 QUAD LVDS OSCILLATOR/BUFFER LVDS CRYSTAL BUFFER Pin Number Pin Name Pin Type Pin Description 14 D , /BUFFER LVDS CRYSTAL BUFFER Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 , DATASHEET ICS556-03 QUAD LVDS OSCILLATOR/BUFFER Description Features The ICS556-03 is
Integrated Device Technology
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4 pin crystal oscillator 3 pin crystal oscillator LVDS Crystal

TXDN12

Abstract: VSC9182 Multicast and Broadcast · Serial LVDS 622Mb/s High-Speed Interface with PECL/CML Compatibility and , differential LVDS STS-12/STM-4 inputs · Receives 64 serial 622.08Mb/s STS-12/STM-4 line channels (these 64 , 622.08Mb/s differential LVDS STS-12/STM-4 outputs · Optionally inserts byte-interleaved parity into B1 , Interrupt output pin to signal status changes of internal alarms Test Interface · IEEE P1149.1 test access , until the CONFIG pin is asserted and the next frame boundary is received (signaled by the SYNC input).
Vitesse Semiconductor
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VSC9182 GR253-CORE VSC9186 STM-64 TXDN12 0011bb VSC918 STS-192/STM-64 STS-192/

MAX14979E

Abstract: no3a ) Pin Description PIN NAME 1 COM0- Common LVDS Differential Terminal for Switch 0 , Switch PIN NAME 22 NC2+ Normally Closed LVDS Differential Terminal for Switch 2 23 NO1 , 19-5252; Rev 0; 4/10 High-Bandwidth, ±15kV ESD Protection LVDS Switch The MAX14979E is , differential signal (LVDS) and low-voltage positive emitter-coupled logic (LVPECL) switching applications , 16 Multiplexer/Demultiplexer S Space-Saving, Lead-Free, 36-Pin, 6mm x 6mm TQFN Package Eye
Maxim Integrated Products
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no3a laptop lcd LVDS 26 pin 650MH MIL-STD-883 100MH

AN1003

Abstract: lvds 32 pin Translator 8 PIN SOIC / MSOP 3.0V to 5.5V LVDS to PECL / LVPECL Translator 8 PIN SOIC / MSOP , AN1004 Interfacing Between LVDS and ECL / LVECL / PECL / LVPECL HIGH-PERFORMANCE PRODUCTS About LVDS Interfacing LVDS with PECL and LVPECL As the bandwidth increases in Telecom / Datacom and even in consumer / commercial applications , the high speed, low power, noise, and cost of LVDS , . Signal level translation between PECL / LVPECL to LVDS can be achieved using resistor divider network
Semtech
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AN1003 lvds 32 pin SK1303

vhdl code for lvds driver

Abstract: LVDS 51 connector Driving the dual-function DESKEW pin high places the LVDS inputs in calibration mode. The calibration , pin names. 23 AN 120: Using LVDS in APEX 20KE Devices Figure 13. LVDS PLL Block Diagram 4 , . EP20K300E devices support using LVDS on dedicated clock signals and LVDS data in bypass (1) mode in the 652-pin ball-grid array (BGA) and 672-pin FineLine BGA packages. EP20K200E and smaller devices support using LVDS , reducing board space. LVDS Paired Pin Labeling Information on the dual-purpose paired LVDS pins are
Altera
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vhdl code for lvds driver LVDS 51 connector verilog code for lvds driver

verilog code for lvds driver

Abstract: vhdl code for lvds driver 1100 7 0011100 8 00111100 Driving the dual-function DESKEW pin high places the LVDS , , including LVDS-specific pin names. 23 AN 120: Using LVDS in APEX 20KE Devices Figure 13. LVDS PLL , and LVDS data in bypass (×1) mode in the 652-pin ball-grid array (BGA) and 672-pin FineLine BGA , space. LVDS Paired Pin Labeling Information on the dual-purpose paired LVDS pins are displayed in , , LVDSRXINCLK1p. LVDS pins have a specific naming convention: all LVDS pin names begin with LVDS. The next two
Altera
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LVDS connector 30 pins

ICS556-03

Abstract: ICS556-03I output. IDTTM / ICSTM QUAD LVDS OSCILLATOR/BUFFER Pin Description 2 ICS556-03 REV C 092309 ICS556-03 QUAD LVDS OSCILLATOR/BUFFER LVDS CRYSTAL BUFFER Pin Number Pin Name Pin Type , DATASHEET ICS556-03 QUAD LVDS OSCILLATOR/BUFFER Description Features The ICS556-03 is a clock oscillator with quad LVDS outputs. Using a standard 25 MHz crystal, no additional external components are required to generate quad LVDS outputs at 25 MHz. · · · · · · This product is
Integrated Device Technology
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ICS556-03I U-09-01
Abstract: LVDS CRYSTAL BUFFER Pin Number 14 15 Pin Name D EN3 Pin Type Output Input Differential , LVDS CRYSTAL BUFFER Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm , DATASHEET QUAD LVDS OSCILLATOR/BUFFER Description The ICS556-03 is a clock oscillator with quad LVDS outputs. Using a standard 25 MHz crystal, no additional external components are required to generate quad LVDS outputs at 25 MHz. This product is intended for clock generation. It has low output Integrated Device Technology
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199707558G

EXS00A

Abstract: 4x10G output swing LVDS output, AC coupled w/ 100 diff load HCSL output, 50 load to GND on each output pin , Switching SPI, I2CTM, and Pin Programmable Professional user GUI for Quick Design Turnaround 7 x 7 mm 48 , , LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, wireline data , I2C or SPI programming interface and in the absence of serial interface, pin mode is also available , outputs using fractional dividers. The CDCM6208 is packaged in a small 48-pin 7mm x 7mm QFN package
Texas Instruments
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EXS00A 4x10G EXS00A-CG EXS00A-CG02813 SCAS931B 48-QFN ISO/TS16949

tolerance j12

Abstract: LVDS 30 pin connector cable DS90CR485 transmitter DS_OPT pin (J6) automatically generates an LVDS switching pattern at the LVDS outputs , The TSEN pin reports the presence of a remote termination resistor on the LVDS clock line. The user , . 1.01 MDR Connector Transmitter LVDS Output Pin # Receiver LVDS Input NAME Pin # NAME , 17 Transmitter PRBS Generator Mode . 19 LVDS Cable Sense (TSEN) Status Flag . 19 Pin & Signal Assignments
National Semiconductor
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CLINK3V48BT-133 tolerance j12 LVDS 30 pin connector cable LVDS connector 30 pin MDR 68 pin configuration LVDS connector 40 pins NAME connector 30 pin IDC DS90CR485/486 CLINK3V485/486

J504 lcd connector

Abstract: JP504 : J104 Aux / LVDS Interface Pin Description â'" MityARM/MityDSP without FPGA Pin Signal Type Standard , Aux / LVDS Interface Pin Description â'" MityARM/MityDSP with FPGA Installed Pin Signal Type , Interface ï'· SD/MMC Card Socket ï'· Audio Output Expansion: ï'· 3 50-pin IO Expansion Slots ï , ) controller for external display connection with DDC support. Interface to QVGA\WQVGA display via 5 pair LVDS , SATA Header Battery (RTC) USB0 SATA 10-pin Header TRS232E RS232 PHY RJ-45 &
Critical Link
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J504 lcd connector JP504 ARM-1810 1810F DSP-L138 L138F RS485 ARM-1808

VSC9182

Abstract: Switch with Nonblocking 768x768 STS-1 Switch Matrix · Supports Both Multicast and Broadcast · Serial LVDS , switch configuration (address map) Input Backplane Interface · Serial 622.08Mb/s differential LVDS , Serial 622.08Mb/s differential LVDS STS-12/STM-4 outputs Optionally inserts byte-interleaved parity into , output pin to signal status changes of internal alarms Test Interface · IEEE P1149.1 test access port , memory. The programming does not take effect until the CONFIG pin is asserted and the next frame boundary
Vitesse Semiconductor
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GR-253CORE G52289
Abstract: 01/03/11 PI6LC4840 Crystal to LVDS/LVCMOS Frequency Synthesizer Pin Number Pin Name I , PI6LC4840 Crystal to LVDS/LVCMOS Frequency Synthesizer Features Description Ãà 3.3V , 125Mhz having both LVDS and LVCMOS outputs for maximum flexibility. One 25Mhz LVCMOS non-PLL output is also available. Ãà Three banks of outputs: àà Bank A: 3 25/50MHz pin selectable LVCMOS outputs àà Bank B: 3 125MHz LVCMOS outputs àà Bank C: 3 125MHz LVDS outputs Ãà 25MHz LVCMOS Pericom Semiconductor
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125MH 25/50MH FL2500029 PS9076 4402B
Abstract: Bias Current (Each Pin) LVDS CLOCK OUTPUTS Output Frequency Differential Output Voltage Offset , CTRL_A CTRL_A selects either CMOS (high) or LVDS (low) logic for Output 1 and Output 0. This pin has an , 1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer ADCLK846 FUNCTIONAL BLOCK DIAGRAM FEATURES ADCLK846 LVDS/CMOS OUT0 (OUT0A) OUT0 (OUT0B) VREF OUT1 (OUT1A) CLK OUT1 (OUT1B) CLK CTRL_A LVDS/CMOS OUT2 (OUT2A) OUT2 (OUT2B) OUT3 (OUT3A) APPLICATIONS Low jitter clock Analog Devices
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LVDS/12 MO-220-VGGD-2 CP-24-2 ADCLK846BCPZ ADCLK846BCPZ-REEL7 ADCLK846/PCBZ

IDT5V5216

Abstract: 5V5216 IDT5V5216 1 Single Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver PIN ASSIGNMENT NC , 2 Single Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver PIN DESCRIPTION , /LVDS Drivers Enable This pin controls the Type-1/Type-2 M-LVDS receiver and LVTTL/LVPECL/LVDS drivers , /LVPECL/LVDS Interface Input/Output This pin globally determines the type of input/output of the LVTTL , output signal can be LVPECL or LVDS, as selected by the DIFF_SEL pin. OUT_A: LVTTL Output This pin
Integrated Device Technology
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5V5216 Figure10 TSSOP14 pin assignment lvds PGG14

lvds 32 pin

Abstract: XCV300E Note Number AN-C1-FPGALVDS-A FPGA LVDS INTERFACE APPLICATION NOTE SIMPLIFY BOARD LAYOUT USING LVDS TERMINATORS INTRODUCTION 140 ohms, whereas the series pair consists of 165 ohms each , of flexible Input/Output interfaces including Low Voltage Differential Signaling (LVDS). The , . See Figure 1 below. 1/8 of RT1723B6/B7 1/16 of RT1722B7 Virtex-E FPGA 2.5 V Z0=50 LVDS Q 165 140 Data Transmit 165 Z0=50 Q LVDS To LVDS Receiver To LVDS Receiver
CTS Frequency Products
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XCV300E RT1710B6 RT1723B6 Xilinx XCV300 of 30 pin LVDS BG432 RT1710B6/B7 RT1710B7 RT1723B7
Abstract: SPI, I2Câ"¢, and Pin Programmable Professional user GUI for Quick Design Turnaround 7 x 7 mm 48 , inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of , serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed , packaged in a small 48-pin 7mm x 7mm QFN package. Additional list of FEATURES Supply Voltage: The , LVDS signaling. TJ lab characterization measured 8 pspp, (typical) and 12 pspp (max) over PVT Texas Instruments
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SCAS931A
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