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Part Manufacturer Description Datasheet BUY
CD74ACT139-W Texas Instruments Dual 2-to-4 Line Decoder/Demultiplexer 0-WAFERSALE visit Texas Instruments
M38510/30702BEA Texas Instruments Dual 2-Line To 4-Line Decoders/Demultiplexers 16-CDIP -55 to 125 visit Texas Instruments
M38510/30701BEA Texas Instruments 3-Line To 8-Line Decoders/Demultiplexers 16-CDIP -55 to 125 visit Texas Instruments
74ACT11139DRE4 Texas Instruments Dual 2-Line to 4-Line Decoder/Demultiplexer 16-SOIC -40 to 85 visit Texas Instruments
74ACT11238D Texas Instruments 3-Line To 8-Line Decoders/Demultiplexers 16-SOIC -40 to 85 visit Texas Instruments
SN54155J Texas Instruments Dual 2-Line To 4-Line Decoders/Demultiplexers 16-CDIP -55 to 125 visit Texas Instruments

5 to 32 line decoder block diagram

Catalog Datasheet MFG & Type PDF Document Tags

LDB6234

Abstract: HDB3 Multiplexer Block Diagram .11 1.7.4 E1/E3 Demultiplexer Block Diagram .12 1.7.4.1 E3 line Interface , LXT6234 E-Rate Multiplexer 1.7.5 E Demultiplexer Block Diagram Figure 5 shows the I/O used on the , . 8 1.7.2 E1/E3 Multiplexer Block Diagram , Demultiplexer Block
Intel
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AN9501 LDB6234 HDB3 HDB3 decoder multiplexing e1 frame to e3 frame E1 HDB3 E2 liu

BT 136 PIN DIAGRAM

Abstract: DSI bt.656 2-2 2-3 2-4 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 4-1 ZiVA Family of Products ZiVA Decoder High-level Block Diagram ZiVA Decoder in a Typical DVD Player Application ZiVA Decoder in Multimedia PC , 26 28 30 32 32 33 34 35 36 36 37 38 38 39 40 40 43 44 44 45 45 45 45 46 47 48 48 3 ZiVA Decoder , Formats Audio Decoder and Output Interface Datapath 32-Bit Wide User Data FIFO Organization ZiVA-DS and ZiVA-D6 Decoders Logic Diagram 2 4 6 7 15 18 19 21 25 27 29 31 32 34 37 40 42 43 47 52 Figures xvii
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BT 136 PIN DIAGRAM DSI bt.656 BT 151 internal dvd pinout C-Cube microsystems BT 151 PIN DIAGRAM

saa5000

Abstract: 5 / 4/ 4/ 5 /' Block Diagram of the CCZ3005-I C CZ3005J Central Control Unit with , A/D Converter HV Sync â  G e n e ra to r. 5K 2 /' l2C/lM-Bus 6, Block Diagram of the , (CCU3001) port lines Assembler or â'Câ' programmable P40 (R/W) P1 (D0.D7) Block Diagram of , , 32 kBytes ROM, and 1024 Bytes RAM. An IM/I2C master interface, a 5-input ADC, ports and 6 PWM , circuit. Features: - CPU with 6 MHz clock (3 MIPS) Closed-Caption Decoder 3-line caption mode
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OCR Scan
saa5000 CCU3000 3000-I 3001-I PLCC68 65C02 CCU3000/CCU3001

SPB-492

Abstract: MB87L2250 active. 3.6.2. Display Unit (VO_DISP) VO_DISP Block Diagram to VO_CTRL line, pos next_line default , DECODER Figure 10: Video Decoder Top Level Block Diagram 3.6. Video Output Interface The Video , written to the RAM (to address hflt_ram_adr[5:2]). 3.6.4. On Screen Display (VO_OSD) VO_OSD Block Diagram to VO_CTRL adr, req, hold to VO_RAM data 16 line, hpos OSD_CTRL to VO_DISP 8 data alpha 5 16 256x16 CM_RAM Figure 14: Block Diagram of VO_OSD 16 Fujitsu
Fujitsu
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MB87L2250 SPB-492 block diagram of audio decoder dvb-c demultiplexer DVB-C top set box mpeg-1 video decoder and arbiter FPT-208P-M01

dad1000

Abstract: dlp dad1000 algorithm, the TVP5160 successfully applies TI's patented 2D, 5-line comb filter to those portions of the , /TVP5147M1 5-Line Comb Filter NTSC/PAL/SECAM Video Decoder -TVP5146M2 Low-Cost Video Decoder , system providers the ability to release both NTSC and PAL models without changing the decoder , package options all at the most competitive price Complete Decoder Solutions Providing the ability to , TVP5147M1 1 1 2 10 9 Bit (30 MHz) 11 Bit (30 MHz) 8 Bit 4:2:2 10/20 Bit 4:2:2 4-Line 5-Line -
Texas Instruments
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dad1000 dlp dad1000 ddp2000 dlp ddp2000 lcd projector china DVD player card circuit diagram

CL9100

Abstract: BT 151 PIN DIAGRAM Products Figure 1-2AViA Decoder High-level Block Diagram Figure 1-3AViA-500 Decoder in a Typical DBS , 4-1AViA-50x Decoder Logic Diagram Figure 5-1Host Interface Internal Architecture Figure 5-2M Mode Write to , System Figure 3-1Data Flow Diagram Figure 3-2High-level Microcode Tasks Figure 3-3AViA Decoder Bitstream , from Host with M-Mode Writes and CSTROBE Figure 6-1AViA Decoder Interface to AViA-GTX or AViA-DMX , Interface Block Diagram Figure 8-2Audio DAC Interface Clocking Modes Figure 8-3I2S Bus Waveform Figure
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CL9100 CL9100 MPEG C-CUBE cl9100 AVIA-GTX avia Avia-500 A-502 11-3C 11-4T 12-1E 12-2I 12-3I

PCM encoder circuit ami

Abstract: AMI encoding block diagram to be transmitted to the line. A com plimentary decoder circuit is also included in the chip for decoding received signals from an external line receiver. Both encoder and decoder functions can be , allow for in-circuit testing. Receive Positive Data. NRZ input data to the decoder block. Sampled on the , RCLK RCLKO V (Note 5) RPOS RNEG V (Note 5) RNRZ BPV Figure 4. Decoder Output Timing Diagram , cable. The IC Is designed to complement the XR-T7295 DS3/SONET STS-1 Integrated Line Receiver. It con
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OCR Scan
PCM encoder circuit ami AMI encoding block diagram XR-T7296 736MBPS 368MBPS T7296
Abstract: ) encoding functions for data to be transmitted to the line. A com­ plimentary decoder circuit is also , Receive Positive Data. NRZ input data to the decoder block. Sampled on the falling edge of RCLK. 28 , decoder block is included to perform B3ZS or HDB3 decoding as determined by the state of the T3/E3 pin , -/ RNRZ _ I BPV Figure 4. Decoder Output Timing Diagram Note 5 : The V pulse is a , Line Receiver. It con­ verts input clock, and unipolar POS and NEG data into AMI pulses according to -
OCR Scan
DS31STS

E1 HDB3

Abstract: pin diagram 14 demultiplexer Multiplexer Block Diagram The block diagram of the E1/E3 Multiplexer is shown in Figure 2. E1 LINE , data and clock to the SXT6234. 9 10 11 12 13 E Multiplexer Block Diagram 14 The block , demultiplexer this pin should be tied to the demultiplexer clock DHMUXC. DHNRZO HDB3 decoder #5 NRZ data , x 32 time slots = 256 bits/frame 5. Since 8000 frames are transmitted each second, the bit rate is , or NRZ I/O to the multiplexer and demultiplexer. Alternatively, the SXT6234 can be used as a 5
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SDB6234 pin diagram 14 demultiplexer HDB3 to nrz 16 line to 4 line coder multiplexer HDB3 E2 1 into 12 demultiplexer circuit diagram how to interface microcontroller with encoder 16-E1/E3 16E1/E3

HDB3 E2

Abstract: multiplexing e1 frame to e3 frame Multiplexer Block Diagram The block diagram of the E1/E3 Multiplexer is shown in Figure 2. E1 LINE , data and clock to the SXT6234. 9 10 11 12 13 E Multiplexer Block Diagram 14 The block , demultiplexer this pin should be tied to the demultiplexer clock DHMUXC. DHNRZO HDB3 decoder #5 NRZ data , x 32 time slots = 256 bits/frame 5. Since 8000 frames are transmitted each second, the bit rate is , NRZ I/O to the multiplexer and demultiplexer. Alternatively, the SXT6234 can be used as a 5
Level One Communications
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multiplexing e2 frame e3 1 into 16 demultiplexer circuit diagram using 1 i design 16 bit demultiplexer introduction multiplexing demultiplexing e2 e3 crystal oscillator 8.448 1 into 4 demultiplexer circuit diagram

smd transistor SAK

Abstract: TRANSISTOR SMD sAK 14 decoder/sync processor Application Note AN96101 Fig A1 Block diagram of the TDA9144: Filters and , Note AN96101 2.2.2 Colour Decoder The block diagram is shown in figure A2 at the end of this , Multistandard decoder/sync processor Application Note AN96101 Fig A3 Block diagram of the TDA9144 , trap is automatically bypassed (internal SWT switch switches to path (b), refer block diagram Filters , 5 Philips Semiconductors TDA9144 Multistandard decoder/sync processor Application Note
Philips Semiconductors
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TDA4665 TDA9141 TDA9143 smd transistor SAK TRANSISTOR SMD sAK 14 colour tv chroma section smd transistor yc 622 TDA9176 TDA9151 PC74HCU04 AN94041

VP23

Abstract: 3RA6 . 3 5. FUNCTIONAL BLOCK DIAGRAM . 4 6. PERFORMANCE OVERVIEW , Clock generating circuit Data slicer Fig. 5.1 Functional Block Diagram of M37273 TIM2 TIM3 Timer count source selection circuit Program counter 5. FUNCTIONAL BLOCK DIAGRAM Data bus ROM , . 32 characters 2 lines (It is possible to display 3 lines or more by software) Kinds of characters , / Output Functions Apply voltage of 5 V ± 10 % to (typical) VCC and 0 V to VSS. This is connected to VSS
Mitsubishi
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VP23 3RA6 M37273MFH M37273MFH-XXXSP M37273EFSP M37273M8-XXXSP M37273E8SP
Abstract: . 3 5. FUNCTIONAL BLOCK DIAGRAM . 4 6. PERFORMANCE OVERVIEW , M3727G Program counter 5. FUNCTIONAL BLOCK DIAGRAM RAM PCL (8) Timer 2 T2 (8) Timer 3 T3 (8 , caption decoder. The features of the M37272E8SP/FP are similar to those of the M3727GM6/M8-XXXSP/FP except , . 32 characters 2 lines (It is possible to display 3 lines or more by software) Kinds of characters , 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Mitsubishi
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M3727GM6/M8 M3727GM6-XXXSP/FP M3727GM8-XXXSP/FP 3727GM6/M8

tv ic M37272

Abstract: m37272m DECODER and ON-SCREEN DISPLAY CONTROLLER 5. FUNCTIONAL BLOCK DIAGRAM Fig. 5.1 Functional Block , . 32 characters 2 lines (It is possible to display 3 lines or more by software) Kinds of , BLOCK DIAGRAM . 4 13. A-D CONVERTER CHARACTERISTICS , ) counter Program 14 P 1 ( 8) 28 29 30 31 32 33 34 35 I/O port P1 10 9 8 7 6 5 4 3 I/O , Power source CNVSS Input/ Output CNVSS Functions Apply voltage of 5 V ± 10 % to (typical
Mitsubishi
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tv ic M37272 m37272m M37272M6H/M8H/MAH/MFH M37272EFSP/FP M37272M6H/M8H/MAH/MFH-XXXSP/FP M37272M6H-XXXSP/FP M37272M8H-XXXSP/FP M37272MAH-XXXSP/FP

pm10 mitsubishi

Abstract: . 3 5. FUNCTIONAL BLOCK DIAGRAM . 4 6. PERFORMANCE OVERVIEW , -BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 5. FUNCTIONAL BLOCK DIAGRAM Fig. 5.1 Functional Block Diagram of M3727G Rev. 1.0 MITSUBISHI MICROCOMPUTERS , . 32 characters 2 lines (It is possible to display 3 lines or more by software) Kinds of , PCL (8) counter Program 14 28 29 30 31 32 33 34 35 I/O port P1 10 9 8 7 6 5 4 3 I
Mitsubishi
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pm10 mitsubishi

CDL17

Abstract: M37273E8SP MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 5. FUNCTIONAL BLOCK DIAGRAM , . 3 12. ELECTRIC CHARACTERISTICS . 98 5. FUNCTIONAL BLOCK DIAGRAM , caption decoder. M37273EFSP is used at the time of program creation. Please refer to Data Sheet of , . 32 characters 2 lines (It is possible to display 3 lines or more by software) Kinds of , . 5 14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS . 100 7. PIN DESCRIPTION
Mitsubishi
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CDL17 P30C dc23 op WN25

BC24

Abstract: vp23 . 3 5. FUNCTIONAL BLOCK DIAGRAM . 4 6. PERFORMANCE OVERVIEW , M3727G Program counter 5. FUNCTIONAL BLOCK DIAGRAM RAM PCL (8) Timer 2 T2 (8) Timer 3 T3 (8 , caption decoder. The features of the M37272E8SP/FP are similar to those of the M3727GM6/M8-XXXSP/FP except , . 32 characters 2 lines (It is possible to display 3 lines or more by software) Kinds of characters , 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Mitsubishi
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BC24

block diagram of speech recognition

Abstract: 16 QAM Transmitter block diagram . 35 Encoder Block Diagram . 38 V.32 Signal , Frequency Shift . 91 V.32 Modem Block Diagram , . 296 Lower Sub-Band Encoder Block Diagram . 297 Higher Sub-Band Decoder Block Diagram . 298 Lower Sub-Band Decoder Block Diagram . , . 11 Transmitter Block Diagram . 19 Receiver
Analog Devices
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ADSP-2100 block diagram of speech recognition 16 QAM Transmitter block diagram 32 QAM Transmitter block diagram goertzel algorithm circuit diagram of speech recognition 16 QAM receiver block diagram ADSP-2101 ADSP-2111 ADSP-21

dm5160

Abstract: September 25, 2013 10 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Block Diagram Video , . 9 BLOCK DIAGRAM , , M, Nc) and SONY 960H CCD Camera l Video decoder could be programmed to operate at 27 or 36MHz. l , addition to CVBS, the DM5160 video decoder supports S-Video as well. Video Synchronization Video , block CVBS signal is separated into Luma and Chroma components. A 5-H 2D comb filter is adapted in the
DAVICOM Semiconductor
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DM5160-DS-P01

CDL26

Abstract: selection system for TV with a closed caption decoder. The features of the M37272E8SP/FP are similar to , FUNCTIONAL BLOCK DIAGRAM of M37272M8-XXXSP/FP MITSUBISHI MICROCOMPUTERS M37272M8-XXXSP/FP M37272E8SP , connected to a ceramic resonator or a quartzcrystal oscillator) Built-in 32 characters ! 2 lines (maximum , P3 P31/AD6 Analog input 6 Functions Apply voltage of 5 V ± 10 % (typical) to VCC and AVCC , register N-channel open-drain output Ports P06, P0 7 Data bus Fig. 1. I/O Pin Block Diagram (1
Mitsubishi
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CDL26
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