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Part Manufacturer Description Datasheet BUY
TMS416100-80DZ Texas Instruments 16MX1 FAST PAGE DRAM, 80ns, PDSO24 visit Texas Instruments
TMS416800P-70DZ Texas Instruments 2MX8 FAST PAGE DRAM, 70ns, PDSO28 visit Texas Instruments
TMS417400-60DZ Texas Instruments 4MX4 FAST PAGE DRAM, 60ns, PDSO24 visit Texas Instruments
TMS45160L-80DZ Texas Instruments 256KX16 FAST PAGE DRAM, 80ns, PDSO40 visit Texas Instruments
TMS45160S-10DZ Texas Instruments 256KX16 FAST PAGE DRAM, 100ns, PDSO40 visit Texas Instruments
TMS465169P-40DGE Texas Instruments 4MX16 EDO DRAM, 40ns, PDSO50 visit Texas Instruments

4464 dram

Catalog Datasheet MFG & Type PDF Document Tags

4464 dram

Abstract: DRAM 4464 4416/4464 DRAM â  Light Pen Interface PIN CONFIGURATION Total 5 Chips Set Solution All 40 Pin Dip
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Abstract: Information Organization Speed Dimensions Power DRAM Die Revision IBM11S1320LNA-60 1M x 32 , "5 UCÃ"5 ÃS U2 ÃE E : LCÃ"5 £ RAS2 CÃ"S2 CAS3 27H 5212 S A 1 4 -4464 -01 , at the end of this document. Page 6 of 20 lO O b H L DQODSbS 24T 27H5212 S A 14 -4464 , data are read/written into the device. CASO & CAST or CAS2 & CAS3 (CASâ'™s t o t h e s a m e DRAM , applicable to this product, but applies to a related product in this family. 27H5212 S A 1 4 -4464 -01 -
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IBM11S1320LN IBM11S1320LL 11S1320LN 00GG577

DRAM 4464

Abstract: MX-1610 1" x .0965" 2.35" x 1" x .0965" Power 3.3V 3.3V 5.0V 5.0V 3.3V 3.3V 5.0V 5.0V DRAM Die Revision C C , < IBM11S1320LN IBM11S1320LL 1M x 32 SODIMM Module Block Diagram 27H 5212 S A 1 4 -4464 -01 R evised 7 /9 5 , Output Capacitance (DQ0-DQ34) C|3 C|4 Ciò 27H 5212 S A 1 4 -4464 -01 R evised 7 /9 5 ©IBM , are read/written into the device. CASO & CAS1 or CAS2 & CAS3 (CAS'S T O T H E SAME DRAM) cannot be , -4464 -01 R evised 7 /9 5 ©IBM Corporation, 1995. All rights reserved. Use is further subject to the
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DRAM 4464 MX-1610 IBM11S1320LN/L SA14-4464-01

DRAM 4464

Abstract: 4464 dram SDRAM Modules (1) Synchronous DRAM Modules Vcc= +3.3V±0.3V, Ta=0°C to +70°C Power Consumption max. (mW) (Bunt mode) down Mod» Organization (Wxb) Part Number Mounted Device Clock [Capacity] x Frequency CLK number max. «Package» (MHZ) Access Bank Time 1 max. (ns) Access Time 2 max , 9 8.5 8.5 9 8.5 8.5 9 8.5 8.5 1944 1800 1620 3888 3600 3312 3888 3600 3312 4752 4464 4176 4752 4464 4176 4374 4050 3726 5346 5022 4698 4320 3744 2880 4320 3744 2880 4896 4320 3456 4896 4320 3456
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4464 dram 2mx64 sdram B8501S064AC-100 MB8501S064AC-84 MB85Q1S064AC-67 B8502S064AC-100 MB8502S064AC-84 MB8502S064AC-67

ic 74138

Abstract: IC 7402, 7404, 7408, 7432, 7400 414000 (DRAM 1-bit) 44 Serial 4464 44256 441000 (DRAM 4-bit) -
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ic 74138 IC 7402, 7404, 7408, 7432, 7400 ic 74139 IC 74147 IC 74373 74148 IC 89/336/EEC EN50081-1 EN50082-1 EN55022 IEC801-2 EN60555-2

NEC D2732

Abstract: 41C1000 New Page 1 DRAM ORGANIZATION/ DENSITY FUJISTU GOLDSTAR HITACHI HYNDAI MB GM HM HY 256K x 1(256K) 81256 71C256 51256 MICRON MT 53C256 1256 MITSUBISHI M5M 4256 1M x 1(1M) 81C1000 71C1000 511000 531000 4C1024 41000 256K x 4(1M) 81C4256 71C4256 , 5116160 416160 4LC1M16C3 5118160 5118160 418160 DRAM continued below ORGANIZATION/ MOTOROLA , 8K x 8(64K) 4464 5165 6264 5864B 5564 5565 32K x 8(256K) 43256 51256/51257
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41C1000 27C32 27C32Q NEC D2732 41256 6264 SRAM 44256 dram NEC 2732 4C4256 71C4400 4C4001 71C4100 4C1004 71C4260

3654P

Abstract: DRAM 4464 To Top / Lineup / Index Product Line-up Memory Volatile memory 4M-bit DRAM (5.0V) RAM 4M-bit DRAM (3.3V) 16M-bit DRAM (5.0V) 16M-bit DRAM (3.3V) 16M-bit SDRAM 64M-bit SDRAM SGRAM DRAM Modules (5.0V) DRAM Modules (3.3V) SDRAM Modules Non-Volatile memory Rewritable , Cards DRAM Flash Memory Mask ROM To Top / Lineup / Index 4M-bit DRAM (5.0V) Capacity DRAM (CMOS) Supply Voltage Organization Type 4M-bit 5.0V 4M×1 Fast page mode
Fujitsu
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MB814405D MB814260 3654P jeida dram 88 pin 1024M-bit 4464 64k dram mb814400a-70 MB814400A MB814400D MB814405C MB814400C MB814100D

dram 64kx1

Abstract: ba05 (DMA) data transfers. â  Directly controls up to 64K bytes of dynamic RAM (DRAM) â  Provides , Manufacturer Part Qty 8031 Microprocessor 32K byte EPROM 64K X 4 DRAM 64KX1 DRAM (parity) optional SCSI , ]-1 COMPARE REFRESH COUNTER ADDRESS OUT MUX PROGRAMMABLE SEQUENCER RAM ADRS DRAM BUFFER , speeds allows the BC 2 to support a wide range of DRAM cycle times. See the following table. Bit Divide , 400 ns 500 ns 1 0 6 250 ns 300 ns 375 ns 1 1 4 250 ns DRAM Cycle Time All four DMA channels
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dram 64kx1 ba05 architecture of 8031 microprocessor 8031 microprocessor 4164 dram 4164 dynamic ram 332D5D3 D0G1313
Abstract: . RESOLUTION REQUIREMENTS DRAM CLOCK RESOLUTION COLORS 120 ns 28 MHz 720 x 400 16 120 ns 25 MHz , -bit dynamic RAMâ'™s should be used to configure 256K byte of video memory. The supported speed of DRAM and , the method of clocking the CRT Controller. A logical 0 selects three refresh DRAM cycles. A -
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VL82C037 VL82C037-FC TL431 74ALS245 74ALS244 74LS244

samsung GDDR5

Abstract: K4D263238K-VC40 July 2007 K4D263238K 128M GDDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM , operation, even numbers of Din are to be written inside DRAM 2. The number of clock of tRP is restricted by , 23.12 25.6 28.76 30.36 34.24 34.88 39.48 38.96 44.64 42.64 49.48 45.76 53.92 48.4 57.92 50.48 61.56 , Updated : April 2009 K4XXXXXXXX - XXXXXXX 1 1. Memory (K) 2. DRAM : 4 3. Small Classification N
Samsung Electronics
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170FBGA samsung GDDR5 K4D263238K-VC40 GDDR5 application note samsung K4D263238K-VC50 tcl 2272 GDDR GDDR2 GDDR3 GDDR4 GDDR5 84FBGA 100FBGA 96FBGA 136FBGA

82C568

Abstract: 82C567 policy: - Write-back - Adaptive write-back - Write-through DRAM interface Supports both Unified Memory , 5.0V DRAM devices Supports 64-bit wide DRAM devices with 256KB, 512KB, 1MB, 2MB, 4MB, 8MB, and 16MB addressing Supports DRAM configurations up to 512MB Six banks of FP mode DRAMs (7-3-3-3 at 66MHz) Six banks of EDO DRAM support with auto detection (5-2-2-2 at 66MHz) Four banks of BEDO (burst EDO) (X-1-1-1 at 66MHz) Four banks of SDRAM (synchronous DRAM) (X-1-1-1 at 66MHz) Figure 1-1 Viper-MAX System Block
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82C566 82C567 82C568 HA20C md4203 AD7166 lclk131 82C566/82C567/82C568 P55CT 667MH

K4D263238K

Abstract: K4D263238K-UC50 K4D263238K 128M GDDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional , , even numbers of Din are to be written inside DRAM AC CHARACTERISTICS (II) K4D263238K-UC40 Frequency , -41.36 -36.08 -44.64 -37.64 -47.64 -38.84 -50.28 -39.84 -52.56 -40.68 -54.56 -41.4 -56.28 -42.04 -57.76
Samsung Electronics
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K4D263238K-UC50

4464 64k dram

Abstract: TMS4461 Simplify System Design Random-Access Port Is Compatible with the TMS4464, 64K x 4 DRAM Supported by Tl , look as if it is organized as 6 5 ,5 3 6 w ords of four bits each, like the TM S 4464. The , serial port interface The TM S4461 M ultiport Video RAM consists o f a 64K x 4 DRAM port and a 256 x 4 serial port. Each o f the four random (DRAM) l/Os is interfaced to a 2 5 6 -b it data register th a t can , transferred, 256 bits in parallel, into any row of m em ory fo r each respective DRAM I/O channel. block
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TMS4461 TMS34061 TMS4461-12 tms34010 TMS4464-12NL DRAM Video RAM 144-BIT 25-MH TMS34010

70413080

Abstract: 70473180 ) 70404328 STEREO D/A CONV. 4464 64K X 4 70424464 100NS D-RAM 4465 64K X 4 D-RAM
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70413080 70473180 SAC-187 Motorola 70483180 70483100 70484200 2N3391 SPS-953 MPS-8097 2N6520 MPS-A18 2N6539

K4D263238K-UC50

Abstract: K4D263238KUC50 K4D263238K 128M GDDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional , Note :1 For normal write operation, even numbers of Din are to be written inside DRAM AC , -25.76 -26.6 -30.16 -29.52 -34.12 -32.12 -37.88 -34.28 -41.36 -36.08 -44.64 -37.64 -47.64 -38.84 -50.28
Samsung Electronics
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K4D263238KUC50 K4D263238K-UC bt 824 6008

K4D263238K

Abstract: K4D263238K-VC40 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES · 2.5V ± 5 , be written inside DRAM 2. The number of clock of tRP is restricted by the number of clock of tRAS , 38.96 44.64 42.64 49.48 45.76 53.92 48.4 57.92 50.48 61.56 52.04 64.72 53.24 67.28 54.16
Samsung Electronics
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Abstract: Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES · 2.5V ± 5% power supply for , numbers of Din are to be written inside DRAM 2. The number of clock of tRP is restricted by the number of , 23.12 25.6 28.76 30.36 34.24 34.88 39.48 38.96 44.64 42.64 49.48 45.76 53.92 48.4 57.92 50.48 61.56 Samsung Electronics
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MPSC16

Abstract: FM0 encoder IC Interface to i960Hx and i486 with minimal glue logic · DRAM controller - 128Mbyte address space - , channels support the communications controllers - Moves data between communications controllers and DRAM , 3.3V supply, 5V tolerant · 208-pin PQFP i960Jx AD BUS ADDR CTL GT-96010 LEDS DRAM , . 3.4 DRAM Controller , . 4.4.1 DRAM, Device, and Internal Address Decode Registers. 4.4.1.1
Galileo Technology
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MPSC16 FM0 encoder IC mpsc46 MR5 Relay TCDT 1102 D PF0148 256K-4M 10/20-M

all ic data

Abstract: arm7tdmi Package = 22.32 µm/0.6 µm N = 12.6 µm/0.6 µm INV8 driver has transistor sizes of p = 44.64 µm/0.6 µm , a fast memory mode (for example DRAM page mode) and/or to bypass the address translation system
Atmel
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all ic data arm7tdmi Package ARM coprocessor
Abstract: family of CPUs - Interface to i960Hx and i486 with minimal glue logic DRAM controller - 128Mbyte , controllers and DRAM - One independent DMA for memory to memory, device to memory, or device to device data , .18 DRAM Controller , . 34 4.4.1 DRAM, Device, and Internal Address Decode Registers. 34 4.4.1.1 DRAM Address Space, Offset: 0x000. 34 4.4.1.2 -
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9601O
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