NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Counter 4-Stage Synchronous Bidirectional Counter Hex D Flip-Flop w/Master Reset Quad D-Type Flip-Flop , Synchronous Presettable Binary Counter 16 Hex D Flip-Flop w/Master Reset 16 Quad D-Type Flip-Flop 16 , Latch w/Cut-Off Drivers Hex D-Type Latch Hex D-Type Flip-Flop 8-Bit Buffer w/Cut-Off Drivers 8-Bit , 16-Bit D Flip-Flop w/3-STATE Outputs 18-Bit Registered Bus Transceiver w/3-STATE Outputs 18-Bit , /3-STATE Outputs Octal D Flip-Flop w/3-STATE Outputs Octal D-Type Flip-Flop w/Clock Enable Quad 2-Port ... | Original |
95 pages, |
texas cmos databook 4011 cmos logic gate 74ACT161 HC 4093 HC 4011 logic gate cmos databook cmos logic 4001 series Sj 47 diode CD4503BC 4017 decade counter 1-of-10 SJ 76 A DIODE EMI quad single supply 50 Ohm Line Drivers NTE 4023 datasheet abstract |
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| Abstract: Hex D Flip-Flop, Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . Dual D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . Octal D Flip-Flop/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal D Flip-Flop with Enable . . . . . . . . . . ... | Original |
13 pages, |
74ls795 74LS299 74ls113a 74LS398 datasheet abstract |
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| Abstract: ATA6020N ATA6020N Pin Description Name Type Function Alternate Function Pin Number SS020 SS020 Reset , register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use , or carrying out of the arithmetic logic unit (ALU) occurred during the last arithmetic operation. , This flag is affected by arithmetic, logic, shift, and rotate operations. 4.1.3.10 Interrupt , scheduled for later execution. 4.1.7.4 Hardware Interrupts In the ATA6020N ATA6020N, there are eleven hardware ... | Original |
69 pages, |
SSO20 BP40 BP23 ATAM893 ATA6020N ATAM893 abstract |
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| Abstract: flip-flop may be read in and the port flip-flop may be written by derivative port instructions. However, the port flip-flop of P1.3/RTCLK must remain set to avoid conflicts between the 16 kHz clock and port , Table 3 DESCRIPTION This bit will always read a logic 0. These 3-bits specify the power of two in , (CLCR) 4.4.1 Table 4 Clock Control Register (address ACH; access type R/W) 7 6 5 4 , must be fixed at a logic 0 by user software. 6 TST1 Test 1 input. This is a testing bit and ... | Original |
92 pages, |
TRX 434 RF TRANSMITTER t-con lvds mrf 510 keyboard encoder 16*8 80C51 memory 9652 MD 2103 DFH datasheet abstract |
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| Abstract: flip-flop may be read in and the port flip-flop may be written by derivative port instructions. However, the port flip-flop of P1.3/RTCLK must remain set to avoid conflicts between the 16 kHz clock and port , PS0 Table 3 DESCRIPTION This bit will always read a logic 0. These 3-bits specify the power of , REGISTER (CLCR) Table 4 Clock Control Register (address ACH; access type R/W) 7 6 5 4 , must be fixed at a logic 0 by user software. 6 TST1 Test 1 input. This is a testing bit and ... | Original |
92 pages, |
t-con lvds MD 2103 DFH 80C51 mrf 510 ise4 transistor MRF 254 datasheet abstract |
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| Abstract: D-type flip-flop with an Exclusive-OR gate on the input. The OLMC allows each GLB output to be , · Registered D, T, J-K Synch/Asynch Clocking Outputs to GRP, ORP or I/O Logic Array , LSC Logo, Generic Array Logic, In-System Programmability, In-System Programmable, ISP, ispATE , logic with its UltraMOS E2CMOS technology. This technology, combined with the Lattice GAL architectures, have established Lattice products as the industry standard in low density programmable logic ... | Original |
501 pages, |
7408 ic truth table PAL16l8 MMI PAL AM 16v8 XOR 7486 GATE semiconductor handbook 7486 xor gate ic pin diagram of ttl 74112 GAL programming Guide laf 0001 pin DIAGRAM OF IC 7486 data sheet IC 7408 vhdl code for vending machine pin configuration of 7486 IC datasheet abstract |
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| Abstract: (7) LCD controller · Adapt to both Shift register type and Built-in RAM type LCD driver (8 , (PC4) SCLK1/ CTS1 (PC5) OPTRX0 (P72) OPTTX0 (P71) SIO/UART (SIO1) W A B C D E H L IX , Port 9 Port C Port D LCD controller CS0 (LCLK0) to CS3 / CS2A (P60 to P63) EA24, CS2B (P64 , area. Lcd CLK: Command controll C/S for S/R type lcdd. 1 I/O Output Port 61: I/O port (with , Output Lcd CLK: Command controll C/S for S/R type lcdd. Pomp-up CLK for external LCD driver 1 I ... | Original |
278 pages, |
panel and detecter block diagram PDCR 800 pressure TMP91C016F TMP91C016 JTMP91C016S 451H PDCR 900 pressure TLCS-900/L1 TLCS-900/L1 abstract |
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| Abstract: (7) LCD controller · Adapt to both Shift register type and Built-in RAM type LCD driver (8) Timer , C D E H L IX IY IZ SP 32 bit F SR PC C Clock Gear, Clock Doubler L-OSC D0 D7 , INPUT PORT B PORT C PORT D D1BSCP (PD0) D2BLP (PD1) D3BFR (PD2) DLEBCD (PD3) DOFFB (PD4 , address area. Lcd CLK: Command controll C/S for S/R type lcdd. P61 /CS1 1 I/O Output Port , : Command controll C/S for S/R type lcdd. Pomp-up CLK for external LCD driver Pin Name I/O D8 to ... | Original |
280 pages, |
TMP91C016 TLCS-90 PDCR 800 pressure P71C 451H PDCR 900 DMA 3 YEER DATE SHEET PDCR 900 pressure TLCS-900/L1 TLCS-900/L1 abstract |
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| Abstract: Port B 3.5.10 Port C 3.5.11 Port D 3.6 Chip Select / Wait Controller 3.7 8-bit Timers(TMRA) 3.8 , TMP91C815 TMP91C815 (8) LCD controller · Adapt to both Shift register type and Built-in RAM type LCD driver (9 , ) 10-bit A/D converter : 8 channels (12) Watch dog timer (13) Melody/Alarm generator · Melody: Output of , ) CPU (TLCS-900/L1 TLCS-900/L1) 10-BIT 10-BIT 8CH A/D CONVERTER SIO/UART/IrDA (SIO0) SIO/UART (SIO1) SERIAL BUS I/F(SBI) 8BIT TIMER (TMRA0) XW A XBC XDE XHL XIX XIY XIZ XSP H-OSC W A B C D ... | Original |
277 pages, |
um 66 melody generator datasheet TMP91C815F TLCS-90 TLCS-900/L1 TLCS-900/L1 abstract |
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| Abstract: 3.5.8 Port A 3.5.9 Port B 3.5.10 Port C 3.5.11 Port D 3.6 Chip Select / Wait Controller 3.7 8-bit , without notice. 91C025-1 91C025-1 TMP91C025 TMP91C025 (7) LCD controller · Adapt to both Shift register type and Built-in RAM type LCD driver (8) Timer for real-time clock (RTC) · Based on TC8521A TC8521A (9) Key-on wake up (Interrupt key input) (10) 10-bit A/D converter: 4 channels (11) Touch Screen Interface · Available to , TMP91C025 TMP91C025 AN2/MX(P82 ) AN3/MY/ADTRG (P83) AN0 , A N1 (P80 , P81) 10-BIT 10-BIT 4C H A/D CONVERTER ... | Original |
259 pages, |
TMP91C025F RKH ah 12 hour digital clock using 7490 TLCS-900/L1 TLCS-900/L1 abstract |
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| use IOB flip-flops Xilinx Answer #424 : XABEL 5.0 and XC7000 XC7000 XC7000 XC7000 EPLDS: The .D extension is not #138 : PROMS: How to program a 'D' type prom from a different type master prom Xilinx Answer #139 /XC3000/XC4000/XC5200 /XC3000/XC4000/XC5200 /XC3000/XC4000/XC5200 /XC3000/XC4000/XC5200: What set, reset capabilities do the 2000. 4000, 5200 flip flops have Boundary Scan in a 3000 device Xilinx Answer #246 : VIEWsynthesis: Infering an xc4000 `set' flip-flop or an inverted xc3000`reset' flip-flop Xilinx Answer #250 : XDM fails, 'can't find termcap www.datasheetarchive.com/files/xilinx/docs/wcd00000/wcd00072-v1.htm |
Xilinx | 16/02/1999 | 433.95 Kb | HTM | wcd00072-v1.htm |
| : How to program a 'D' type prom from a different type master prom Xilinx Answer #139 : Data I /XC3000/XC4000/XC5200 /XC3000/XC4000/XC5200 /XC3000/XC4000/XC5200 /XC3000/XC4000/XC5200: What set, reset capabilities do the 2000. 4000, 5200 flip flops have a 3000 device Xilinx Answer #246 : VIEWsynthesis: Infering an xc4000 `set' flip-flop or an inverted xc3000`reset' flip-flop Xilinx Answer #250 : XDM fails, 'can't find termcap.xct, aborting #310 : FITNET DRC error, flip flop using both SET and RESET Xilinx Answer #311 : PPR 5.0: PPR www.datasheetarchive.com/files/xilinx/docs/wcd00000/wcd0005b.htm |
Xilinx | 17/07/1998 | 357.17 Kb | HTM | wcd0005b.htm |
| device Xilinx Answer #138 : PROMS: How to program a 'D' type prom from a different type master prom capabilities do the 2000. 4000, 5200 flip flops have? Xilinx Answer #152 : FPGA: Default configuration of components in HDL? Xilinx Answer #246 : VIEWsynthesis: Infering an xc4000 `set' flip-flop or an inverted xc3000 `reset' flip-flop Xilinx Answer #249 : BBS: Getting control characters on screen in work with the XACT 5.0 PC install program Xilinx Answer #310 : FITNET DRC error, flip flop using www.datasheetarchive.com/files/xilinx/docs/rp00002/rp00254.htm |
Xilinx | 29/02/2000 | 662.64 Kb | HTM | rp00254.htm |
| + Positive node, 2,N- Negative node, 1, 7, 1,Type (Linear/Nonlinear),ON/OFF, 2, 5, 1,Nc , 2,N- Negative node, 1, 7, 1,Type (Linear/Nonlinear),ON/OFF, 2, 5, 1,Nc+ Positive of source, 1, 8, 1,Type (Linear/Nonlinear),ON/OFF, 2, 6, 2,Controlling Voltage source source, 2,N- Negative node of source, 1, 8, 1,Type (Linear/Nonlinear),ON/OFF, 2, 6, 2 ,Number of Lumps,n,N=, *D,Junction Diode,D,2,13, 1,N1 Positive node, 2,N2 Negative node www.datasheetarchive.com/files/kaleidoscope/cad/visionics_edwinxp140/edwinxp/sys/elements.spc |
Kaleidoscope | 15/09/2004 | 444.15 Kb | SPC | elements.spc |
| /catalog/appnotes/29362.html Applicationnotes for Flip flops Title Date AN203 AN203 AN203 AN203 2: Test Fixtures for High for Logic Title Date AN202 AN202 AN202 AN202 1: Testing and specifying FAST logic 1987-06-01 AN2021 AN2021 AN2021 AN2021 1: Thermal considerations for FAST logic products 1995-03-13 AN203 AN203 AN203 AN203 2: 25 1 0 /catalog/appnotes/27113.html Applicationnotes Applicationnotes for Full adders Title Date AN202 AN202 AN202 AN202 1: Testing and specifying FAST logic 1987-06-01 AN2021 AN2021 AN2021 AN2021 1: Thermal considerations for FAST logic products 1995-03-13 AN203 AN203 AN203 AN203 2: 37 1 0 /catalog/appnotes/27324.html Applicationnotes www.datasheetarchive.com/files/philips/search/docindex.txt |
Philips | 25/04/2003 | 954.24 Kb | TXT | docindex.txt |
| /parametrics/39.html Parametrics NE556D Function Timers Category Timers, oscillators and counters Timer Type Dual /parametrics/10.html Parametrics TSA5512M/C3 TSA5512M/C3 TSA5512M/C3 TSA5512M/C3 Temperature Range -10 to +80 Application 12C Peripherals Circuit Type Category 4 1 0 /catalog/parametrics/12.html Parametrics TDA8010M/C1 TDA8010M/C1 TDA8010M/C1 TDA8010M/C1 Total gain min/max dB -17/40 NOISE FIGURE MAX dB 10 Local oscillator buffer and prescaler Supply current mA 70 One 5 1 0 /catalog .2 Gp min f min dB 16.5 DESCRIPTION Cascade Amps S11 10.0 f max ?14 Gp typ f min 9 1 0 /catalog www.datasheetarchive.com/files/philips/search/docindex-v2.txt |
Philips | 14/02/2002 | 998.47 Kb | TXT | docindex-v2.txt |
| : These bits control the type of SRAMs used to construct L2 cache. 00 - asynchronous SRAM ram type and the programmed burst parameters. A value of 0 for this field is the least optimal Control Register 0, this register controls the read/write attributes of the memory located at 0xD0000-0x cycle 1: shadow enabled for write cycle Bit 5 d8shren: This bit controls the read attribute of the 0xD8000-0xDBFFF memory. 0: shadow disabled for read cycle www.datasheetarchive.com/download/49127042-847939ZC/gr-v1.zip (REG.TXT) |
STMicroelectronics | 16/12/1998 | 632.06 Kb | ZIP | gr-v1.zip |
| , Constraints, and Carry Logic" (chapter 12 of Libraries Guide). For All Platforms For Kb Uploaded: 10-16-1998 Constraints Editor Presentation: Explains what type of Q1/98 Q1/98 Q1/98 Q1/98 The Quarterly Journal for Xilinx Programmable Logic Users For All Platforms Guide mansim.pdf 3,655KB 655KB 655KB 655KB Foundation Logic Simulator Users Guide mentor.pdf 2 Foundation toolset) vlintrfc.pdf 2,121KB 121KB 121KB 121KB ViewLogic Interface Guide vlogintdoc.pdf 107KB 107KB 107KB 107KB www.datasheetarchive.com/files/xilinx/docs/wcd0003c/wcd03cd9.lst |
Xilinx | 12/02/1999 | 179.16 Kb | LST | wcd03cd9.lst |
| , Constraints, and Carry Logic" (chapter 12 of Libraries Guide). For All Platforms type of constraints can be created with the editor. Explains basic constraining methodolgy 955 Kb XCell Journal #27 Q1/98 Q1/98 Q1/98 Q1/98 The Quarterly Journal for Xilinx Programmable Logic Users Schematic Editor Users Guide mansim.pdf 3,655KB 655KB 655KB 655KB Foundation Logic Simulator Guide (VHDL Compiler for Foundation toolset) vlintrfc.pdf 2,121KB 121KB 121KB 121KB ViewLogic www.datasheetarchive.com/files/xilinx/docs/wcd00002/wcd00270-v1.htm |
Xilinx | 16/02/1999 | 285.52 Kb | HTM | wcd00270-v1.htm |
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75 Macrocell Flip-Flop Da ta B oo k The Programmable Logic Data Book Click anywhere on this page to continue 's leading supplier of programmable logic, we would like to pledge our continuing commitment to providing you functionality and ease-of-use in programmable logic development systems. You can expect this pace of innovation -edge programmable logic solutions to the market. We look forward to satisfying all of your programmable logic needs www.datasheetarchive.com/download/90212243-999460ZC/dbookold.zip (DBOOKOLD.PDF) |
Xilinx | 07/09/1996 | 10340.01 Kb | ZIP | dbookold.zip |