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CS5351-BZZR Cirrus Logic 108 dB, 192 kHz Stereo A/D Converter ri Buy
CS5331A-BSR Cirrus Logic 8-Pin Stereo A/D Converters ri Buy
CS5360-BSR Cirrus Logic 24-Bit, 48 kHz Stereo A/D Converter ri Buy

4174 logic hex D type flip-flop

Catalog Datasheet Results Type PDF Document Tags
Abstract: Counter 4-Stage Synchronous Bidirectional Counter Hex D Flip-Flop w/Master Reset Quad D-Type Flip-Flop , Synchronous Presettable Binary Counter 16 Hex D Flip-Flop w/Master Reset 16 Quad D-Type Flip-Flop 16 , Latch w/Cut-Off Drivers Hex D-Type Latch Hex D-Type Flip-Flop 8-Bit Buffer w/Cut-Off Drivers 8-Bit , 16-Bit D Flip-Flop w/3-STATE Outputs 18-Bit Registered Bus Transceiver w/3-STATE Outputs 18-Bit , /3-STATE Outputs Octal D Flip-Flop w/3-STATE Outputs Octal D-Type Flip-Flop w/Clock Enable Quad 2-Port ... Original
datasheet

95 pages,
2666.22 Kb

cmos databook cmos logic 4001 series HC 4093 CD4503BC msa 520 HC 4011 logic gate NTE 4023 74F190 4017 decade counter 1-of-10 Sj 47 diode quad single supply 50 Ohm Line Drivers application MM74C926 7400 functional cross-reference datasheet abstract
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Abstract: Hex D Flip-Flop, Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . Dual D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . Octal D Flip-Flop/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal D Flip-Flop with Enable . . . . . . . . . . ... Original
datasheet

13 pages,
50.76 Kb

ttl buffer 74LS245 74LS08 fan-out 74LS08 TTL 74ls113a 74LS299 74LS73 74ls795 74LS14 Hex Inverter definition MC74F579 74LS398 74LS08 fan-in datasheet abstract
datasheet frame
Abstract: ATA6020N ATA6020N Pin Description Name Type Function Alternate Function Pin Number SS020 SS020 Reset , register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use , or carrying out of the arithmetic logic unit (ALU) occurred during the last arithmetic operation. , This flag is affected by arithmetic, logic, shift, and rotate operations. 4.1.3.10 Interrupt , scheduled for later execution. 4.1.7.4 Hardware Interrupts In the ATA6020N ATA6020N, there are eleven hardware ... Original
datasheet

69 pages,
671.82 Kb

SSO20 BP40 BP23 ATAM893 ATA6020N ATAM893 abstract
datasheet frame
Abstract: instructions for P1.3/RTCLK. Therefore, the state of both port line and flip-flop may be read in and the port flip-flop may be written by derivative port instructions. However, the port flip-flop of P1.3/RTCLK must , \7 \7 7 \ 8-bít internal bus O ) A D 0 to A D 7 ( ') < ^ I 16-BIT 16-BIT TIMER/EVENT COUNTER WITH , factor; see Table 3. This bit will always read a logic 0. These 3-bits specify the power of two in the , Control Register (address ACH; access type R/W) 6 TST1 5 ERCO 4 RUN 3 CIF 2 1 ITS1 0 ITSO TST2 Table 5 ... OCR Scan
datasheet

86 pages,
2547.73 Kb

datasheet abstract
datasheet frame
Abstract: flip-flop may be read in and the port flip-flop may be written by derivative port instructions. However, the port flip-flop of P1.3/RTCLK must remain set to avoid conflicts between the 16 kHz clock and port , Table 3 DESCRIPTION This bit will always read a logic 0. These 3-bits specify the power of two in , (CLCR) 4.4.1 Table 4 Clock Control Register (address ACH; access type R/W) 7 6 5 4 , must be fixed at a logic 0 by user software. 6 TST1 Test 1 input. This is a testing bit and ... Original
datasheet

92 pages,
465.67 Kb

TRX 434 RF TRANSMITTER transistor MRF 254 t-con lvds MRF transistor 237 mrf 510 keyboard encoder 16*8 80C51 memory 9652 MD 2103 DFH datasheet abstract
datasheet frame
Abstract: flip-flop may be read in and the port flip-flop may be written by derivative port instructions. However, the port flip-flop of P1.3/RTCLK must remain set to avoid conflicts between the 16 kHz clock and port , PS0 Table 3 DESCRIPTION This bit will always read a logic 0. These 3-bits specify the power of , REGISTER (CLCR) Table 4 Clock Control Register (address ACH; access type R/W) 7 6 5 4 , must be fixed at a logic 0 by user software. 6 TST1 Test 1 input. This is a testing bit and ... Original
datasheet

92 pages,
433.57 Kb

t-con lvds MD 2103 DFH 80C51 mrf 510 ise4 transistor MRF 254 datasheet abstract
datasheet frame
Abstract: /RTCLK. Therefore, the state of both port line and flip-flop may be read in and the port flip-flop may be written by derivative port instructions. However, the port flip-flop of P1.3/RTCLK must remain set to , will always read a logic 0. These 3-bits specify the power of two in the division factor of the UART , Control Register (address ACH; access type R/W) 6 TST1 5 ERC0 4 RUN 3 CIF 2 - 1 ITS1 0 ITS0 Description , at a logic 0 by user software. Test 1 input. This is a testing bit and must be fixed at a logic 0 by ... Original
datasheet

92 pages,
459.97 Kb

datasheet abstract
datasheet frame
Abstract: Port A 3.5.9 Port B 3.5.10 Port C 3.5.11 Port D 3.6 Chip Select / Wait Controller 3.7 8-bit Timers(TMRA , (8) LCD controller · Adapt to both Shift register type and Built-in RAM type LCD driver (9) Timer for real-time clock (RTC) · Based on TC8521A TC8521A (10) Key-on wake up (Interrupt key input) (11) 10-bit A/D converter , (PC1) SCLK0/CTS0/DSPRD(PC 2) TXD1 (PC3) RXD1 (P C4) SCLK1/CTS1/D SPW R(PC5) PX/INT2 (PB5) PY/INT3 (PB6) 10-B IT 4CH A/D CONVERTER CPU (T LCS-900/L1 LCS-900/L1) H-OSC Clock Gear, Clock Doubler DVCC [2] DVSS [2 ... Original
datasheet

250 pages,
2358.13 Kb

stop watch using 7490 12 hour digital clock using 7490 mxic dsp TLCS-900/L1 TMP91C025F TLCS-900/L1 abstract
datasheet frame
Abstract: yx 801 led 6821 6820 pia yx 801 led pl 74L73 yx 801 led driver 1702a eprom RAM 2102 yx 805 led driver ferranti ula pia 6820 is turned off the statem ent could be false. Depend ing on the type of logic circuits used, the , O ... OCR Scan
datasheet

273 pages,
114732.62 Kb

PUSH PULL MOSFET DRIVER watts 4017-DECADE COUNTER 8251 usart intel 8080 MCS s100 bus specification transistor equivalent book te 1570 TRIAC zo 607 MA 0897-X 0897-X abstract
datasheet frame
Abstract: ) XWA XBC XDE XHL XIX XIY XIZ XSP W A B C D E H L IX IY IZ SP 32 bits SR F PC L-OSC AM0 AM1 , Port 8 Port 9 Port A Port B Port C Port D Port E Port F D1BSCP (PD0) D2BLP (PD1) D3BFR (PD2) DLEBCD , : Address 000FE0H 000FE0H to 000FFFH 000FFFH is assigned for the external memory area of built-in RAM type LCD driver. And , access to the logic address 000000H 000000H to 000FDFH 000FDFH, 001000H 001000H to 002FFFH 002FFFH and FFE000H FFE000H to FFFFFFH, A0 to A23 ... Original
datasheet

360 pages,
3012.44 Kb

TMP91C820AFG TLCS-900/L1 TLCS-900/L1 abstract
datasheet frame

Datasheet Content (non pdf)

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Over 1.1 million files (1986-2014): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.
 
Answer #138 : PROMS: How to program a 'D' type prom from a different type master prom Xilinx Answer device Xilinx Answer #246 : VIEWsynthesis: Infering an xc4000 `set' flip-flop or an inverted xc3000`reset' flip-flop Xilinx Answer #250 : XDM fails, 'can't find termcap.xct, aborting' Xilinx Answer designs Xilinx Answer #432 : How flip-flop initial states are determined Xilinx Answer #434 /XC4000 /XC4000 /XC4000 /XC4000: Can I source ACLK/GCLK from internal logic? BUFGS, BUFGP? Xilinx Answer #117 : FPGA
www.datasheetarchive.com/files/xilinx/docs/wcd00000/wcd00072-v1.htm
Xilinx 16/02/1999 433.95 Kb HTM wcd00072-v1.htm
And Capacitance Without An A/D 1993-12-01 AN202 AN202 AN202 AN202 1: Testing and specifying FAST logic 1987-06-01 AN2021 AN2021 AN2021 AN2021 Logic Title Date AN202 AN202 AN202 AN202 1: Testing and specifying FAST logic 1987-06-01 AN2021 AN2021 AN2021 AN2021 1: Thermal considerations for FAST logic products 1995-03-13 AN203 AN203 AN203 AN203 2: 25 1 0 /catalog/appnotes/27113.html Applicationnotes for Title Date AN202 AN202 AN202 AN202 1: Testing and specifying FAST logic 1987-06-01 AN2021 AN2021 AN2021 AN2021 1: Thermal considerations for FAST logic products 1995-03-13 AN203 AN203 AN203 AN203 2: 37 1 0 /catalog/appnotes/27324.html Applicationnotes for
www.datasheetarchive.com/files/philips/search/docindex.txt
Philips 25/04/2003 954.24 Kb TXT docindex.txt
program a 'D' type prom from a different type master prom Xilinx Answer #139 : Data I/O Tech Support 3000 device Xilinx Answer #246 : VIEWsynthesis: Infering an xc4000 `set' flip-flop or an inverted xc3000`reset' flip-flop Xilinx Answer #250 : XDM fails, 'can't find termcap.xct, aborting' Xilinx Answer Orcad designs Xilinx Answer #432 : How flip-flop initial states are determined Xilinx Answer #434 /XC4000 /XC4000 /XC4000 /XC4000: Can I source ACLK/GCLK from internal logic? BUFGS, BUFGP? Xilinx Answer #120 : VST gets stuck
www.datasheetarchive.com/files/xilinx/docs/wcd00000/wcd0005b.htm
Xilinx 17/07/1998 357.17 Kb HTM wcd0005b.htm
,N- Negative node, 1, 7, 1,Type (Linear/Nonlinear),ON/OFF, 2, 5, 1,Nc+ Positive Negative node, 1, 7, 1,Type (Linear/Nonlinear),ON/OFF, 2, 5, 1,Nc+ Positive controlling Node , 1, 8, 1,Type (Linear/Nonlinear),ON/OFF, 2, 6, 2,Controlling Voltage source,control, 3, 1 source, 2,N- Negative node of source, 1, 8, 1,Type (Linear/Nonlinear),ON/OFF, 2, 6, 2 transmission line,l,L=,Meters, 3, 1, 2,Number of Lumps,n,N=, *D,Junction Diode,D,2,13, 1,N1
www.datasheetarchive.com/files/kaleidoscope/cad/visionics_edwinxp140/edwinxp/sys/elements.spc
Kaleidoscope 15/09/2004 444.15 Kb SPC elements.spc
XC4000 XC4000 XC4000 XC4000 device Xilinx Answer #138 : PROMS: How to program a 'D' type prom from a different type : Infering an xc4000 `set' flip-flop or an inverted xc3000 `reset' flip-flop Xilinx Answer #249 : BBS Answer #432 : How flip-flop initial states are determined Xilinx Answer #433 : FPGA COMPILER 3.1a ACLK/GCLK from internal logic? BUFGS, BUFGP? Xilinx Answer #117 : FPGA Configuration: Preparing a &_logic_1_.map' Xilinx Answer #201 : PACKAGING: sources for socket converters and test sockets Xilinx
www.datasheetarchive.com/files/xilinx/docs/rp00002/rp00254.htm
Xilinx 29/02/2000 662.64 Kb HTM rp00254.htm
No abstract text available
www.datasheetarchive.com/download/49127042-847939ZC/gr-v1.zip (REG.TXT)
STMicroelectronics 16/12/1998 632.06 Kb ZIP gr-v1.zip
Type Multimedia ICs Category Synthesizers Number of Pins 20 Function Synthesizers 3 1 0 /catalog /parametrics/18.html Parametrics BAL74 BAL74 BAL74 BAL74 I F mA 50 C D max. pF 2.0 I FSM max A 4.0 V F max mV 1000 V 11 1 0 Logic Switching Levels TTL Package Material Plastic Bit Width Other 14 1 0 /catalog/parametrics/24.html Parametrics 74HCT4059N 74HCT4059N 74HCT4059N 74HCT4059N Speed Low Series HC/T Logic Switching Levels CMOS Desired Maximum Propagation Delay Range ns 15 to 50 Number of Pins 15 1 0 /catalog/parametrics/25.html Parametrics BUK7514-55 BUK7514-55 BUK7514-55 BUK7514-55 I D max 100
www.datasheetarchive.com/files/philips/search/docindex-v2.txt
Philips 14/02/2002 998.47 Kb TXT docindex-v2.txt
Noise Exponent,af,AF=, , , , 43, 1, 3,PNP,type, , , , , 44, 1, 3,Inverse early voltage:forward Noise exponent,af,AF=, , , , 43, 1, 3,PNP,type, , , , , 44, 1, 3,Inverse early voltage:forward ,DEFW=,Meters, , , 4, 1, 2,Width correction factor,narrow,NARROW=,Meters, , , *D,Junction Diode, ,16 ,Flicker noise Coefficent,kf,KF=, , , , 14, 1, 2,Flicker noise Exponent,af,AF=, , , , 15, 1, 3,Type ,Flicker noise Coefficent,kf,KF=, , , , 14, 1, 2,Flicker noise Exponent,af,AF=, , , , 15, 1, 3,Type
www.datasheetarchive.com/files/kaleidoscope/cad/visionics_edwinxp140/edwinxp/sys/models.spc
Kaleidoscope 15/09/2004 811.67 Kb SPC models.spc
No abstract text available
www.datasheetarchive.com/download/90212243-999460ZC/dbookold.zip (DBOOKOLD.PDF)
Xilinx 07/09/1996 10340.01 Kb ZIP dbookold.zip
A/D 1993-12-01 AN202 AN202 AN202 AN202 1.pdf: Testing and specifying FAST logic 1987-06-01 AN2021 AN2021 AN2021 AN2021 1.pdf: 179 1 0 /appnotes/16840.html Applicationnotes for General purpose Title Date AN00014 AN00014 AN00014 AN00014 1.pdf: TDA8766G TDA8766G TDA8766G TDA8766G 10-bit A/D converter demonstration board 2002-12-16 AN00018 AN00018 AN00018 AN00018 1.pdf: TDA8764ATS TDA8764ATS TDA8764ATS TDA8764ATS 10-bit A/D converter demonstration board /27063.html Applicationnotes for Logic Title Date AN10161 AN10161 AN10161 AN10161 2.pdf: PicoGate Logic footprints 2002-10-30 AN202 AN202 AN202 AN202 1.pdf: Testing and specifying FAST logic 1987-06-01 AN2021 AN2021 AN2021 AN2021 1.pdf: Thermal considerations for FAST
www.datasheetarchive.com/files/philips/search/docindex-v1.txt
Philips 16/06/2005 2589.32 Kb TXT docindex-v1.txt