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Part Manufacturer Description Datasheet BUY
TMS416400-80DZ Texas Instruments 4MX4 FAST PAGE DRAM, 80ns, PDSO24 visit Texas Instruments
TMS416400-10DZ Texas Instruments 4MX4 FAST PAGE DRAM, 100ns, PDSO24 visit Texas Instruments
TMS416400-70DZ Texas Instruments 4MX4 FAST PAGE DRAM, 70ns, PDSO24 visit Texas Instruments
TMS416400-60DGA Texas Instruments 4MX4 FAST PAGE DRAM, 60ns, PDSO24, PLASTIC, TSOP-26/24 visit Texas Instruments
TMS416400-80DGA Texas Instruments 4MX4 FAST PAGE DRAM, 80ns, PDSO24, PLASTIC, TSOP-26/24 visit Texas Instruments
TMS416400A-70DGA Texas Instruments 4MX4 FAST PAGE DRAM, 70ns, PDSO24, PLASTIC, TSOP-26/24 visit Texas Instruments

4164 dram

Catalog Datasheet MFG & Type PDF Document Tags

dram 4164

Abstract: 4164 64k dram sampling rate of 25KHz when combined with an external DRAM (41256/4164). The HT8955A is superior to an , A0 A1 A2 A3 A4 A5 A6 A7 DRAM 4164 WRB VSS VDD DI DO CASB 20 1 , · · Operating voltage: 5.0V Long delay time ­ 0.8 seconds (SEL=VSS, 256K DRAM) ­ 0.2 seconds (SEL=VDD/open, 64K DRAM) 25KHz sampling rate Continuous variable delay time Echo generators Sound , consists of a built-in pre-amplifier, onchip oscillator, DRAM interface, 10 bit A/D and D/A converters as
Holtek
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LM386 dram 4164 4164 64k dram 4164 dram bbd delay variable delay audio preamplifier 41256 dram 3000P

IPC 4104

Abstract: 4116 DRAM 4.4 Graphics DRAM Controller registers CR3C - DRAM Timing Parameter register CR3D-DRAM Arbitration , 4.6.2 4.6.3 4.6.4 4.6.5 Host DRAM controller registers DRAM Bank 0 register DRAM Bank 1 register DRAM Bank 2 register DRAM Bank 3 register Memory Bank Width DRAM Bank 0 Timing Parameter register Graphics memory size register Memory Type register DRAM Bank 1 Timing Parameter register DRAM Refresh DRAM Bank 2 Timing Parameter register DRAM Bank 3 Timing Parameter register ADPC PCI related
STMicroelectronics
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IPC 4104 4116 DRAM C 4751-1 0X094 0x00000001 0x10-0x13

dram 4164

Abstract: 41256 logic â  ROM decoder for one 2764 and one 27256 â  RAM decoder for 4164 or 41256 DRAM â  H/W and S , DMA controller, channel 0 is used for DRAM refresh â  82C59 8 channel interrupt controller, level 0 , Is used for system ' time base, channel 1 for DRAM refresh, and channel 2 for speaker audio â
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41256 74670 register UM82C088 82C84 82C88 82C37 82C53 82C55

information applikation

Abstract: U880D k t s n o n i k Heft 30: HALBLEITERSPEICHER Teil 2 SRAM und DRAM v e b halbleiterw , Inhetliebnahme/ Nachnutzung 28 7«.2t4,?* Dynamische Sehreib-/Lese-Speicher (DRAM) Grundlagen. Prinzip der dynamischen Speicherzelle 8.1.1. 8.1.2. Aufbau von DRAM - Schaltkreisen Funktionsweise und Betriebsarten von DRAM's 8.1.38.1.3.1. Adressierung 8.1.3.2. Betriebsarten 8.1.3.3. Datenausgang 8. 8.1. 31 31 31 33 34 34 35 37 38 33 Biographie wichtiger DRAM - Typen. T J 256 C/D Kurzcharakteristik Schaltbild
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information applikation U880D information applikation mikroelektronik Halbleiterbauelemente DDR mikroelektronik applikation

41256 dram

Abstract: 4164 dram with an external DRAM (41256/4164). The HT8955A is superior to a conventional BBD delay unit in its , · · Operating voltage: 5.0V Long delay time ­ 0.8 seconds (SEL=VSS, 256K DRAM) ­ 0.2 seconds (SEL=VDD/open, 64K DRAM) 25kHz sampling rate Continuous variable delay time Echo generators Sound , pre-amplifier, on-chip oscillator, DRAM interface, 10-bit A/D and D/A converters as well as control logic. It , Connects to DRAM A6 12 A7 O CMOS OUT Connects to DRAM A7 Delayed audio signal output pin
Holtek
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PCB digital echo sound AUDIO DELAY CIRCUIT DIAGRAM HT8955 PCB echo sound Echo Processor IC delay Digital Signal Processor for Karaoke

ic 74138

Abstract: IC 7402, 7404, 7408, 7432, 7400 4532 4539 4543 4551 4553 4555 4556 4560 4561 4566 4572 4581 4584 4585 41 Serial 4164 41256 411000 414000 (DRAM 1-bit) 44 Serial 4464 44256 441000 (DRAM 4-bit) -
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ic 74138 IC 7402, 7404, 7408, 7432, 7400 ic 74139 IC 74147 IC 74373 74148 IC 89/336/EEC EN50081-1 EN50082-1 EN55022 IEC801-2 EN60555-2

80387SX

Abstract: 41256 88C212 provides higher performance over the conventional DRAM accessing schemes. As a result, the 88C212 can support a 16 Mhz system with 100 ns DRAM by the use of the Page-Interleaved mode. The 88C212 also , the real mode and protected mode. A staggered DRAM refresh scheme is also included to reduce the power , ±0.12 Unit (mm) DRAM Type Total Memory EMS Range BankO Bankl Bank2 Bank3 1 256K 0 0 Q 512kb 0 2 1M 0 0 , ODDOQOb 3 Wkf~z5Z'33"Oi: SOLUTIONS 80386SX MOTHER BOARD DRAM INSTALLATION v 1) SOLUTIONS 386SX MOTHERBOARD
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88C215 80387SX ibm at motherboard 80286 80286 pin configuration 511000 dram 88c211 SYSL06IC 145M0 88C286 88C211 88C2Q6

41256 dram

Abstract: 4164 64k dram 6 K DRAM) - 0.2 seconds (SEL=V D D /open, 64K D R A M ) 25kH z sam p lin g rate Continuous variab le , , on-chip oscillator, DRAM interface, 10-bit A/D and D/A converters a s well a s control logic. It provides , e d w ith a n e x t e r n a l D R A M (41256/4164). The H T8955A is superior to a conventional B B D , Osc. - Ó O S C 4 DRAM SEL D/A Converter Shift Register 4- -Ó S E L - O DATA ouT O *- , sign al in pu t pin (inverted) Pre-am plifier output pin D elayed audio sign al output pin DRAM type
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8955A M41256

dram 4164

Abstract: ADVANCE MICRON 8 MEG X MT16D832 32, 16 MEG x 16 DRAM MODULE PAM MODULE FEATURES , width 8 MEG x 32,16 MEG x16 FAST-PAGE-MODE PIN ASSIGNMENT (Top View) 72-Pin SIMM (DE-16) DRAM , X MT16D832 16 DRAM M ODULE RAS cycle (READ, W RITE) or RAS REFRESH cycle (RASONLY, CBR or , bank select for the x l6 memory organization. FUNCTIONAL BLOCK DIAGRAM DRAM MODULE MT16D832 REV , x 16 DRAM M ODULE MT16D832 TRUTH TABLE ADDRESSES FUNCTION Standby READ EARLY-WRITE
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MT16D832M/G T16D832 MT160632 A0-A11
Abstract: . 4.16.4 DRAM Relationships , ) . 4.10 DRAM Control Register 4/5 (DMCR4/5 , ) . 4.14 DRAM Signal Control Register (DSCR , . 4.17.8 Usual DRAM Interface: Read . 4.17.9 Usual DRAM Interface: Write Fujitsu
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CM71-10106-1E MB91F109

4164 dram

Abstract: FR30 . 4.16.4 DRAM Relationships , ) . 4.10 DRAM Control Register 4/5 (DMCR4/5 , ) . 4.14 DRAM Signal Control Register (DSCR , . 4.17.8 Usual DRAM Interface: Read . 4.17.9 Usual DRAM Interface: Write
Fujitsu
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FR30 LQFP-100 QFP-100

DOT MATRIX PRINTER SERVICE MANUAL

Abstract: sc1236 SEK Euro Description IBM 4400 Thermal Printer Serial&Parallel port, 8MB DRAM & 4MB Flash, ASCII , Memory Option *), 8MB DRAM and 6MB Flash 7 218 6 313 12 671 0 1 771 *) For a total of 16MB DRAM and 10MB Flash (prereq. for IPDS) Media and output handling options 4400 4400 4400 , /Twinax Attachment IPDS for Twinax or Ethernet NIC Memory Option, 8MB DRAM and 6MB Flash Bar Code , 459 3 712 4247 4247 4247 4247 4247 4247 4164 7803 4165 4121 4124 7703 Attachment
IBM
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69G7336 69G7343 DOT MATRIX PRINTER SERVICE MANUAL sc1236 SC-1236 4247-A00 IBM 6400 IBM 4230 14J1460 14J1458 14J1459 69G7325 69G7326 69G7327
Abstract: ADVANCE |U |IC Z R O N 8 MEG DRAM MODULE X MT16D832 32, 16 MEG x 16 DRAM MODULE , ,388,608 words organized in a x32 configuration. The MT16D832 and MT16D832B are the sam e DRAM m , MEG X MT16D832 16 DRAM MODULE For x l6 applications, the corresponding DQ and CAS pins must , x 16 DRAM MODULE TRUTH TABLE ADDRESSES DATA-IN/OUT MS ÃÃ"5T WE *R 'C , MEG ABSOLUTE MAXIMUM RATINGS* X MT16D832 32, 16 MEG x 16 DRAM MODULE â'™ Stresses greater -
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MT160832
Abstract: X MT16D832 32, 16 MEG x 16 DRAM MODULE 8 MEG DRAM MODULE X 32,16 MEG x16 , are the same DRAM module versions except that the MT16D832B has a 4,096-cycle refresh instead of a 2 , refresh counter for automatic RAS addressing. X MT16D832 3 2 ,1 6 MEG x 16 DRAM MODULE For x l6 , 8 MEG X 32, 16 MEG X MT16D832 16 DRAM MODULE TRUTH TABLE DATA-IN/OUT ADDRESSES , specifications without notice. 91993, Micron Semiconductor, Inc. DRAM MODULE L FAST-PAGE-MODE MI CR -
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MT16D832BG-6

4164 64k dram

Abstract: S41128B characteristics of the TM S 4164 NMOS dynamic RAM. A logic low on the RAS1 input selects the low er DRAM; a logic low on the RAS2 input selects the upper DRAM. The T M S 41128B-15 features a RAS access time of 150 ns , A lt 7 9 DA7 vddC 8 t RAS1 (pin 3) selects th e lo w er DRAM, and pin 3 on the upper DRAM is a no connect. RAS2 (pin 4) selects the upper DRAM, and pin 4 on th e low er DRAM is a no connect. PIN , (either RAS1 or RAS2) must be applied to select either the low er DRAM or the upper DRAM. When a RAS-only
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S41128B tms4164 Z41H 072-BIT 16-PIN

U15-U10

Abstract: MT18D236 |V /|ICZRO N MT9D136, MT18D236 1 MEG. 2 MEG x 36 DRAM MODULE DRAM MODULE FEATURES · C o m m , MODE PIN ASSIGNMENT (Front View) 72-Pin SIMM (DD-9) 1 Meg x 36, (DD-10) 2 Meg x 36 N E W DRAM , Technology, Irte. |V |IC =RO N MT9D136, MT18D236 1 MEG, 2 MEG x 36 DRAM MODULE REFRESH _ R A , in ed in its co rrect state b y m a in ta in in g p o w er and exe cu tin g an y N E W DRAM SIMM , MT4C4001JDJ U5 = MT4C4004JDJ NOTE: Due to the use of a Quad CAS parity DRAM, RASO is common to all DRAMs
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U15-U10 MT9D13S MT1BD236

VL82C205A-16QC

Abstract: VL82c205 page mode DRAM accesses for PC/ATcompatible systems · Speed upgrades to 20 MHz · Companion to VL82CPCAT , ) · Less than 0.6 wait state average DRAM performance · Low power CMOS technology · 68-pin PLCC , the DRAM control signals. Status 0 - This input is used along with -S1 and M /-IO to determine which , which bank of DRAM should be aocessed. CAS Enable Input for Bank 1 - This input is used along with CASO, RASO, and RAS1 to determine which bank of DRAM should be aocessed. FtAS Enable Input for Bank 0 - This
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VL82C205A-16QC VL82c205 vl82c205a16qc VL82C2 VL82C205A VL82CPCAT-16 VL82CPCAT-20 VL82C205 VLS2C205A
Abstract: 1 MEG x 40, 2 MEG x 20 IC DRAM CARD MICRON B S5E D ltCHNOl.OCiV INC IC DRAM CARD 4 , The MT12D88C140 is a 4 megabyte, IC DRAM card organized primarily as a 1 Meg x 40 bit memory array , ) cycle refresh; a very low current, data retention mode. Standard compo­ nent DRAM refresh modes are , Technology, Inc. I D A CARD C RM â'¢ JEIDA, JEDEC and PCMCIA standard 88-pin IC DRAM card â'¢ Polarized receptacle connector â'¢ Industry standard DRAM functions and timing â'¢ High-performance, CMOS -
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41256 dram

Abstract: 41256 MEMORY select pin to choose between 4164 or 41256 DRAM connection. It is pulled high so for a 64K system, it may , controlled by the user's needs. All the necessary control logic needed to drive a DRAM are included so that direct read and write are possible without a DRAM controller. 41256 or 411024 DRAMs can be used with , speech. Pin names are compatible with DRAM pin names, so a direct name match is the only require ment
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MX8012 41256 MEMORY 41256 ram mx8003 Continuously Variable Slope Delta Modulator 0QQQ177 MX8003M

WTS 1.7 IC 28 PIN

Abstract: M IC R O N 1 MT12D88C140 1 MEG x 40. 2 MEG x 20 IC DRAM CA R D IC DRAM CARD FEATURES · JEIDA, JEDEC and PCMCIA standard 88-pin IC DRAM card · Polarized receptacle connector · Industry standard DRAM functions and tim ing · H igh-perform ance, CMOS silicon-gate process · All outp u ts are , 4 m egabyte, IC DRAM card organized prim arily as a 1 Meg x 40 bit m em ory array for EDC , (BBU) cycle refresh; a very low current, data retention m ode. S tandard com po nent DRAM refresh m
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WTS 1.7 IC 28 PIN MT12O80C14O
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