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SN74LS295BN Texas Instruments 4-Bit Right-Shift Left-Shift Registers 14-PDIP 0 to 70 visit Texas Instruments
SN54LS295BJ Texas Instruments 4-Bit Right-Shift Left-Shift Registers With 3-State Outputs 14-CDIP -55 to 125 visit Texas Instruments
TPIC6596DWG4 Texas Instruments 8-Bit Shift Register 20-SOIC visit Texas Instruments
TPIC6B595DWG4 Texas Instruments 8-Bit Shift Register 20-SOIC visit Texas Instruments Buy
TPIC6596DWRG4 Texas Instruments 8-Bit Shift Register 20-SOIC visit Texas Instruments
TPIC6B595DWRG4 Texas Instruments 8-Bit Shift Register 20-SOIC visit Texas Instruments

4 bit left shift circuit for dsp

Catalog Datasheet MFG & Type PDF Document Tags

TMS320C25

Abstract: 74HC163 ) B TIMER NEXTSCLK ZA LS >0 STORE Dout WORD IN ACC SFL SHIFT ACC LEFT 1 BIT SACL STORE ACC IN >200 B TXRX GO TO TXRX ROUTINE END Figure 5. TMS320C25 Code for Circuit 1 MSB LSB 8 7 6 5 4 3 2 1 0 filledwithOs >200 D0ut from LTC1090 stored in TMS320C25 RAM Figure 4. Memory Map for Circuit 1 , the two circuits. For circuit 1 the XF bit is first initialized to 0. The TC bit is set (TC is used as , REPEAT 5 TIMES SFR SHIFT ACC RIGHT 1 BIT SACL *,0 STORE ACC IN >200 RPTK 127 DELAY NOP 22/iS FOR
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74HC163 74HC04 T016 4 bit left shift circuit for dsp AN26M-3

hc-sr

Abstract: DSP56011 -Host Command bit (HC) 4-30 D Data ALU 1-11 Data Buses 1-12 data transfer DMA 4-59 DSP to host 4-19 , DMA mode 4-26 DMA procedure DSP to host 4-65 host to DSP 4-62 DMA Status bit (DMA) 4-18, 4-32 DSP , Receive Interrupt Enable (HRIE) bit 4-15 HI registers after reset as seen by DSP 4-19 HI Registers , host to DSP internal processing 4-61 Host Transmit Data Empty bit (HTDE) 4-16 Host Transmit Data , , 4-53 HV5­HV0 bits 4-29 I I2C 1-18, 5-3, 5-20 Bit Transfer 5-20 Bus Protocol For Host Read Cycle
Freescale Semiconductor
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DSP56011 hc-sr IEC958 CP-340

AN26N

Abstract: TMS320C25 zero which sets up the serial port to operate in the 16-bit mode. For circuit 1 the XF bit is first , . For circuit 1 the XF bit is set which causes the FSX pin to generate a CS signal which is fed into the , . TMS320C25 Code for Circuit 2 Figure 7. Timing for Circuit 2 Shows 32/ts Throughput Rate AN26N-4 /yuvm , LTC1091 10-bit data acquisition system and the TMS320C25 digital signal processor (DSP). In particular two , . Circuit 1: Minimum Hardware Interface Figure 2. Timing for Circuit 1 Shows 39/tS Throughput Rate
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LTC1092 AN26N TMS320C25 schematic LCT1091 LTC1091/92 AN26N-3 AN26N-4

logic diagram to setup adder and subtractor

Abstract: 1818D , or two LABs and one DSP block to the right or left of a source LAB. These resources are used for , shift registers for DSP applications such as pseudo-random number generators, multichannel filtering , TriMatrix Memory RAM block and 4,608 bits for the M4K RAM block. The total number of shift register , DSP blocks from the left and right can also drive an LAB's local interconnect through the direct link , interconnect from left LAB, TriMatrix memory block, DSP block, or IOE output Direct link interconnect from
Altera
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logic diagram to setup adder and subtractor 1818D CLK12 SGX51004-1

SONY APS 279 power supply

Abstract: SONY APS 279 A Cirrus Logic Company MPEG Audio Decoder System Features · · DSP Optimized for Audio Decode, 24-bit Fixed Point w/48-bit Accumulator On-Chip Functional Blocks Include: - DSP with RAM and ROM Memories - , Consumption VA+ VD+ Note: 1. 10 k£2, 100pF load for each analog signal (Left, Right). 30 kft, 100pF load for , DSP has a 24-bit fixed point data path, 5K words of program RAM, and 3K words of data RAM. The , from memory and store results back to memory. Modulo and bit reverse addressing are supported. For a
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SONY APS 279 power supply SONY APS 279 CNT16 CS4922 CS4920A CS4922-CL CDB4922 DS227PP1

verilog code for crossbar switch

Abstract: LUT-based-64 implement shift registers for FIR filter applications, and the Stratix III DSP blocks support rounding and , performance Support for high-speed networking and communications bus standards including SPI-4.2, SFI-4 , FPGA with support for 256-bit (AES) volatile and non-volatile security key to protect designs Robust , signal processing (DSP) blocks optimized for DSP applications requiring high data throughput. Stratix , optimized, fully pipelined multiplication operations Native support for 9-bit, 12-bit, 18-bit, 36-bit word
Altera
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verilog code for crossbar switch LUT-based-64 add round key for aes algorithm verilog code for twiddle factor ROM C6316 fpga frame by vhdl examples SIII51001-1

logic diagram to setup adder and subtractor

Abstract: DIN 5463 efficiently implement shift registers for FIR filter applications, and the Stratix III DSP blocks support , high-density, high-performance FPGA with support for 256-bit AES volatile and non-volatile security key to , , PLL_R1_CLKp, and PLL_R1_CLKn) that can be used for data inputs. (4) The EP3SL340 FPGA is offered only in the , : 320-bit MLAB blocks optimized to implement filter delay lines, small FIFO buffers, and shift , digital signal processing (DSP) blocks optimized for DSP applications requiring high data throughput
Altera
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DIN 5463 EP3SE50 circuit diagram of inverting adder H.264 encoder vhdl code for complex multiplication and addition VHDL codes of 16 point FFT radix-4

TMS1000

Abstract: Effio 1 SET AS INPUT CLR PU SCLK GOES LOW SETB Pi .4 CS GOES HIGH MOV A. #0DH DiN WORD FOR LTC1090 CLR P1.4 CS GOES LOW MOV R4. #Q8H LOAD COUNTER NOP DELAY FOR DEGLITCHER MOV C, P1.1 READ DATA BIT , don't don't Ignore Start S/D O/S MSBF care care care Figure 3. 4-Bit D)N Word for LTC1091 in $50 MSB , hardware and software required for communication between the LTC1090 10-bit data acquisition system and the , 1 MOV P1.I02H BIT 1 PORT 1 SET AS INPUT CLR P1.3 SCLK GOES LOW SETB Pi .4 CS GOES HIGH MOV A, Â
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MCS-51 TMS1000 Effio TMS7000 M063 AN26D-2 EPROM 27256 programmer schematic LTC1094 FA80005F FF800024 AN26R-3

19SPI

Abstract: 12CLKOUT for a variety of applications. This device integrates a 24-bit DSP with on-chip program and data RAM , . A diagram of the CLKOUT circuit is shown in Figure 12. The value of Q (10 bit) is set by the DSP , SCP output register by the DSP between the rising edge of SCK/SCL for the D1 data bit, but before , the shift register on the falling edge of SCK/SCL for the D0 bit. A new read transaction is required , CS4912 Multi-Function Digital Audio Processor Features Description l 24-bit DSP with
Cirrus Logic
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CS5331 CS4222 CS4912-CL 19SPI 12CLKOUT either128fs car audio crossover CRD4912-01 DS282PP2 MS-018

modified harvard architecture

Abstract: 3955K Bit-Field for Zeros TST1 Test Bit-Field for Ones TSTB Test Specific Bit SHFC Shift Accumulators , (DSP) core designed for middle to high-end telecommunications applications and consumer electronics , , digital video, DSP, and others. LSI Logic provides a complete framework for device and system development , Arithmetic Unit Six 16-bit data pointers for X and Y data memory with additional three alternative , Instruction n+1. Instruction Set Summary Table 1 summarizes the instruction set for the Oak DSP Core
LSI Logic
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CWDSP1640 modified harvard architecture 3955K oak dsp CW4001

circuit using 74hc574

Abstract: 16 bit processor schematic and the software for this circuit is available from the ?. 18-bit Input Shift Register 18 , circuit is active low for AT&T DSP processors, the circuit must be modified for use with DSP processors , out to the DSP processor IC, synchronous to the bit transfer clock. As the serial data is clocked out to the DSP processor IC, serial data inputted to TAG is clocked into the output shift register , the DSP processor software modified to recognize an N-1 channel ID. However, for systems using
Burr-Brown
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DSP101 DSP102 HI-508A 74HC221 OPA627 74HC166 circuit using 74hc574 16 bit processor schematic 74hc574 DEM-DSP102 74HC574

i2c to AES-EBU converter

Abstract: CS4920A-CL : Left/Right bit of DAC. Special test bit intended for test purposes only. DS189PP2 CS4920A , . 13 3 Transmitter Sequencing . 15 4 Clock Manager Register Bit Map , . 47 32 DAC Passband Ripple . 47 1 2 3 4 Ratios for 64Fs based , ) Notes: 1. 10 k, 100pF load for each analog signal (Left, Right, Mono). D/A INTERPOLATION FILTER , initialize and for the on-board PLL to stablize. 4. The mode of the Serial Control Port is selected by CS
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CS4920 i2c to AES-EBU converter CS4920A-CL schematic diagram tv sony digital tv CS4921 SIGNETICS PLL AN50REV3 CS4920/20A/21

AK7712AVT

Abstract: AK7712 operation 24-bit arithmetic logic operation ·Shift: 1-,2-,3-,4-,6-,8-,15-bit right/left shift AK7712A , ] 2) Multiplier Multiplier outputs the 31-bit data for shift circuit as a result of fixed-point calculation(24-bit(data) × 16-bit(coefficient) = 40-bit). 4 ways of multiplication can operate for the data , .) ·Register: 34-bit × 4(ACC) [for ALU] 24-bit × 8(TMP) [for DBUS connection] ·Double precision operation , . The shift commands which shift the data 0/1/2/3/4/6/8/15 bits to right/left, and the indirect shift
Asahi Kasei Microsystems
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AK7712A-VT AK7712AVT AK7712 BHR4 1000H AKD7712A

sun flower

Abstract: matsua dsp 16-bit still pictures. Pa cka g e O utline Unit: mm ^ Features · A 16-bit, fixed-point DSP capable of , discrete cosine transform (DCT) circuit, which is necessary for international standards for video coding , memory memory memory read read read read read read read read (left shift) - (right shift) memory write (left shift) - ALU - (right shift) memory write (left shift) - multiplication - (right shift) memory write (left shift) - FDCT/IDCT - (right shift) memory write (left shift) - FLT - (right shift) memory
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sun flower matsua dsp 16-bit 251381 N195901 392-47S9 CA9S03S AA73317

phillips 031 ko Capacitor

Abstract: EEFL into the shift register on the falling edge of the FS status bit and the left channel is loaded on the , disabled. DACLRB: Left/Right bit of DAC. Special test bit intended for test purposes only. 20 â , Purpose Digital Signal Processor Optimized for Audio 24 Bit Fixed Point 48 Bit Accumulator 12.3 MIPS @ , .13 Figure 3 Transmitter Sequencing.15 Figure 4 Clock Manager Register Bit Map , .27 Figure 17 User Definable Pins Register Bit Map.29 Figure 18 DSP Architecture
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phillips 031 ko Capacitor EEFL mpeg 1 layer 1 33-bit-counter 2sb 324 LM 13500

prologic II 5.1 circuit diagram

Abstract: ym34 circuit for generating clock for operation. n Internal operating frequency of 512 fs. n Allows fading in , (Enabled when CTLSEL = 0) Reset signal input Bit shift selection (Enabled when CTLSEL = 0) Bit shift , 2 DA ROUT AIROUT AIRRET Rch Bit Shift COEF 2 Fader SYNCN Rch COEF 1 Rch , , refer to the format diagram shown in the next page. 3-3) Bit shift BSFT1, BSFT0 and CTLSEL This function is used to specify the amount of bit shift after the addition of the results of filtering. CTLSEL
Yamaha
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prologic II 5.1 circuit diagram ym34 Digital Sound Processor circuit diagram Yamaha 20 YM3433 yss205 YSS91 YSS901 YM3433B-D/F 16DIP 24SOP YM3437C-D/F

SONY APS 252 power supply

Abstract: SONY APS 252 memory. Modulo and bit re verse addressing are supported. For a sample rate of 48 kHz, the DSP can , shift register on the falling edge of the FS status bit and the left channel is loaded on the rising , . Normal data transmission is disabled. DACLRfi: Left/Right bit of DAC. Special test bit intended for test , Digital Signal Processor Optimized for Audio 24 Bit Fixed Point 48 Bit Accumulator 12.3 M IP S @ 48 kHz , . 15 Figure 4 Clock Manager Register Bit Map . 16 Figure 5 DAC
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SONY APS 252 power supply SONY APS 252 APS 252 sony power DS189
Abstract: output register by the DSP between the rising edge of SCK/SCL for the DO bit, but before the rising , into the serial shift register on the falling edge of SCK/SCL for the DO bit. The bus master should , CS4912 Multi-Function Digital Audio Processor Features Description â'¢ 24-bit DSP with , a 24-bit DSP with on-chip program and data RAM, a stereo DAC, a full-duplex serial audio inter , external logic. The CS4912 is configured for specific applications by DSP code loaded into the on-chip -
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CRD4912

2808990

Abstract: hearing aid microphone using amplifier Shift = 5 See Note B NOTE B: For 5-bit left shift, digital word is limited to 15 bits with , circuit. The AIC111 is part of a comprehensive family of DSP/µC based highperformance analog interface , Gain (linear), R = 20.4 k for A 4 or 20.4 k × (4/A) for A , DO 5-MHz output clock for external DSP/µC 19 DVSS1 GND Ground return for digital , DO Digital interface serial shift clock 27 DVSS2 GND Ground return for digital
Texas Instruments
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2808990 hearing aid microphone using amplifier hearing aid chip circuit diagram of hearing aid using transistors JEDS78 MSP430F12x SLAS382 TMS320VC54 TMS320VC55 MSP430

2808990

Abstract: 20.000 G Shift = 5 See Note B NOTE B: For 5-bit left shift, digital word is limited to 15 bits with , circuit. The AIC111 is part of a comprehensive family of DSP/µC based highperformance analog interface , Gain (linear), R = 20.4 k for A 4 or 20.4 k × (4/A) for A , DO 5-MHz output clock for external DSP/µC 19 DVSS1 GND Ground return for digital , DO Digital interface serial shift clock 27 DVSS2 GND Ground return for digital
Texas Instruments
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20.000 G DSP hearing aid circuit diagram of hearing aid circuit diagram of digital hearing aid ic for hearing aid compressor ic
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