NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 32-bits per pixel, however once the polygon' pixels are shaded and textured they are written to the framebuffer. If the s framebuffer is 16-bit, the pixel data is truncated from 32-bits to 16-bits with a , and Shade 32-bits colour value 32-bits colour value 32-bits colour value BLEND 32-bits result CLAMP Frame buffer colour (16-bits) BLEND 32-bits result CLAMP Frame buffer colour (16-bits) BLEND 32-bits result CLAMP Final frame buffer colour (16- bits) This results in visual ... | Original |
7 pages, |
framebuffer kyro PowerVR datasheet abstract |
| Abstract: CLOCK generator HCLK DCLK MCLK PCICLK ISACLK x86 CORE PMU HCLK PCICLK HCLK 32bits , 24bits Video Pipeline 2D Accelerator IDE I/F 32bits PCI Controller DCLK SDRAM I/F ... | Original |
6 pages, |
Video cvbs 656 RGB input CVBS output MiniDIN 6 video datasheet abstract |
| Abstract: HCLK DCLK GCLK PCICLK ISACLK x86 CORE PMU HCLK PCICLK HCLK 32bits HCLK GCLK , Accelerator IDE I/F 32bits PCI Controller CRT & VGA Controller DRAM I/F EIDE Controller ... | Original |
7 pages, |
Video cvbs 656 scart vga TV MICROPROCESSORS RGB input CVBS output datasheet abstract |
| Abstract: HCLK DCLK GCLK PCICLK ISACLK x86 CORE PMU HCLK PCICLK HCLK 32bits HCLK GCLK , I/F 32bits PCI Controller CRT & VGA Controller DRAM I/F EIDE Controller RAMDAC ... | Original |
7 pages, |
STPC CCIR601 datasheet abstract |
| Abstract: PCICLK ISACLK x86 CORE PMU HCLK PCICLK HCLK 32bits PCICLK PCI I/F ISACLK PCICLK , Accelerator IDE I/F 32bits PCI Controller DCLK SDRAM I/F EIDE Controller DCLK VIDEO ... | Original |
6 pages, |
RGB input CVBS output datasheet abstract |
| Abstract: 3 Table Of Contents Case for 32-bits 256Mb (8Mx32 , Electronics Co; LTD 4 1 Case for 32-bits 256Mb (8Mx32) According to the density variation of memory , register configuration values of 32-bits, 256Mb (8Mx32) will be shown below. Assume that CAS Latency is 2 , 10 1600 64Mx8 DDP(1CS) 13 11 1800 64Mb 32bits 2Mx32 Mono 11 8 5300 , 10 5880 The value for 32-bits 512Mb (8Mx32, Mono) is not defined in Table 2.1 because it didn't ... | Original |
9 pages, |
Samsung 6400 PL340 4C00 C800 C400 4mx32 810400 831000 20C200 PL172 8Mx32 PL172 abstract |
| Abstract: A95AD-A-000 A95AD-A-000 Preliminary Universal Communicator Embedded Computer for RFID reader Feature 32-bits RISC processor with XScale technology 32MB of Flash memory 128MB 128MB of SDRAM 10/100 Fast Ethernet 1 RS232 RS232 console port 1 RS232 RS232 communication port 1 RS485 RS485 communication AMIC's A95AD-A-000 A95AD-A-000 embedded port computer is a high performance and Embedded Linux cost effective platform for , Specification CPU 32-bits RISC Processor Flash 32 MB RAM 128 MB System Interface RS232 RS232 ... | Original |
2 pages, |
RS485 to Ethernet Converter A95AD-A-000 A95A "embedded systems" ethernet protocol RFID RS232 communication port RFID protocol communication A95AD-A-000 abstract |
| Abstract: A9235-A-001-NET A9235-A-001-NET 900MHz UHF RFID Reader / Writer Feature 32-bits RISC processor with XScale technology 32MB of Flash memory 128MB 128MB of SDRAM 10/100 Fast Ethernet 1 RS232 RS232 console port Embedded Linux operating system Fan-less design Build-in RTC Supports standard TCP/IP protocol stacks AMIC's A9235-A-001-NET A9235-A-001-NET is a high Supports multi-thread performance and cost effective UHF environment RFID , A9235-A-001-NET A9235-A-001-NET 900MHz UHF RFID Reader / Writer System Specification CPU 32-bits RISC Processor Flash ... | Original |
2 pages, |
900Mhz RFID UHF rfid antenna EPC Gen2 class1 UHF rfid circuit 900mhz circuit diagram of RFID UHF rfid circuit ISO18000-6B EPC gen2 UHF RFID READER rfid circuit diagram A9235-A-001-NET A9235-A-001-NET abstract |
| Abstract: /F Keyboard ISACLK DEVCLK HCLK Mouse Peripherals Serial 2 32bits Parallel , 64bits ! Video Pipeline PCI I/F PCICLK CRT & VGA Controller ISA I/F 32bits PCI ... | Original |
7 pages, |
embedded microprocessors datasheet abstract |
| Abstract: TLB exception vectors. Specifically, virtual addresses whose upper 32-bits are not equal to all "0" , instruction set) are invalid. This prevents software from generating pointer values larger than 32-bits. - , 32-bits; addresses or pointers are 32-bits; and the type "long long" specifies a 64-bit datum. - , remain 32-bits. - mint64. This switch makes all variables of type "int", "long", and "long long" to be ... | Original |
2 pages, |
R3000 IDT79R4600 79R4600 64 bit microprocessor "64-Bit Microprocessor" MIPS 32-bit bus architecture 32-bit microprocessor architecture 64-BIT IDT79R4600TM TN-21 64-BIT abstract |
| Abstract: H8300H APPLICATION NOTE H8/300H H8/300H Tiny Series Unsigned 64-Bit Binary Division Introduction The software DIVIDE64 DIVIDE64 carries out division in this format: Dividend (unsigned, 64 bits)/divisor (unsigned, 32 bits) = quotient (unsigned, 32 bits) . remainder (unsigned, 32 bits). Division by 0 sets the Z flag. Target Device H8/300H H8/300H Tiny Series Contents 1. Functions. ... | Original |
9 pages, |
H8/300H H8/300H abstract |
| Abstract: APPLICATION NOTE SH7000 SH7000 Series 64 Bit + 64 Bit = 64 Bit (Unsigned) Label: ADDU64 ADDU64 Functions Used: ADDC Instruction Contents 1. Function . 2 2. Arguments. 2 3. Internal Register Changes and Flag Changes. 3 4. Programming Specifications ... | Original |
8 pages, |
SH7000 313E 302E ADDU64 SH7000 abstract |
| Abstract: APPLICATION NOTE SH7000 SH7000 Series 64 Bit + 64 Bit = 64 Bit (Signed) Label: ADDS64 ADDS64 Functions Used: ADDV Instruction Contents 1. Function . 2 2. Arguments. 2 3. Internal Register Changes and Flag Changes. 3 4. Programming Specifications . ... | Original |
10 pages, |
SH7000 313E 304F 302F ADDS64 SH7000 abstract |
| Abstract: upper 32-bits of the minuend (unsigned, 64 bits) as an input argument. The upper 32 bits of the difference (unsigned, 64 bits) are also set here as an output argument. ER1: Set the lower 32-bits of the , ) are also set here as an output argument. ER2: Set the upper 32-bits of the subtrahend (unsigned, 64 bits) as an input argument. ER3: Set the lower 32-bits of the subtrahend (unsigned, 64 bits) as an ... | Original |
10 pages, |
1E20 datasheet abstract |
| Abstract: upper 32-bits of the minuend (unsigned, 64 bits) as an input argument. The upper 32 bits of the difference (unsigned, 64 bits) are also set here as an output argument. ER1: Set the lower 32-bits of the , ) are also set here as an output argument. ER2: Set the upper 32-bits of the subtrahend (unsigned, 64 bits) as an input argument. ER3: Set the lower 32-bits of the subtrahend (unsigned, 64 bits) as an ... | Original |
9 pages, |
1E20 H8/300H H8/300H abstract |
| Abstract: To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and ... | Original |
10 pages, |
datasheet abstract |
| Abstract: APPLICATION NOTE H8/300H H8/300H Tiny Series 64-Bit Binary Addition (ADD) Introduction Performs binary addition in this format: augend (unsigned, 64 bits) + addend (unsigned, 64 bits) = sum (unsigned, 64 bits). Target Device H8/300H H8/300H Tiny Series Contents 1. Arguments. 2 2. Changes to Internal Registers and Flags . ... | Original |
9 pages, |
H8/300H H8/300H abstract |
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