NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| LM324NS | Texas Instruments | IC QUAD OP-AMP, 9000 uV OFFSET-MAX, 1.2 MHz BAND WIDTH, PDSO14, Operational Amplifier | 
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| LM324NSR | Texas Instruments | Quadruple Operational Amplifier 14-SO 0 to 70 |
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| SG3524NS | Texas Instruments | Regulating Pulse-Width Modulators 16-SO 0 to 70 |
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| SG3524NSE4 | Texas Instruments | IC 0.1 A SWITCHING CONTROLLER, 450 kHz SWITCHING FREQ-MAX, PDSO16, GREEN, PLASTIC, SOP-16, Switching Regulator or Controller |
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| LM324NSRG4 | Texas Instruments | Quadruple Operational Amplifier 14-SO 0 to 70 |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: PLESSEY W Semiconductors, SP9680 SP9680 ULTRA FAST COMPARATOR The SP9680 SP9680 is an ultra fast comparator manufactured using a high performance bipolar process which makes possible very short propagation delays (2.4ns typ.). The circuit has differential inputs and complementary ECL outputs, capable of driving 50 D lines. The device is manufactured in a low cost mini-dip package and is intended as an alternative to , FEATURES â- Propagation Delay 2.4ns Typ. â- Complementary ECL Outputs â- 50 Q Line Driving Capability â- ... | OCR Scan |
1 pages, |
SP9680MP SP9680DP SP9680 552V SP9685 SP9680 abstract |
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| Abstract: AverLogic Video FIFO Selection Guide FIFO Usage Frame Buffer Bus Width 8-bit 8-bit AL460A-PBF AL460A-PBF Density 128M AL440B-12-PBF AL440B-12-PBF & AL440B-24-PBF AL440B-24-PBF 4M 3M Max. Speed Key Features Width Expansion AL422B-PBF AL422B-PBF 50Mhz 80Mhz/ 40Mhz 150Mhz 20ns 12ns/ 24ns 6ns Input Enable Output Enable 16-bit Window Mode Access Polarity Select Double buffering Power Supply 3.3V or 5V 3.3V 2.5 & 3.3V 5V input tolerant ... | Original |
1 pages, |
AL460A AL460A-PBF 50mhz FIFO al422b AL440B AL440B-24-PBF al440 40mhz buffering AL440B-12-PBF AL422B-PBF 28-SOP AL422B-PBF abstract |
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| Abstract: AverLogic Video FIFO Selection Guide FIFO Usage Frame Buffer Bus Width 8-bit 8-bit AL460A-7-PBF/ AL460A-7-PBF/ AL460A-13-PBF AL460A-13-PBF Density 128M AL440B-12-PBF/ AL440B-12-PBF/ AL440B-24-PBF AL440B-24-PBF 4M 3M Max. Speed Key Features Width Expansion AL422B-PBF AL422B-PBF 50Mhz 80Mhz/ 40Mhz 150Mhz/ 75Mhz 20ns 12ns/ 24ns 6ns Input Enable Output Enable 16-bit Window Mode Access Polarity Select Double buffering Power Supply 3.3V or 5V 3.3V 2.5 & 3.3V 5V input ... | Original |
1 pages, |
80MHz 5V buffering AL440B-24-PBF al422b FIFO AL460A-13-PBF AL460A-7-PBF AL460A AL460A-7 AL422B-PBF AL440B-12-PBF 28-SOP AL460A-7-PBF/ AL440B-12-PBF/ AL422B-PBF abstract |
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| Abstract: /7.8 24ns/28ns into 1000pF 42ns into 1,000pF 4.5V to 18V SOT-143 IttyBitty® Device. MIC4417 MIC4417 Low-Side Driver Single Inverting 1.2A 7.6/7.8 24ns/28ns into 1000pF 37ns into 1 , MIC4421 MIC4421 MIC4421A MIC4421A(2) Low-Side Driver Single Inverting 9A 0.8/0.6 0.8/0.6 20ns/24ns into 10nF 20ns/24ns into 10nF 15ns/35ns into 10nF 15ns/35ns into 10nF 4.5V to 18V PDIP-8, SOIC-8 , 20ns/24ns into 10nF 20ns/24ns into 10nF 15ns/35ns into 10nF 15ns/35ns into 10nF 4.5V to 18V ... | Original |
2 pages, |
MIC4102 MIC4101 MIC4100 high speed mosfet driver hex latch MIC4424 MIC4425 MIC4426 Peak Low-Side MOSFET Driver p-channel mosfet driver MIC4452A MOSFET DRIVER circuits MIC4429 mosfet driver MIC4100 abstract |
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| Abstract: PLESSEY W Semiconductors, SP9680 SP9680 ULTRA FAST COMPARATOR The SP9680 SP9680 is an ultra fast comparator manufactured using a high performance bipolar process which makes possible very short propagation delays (2.4ns typ.). The circuit has differential inputs and complementary ECL outputs, capable of driving 50 D lines. The device is manufactured in a low cost mini-dip package and is intended as an alternative to , FEATURES â- Propagation Delay 2.4ns Typ. â- Complementary ECL Outputs â- 50 Q Line Driving Capability â- ... | OCR Scan |
2 pages, |
SP9680MP SP9680DP SP9680 sp9685 SP9685 SP9680 abstract |
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| Abstract: CLK1 CLK2 0 12 24 12ns MULTICYCLE=2 HOLD_MULTICYCLE=2 30 clk2 tSU 24ns tH 12ns 12ns 24ns 12ns 24ns 31 12ns MULTICYCLE=2 HOLD_MULTICYCLE=1 26 Altera , 12ns tSU tH 0ns 24ns clk2 clk1 2ns 32 Period = 12nsoffset = 2ns Altera ... | Original |
36 pages, |
datasheet abstract |
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| Abstract: (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 Minimum RAS to CAS delay (=tRCD) 24ns 18h 30 Minimum activate precharge time (=tRAS) 50ns , latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 Minimum RAS to CAS delay (=tRCD) 24ns , time (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 ... | Original |
9 pages, |
M466S1724BT2-L10 M466S1723BT3-L10 M466S1723BT2-L10 M466S0924BT0-L10 K4S281632B-TL10 K4S280832B-TL10 datasheet abstract |
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| Abstract: (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 Minimum RAS to CAS delay (=tRCD) 24ns 18h 30 Minimum activate precharge time (=tRAS) 50ns , time (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 Minimum RAS to CAS delay (=tRCD) 24ns 18h 30 Minimum activate precharge time (=tRAS) 50ns , time (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 ... | Original |
9 pages, |
M466S1724MT2-L10 M466S1723MT3-L10 M466S1723MT2-L10 M466S0924MT0-L10 K4S281632M-TL10 datasheet abstract |
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| Abstract: 24ns after C4 falling edge. Maximum LOUT peak-to-peak voltage is slightly reduced (by 0.2V p-p) in , within a timing window beginning 17ns before, and extending to 24ns after, the C4 clock falling edge. ... | Original |
2 pages, |
MT8972B MT8972A MSAS-59 MSAS-59 abstract |
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| Abstract: 3010 data 3 delay devices, inc. VOLTAGE-VARIABLE DELAY LINE TR < 1ns (SERIES 3010) FEATURES · · · · · · · PACKAGE Varactor Technology Fast rise time for high frequency applications Delay continuously adjustable from 2.4ns to 3.4ns Very narrow device (SIP package) Stackable for PC board economy Epoxy encapsulated Meets or exceeds MIL-D-23859C MIL-D-23859C 3010 1 3 IN 6 , ) to -11.3V (min TD) Range of delay variation: 1.0ns minimum Minimum delay: 2.4ns ± 0.25ns ... | Original |
3 pages, |
variable analog delay 3010-P 3010-N varactor voltage MIL-D-23859C MIL-D-23859C abstract |
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| Abstract: SF1111A SF1111A 160 MHz SAW Filter 0 dB -20 -40 -60 -80 -100 800 kHz/DIV 0 dB -2 2.4 ns/DIV -4 -6 -8 -10 200 kHz/DIV RF Monolithics, Inc. 4347 Sigma Road Dallas, Texas 75244 USA Phone: +1(972)233-2903 Fax: +1(972)387-8148 e-mail: info@rfm.com Home page: www.rfm.com European Sales Office sf1111ap 7/22/1999 R ... | Original |
1 pages, |
SF1111A SF1111A abstract |
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| Abstract: WFB40A1950CD WFB40A1950CD WCDMA (Band1) RF SAW WFB40A1950CD WFB40A1950CD min. 1950 - 1920 typ. - fn (MHz) max. - 1980 (dB) 1920 1980 MHz - 2.0 2.5 (dB) 1920 1980 MHz - 0.6 1.6 VSWR 1920 1980 MHz - 2.0 2.4 (ns) 1920 1980 MHz 1500 1540 MHz 1540 1570 MHz 2110 2170 MHz - 42 35 13 6 44 43 25 � +85 30 - - - (dB) ( ) ( ) 50 mm CH1 A/R LOG MAG REF 0. ... | Original |
1 pages, |
WFB40A1950CD WFB40A1950CD abstract |
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| Abstract: TMS320LC541B TMS320LC541B DSP DATA SHEET ADDENDUM SPRS071 SPRS071 Â OCTOBER 1998 ADDENDUM TMS320C54x, TMS320LC54x, TMS320VC54x DATA SHEET (SPRS039B SPRS039B) This addendum provides current updated information regarding different speed performance versions and available derivative devices in the '54x family. This addendum provides changed dc characteristics and parameter data that apply to the 66 MIPS version of the TMS320LC541B8 TMS320LC541B8 devices only. Data in the unshaded cells is new and applies only to the TMS320LC541B-6 TMS320LC541B-6 ... | Original |
4 pages, |
TMS320VC54x TMS320LC541B-66 TMS320LC541B SPRS071 SPRS039B TMS320LC541B abstract |
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| Abstract: 7404 VCC 6A ev SA 6V «A 4Y ^jïïUiîuiqjïUTjTu y y F (O, l>l J>1 1A IV 2A 2V 3A 3Y GND -19- Hex Inverters 74LS04 74LS04 74 S04 m * Ail IN iftfj OUT N LS ALS ALSK F S AS AC ACT HC HCO HCT BC BCT • ... | OCR Scan |
1 pages, |
74s04 7400 TTL TTL 7400 NOT gate 74LS04 7404 hex inverter 74ls04 TTL LS 7400 7404 TTL 7404 ls 74LS04 NOT gate 7410 JRC 7404 hc 7400 HC 7404 74LS04 74LS04 abstract |
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| Abstract: -17- 7402 Quad 2 Input NOR VCC 4V 48 4* 3Y 3B 3* lijiiinininininir IB 2Y ZA 2B GND o-mMi iz t OY=A+B < < m Ml I» ititi OUT » LS ALS ALSK F S AS AC ACT HC HCU HCT BC BCT *fi tpd nax L-H t 15 15 12 8 6.5 5. 5 4.5 10.4 11. 1 23 24 ns tpd max H-L i 15 15 10 7 5. 3 5.5 4.5 10.4 11. 1 23 24 ns Icc nan H IS 3.2 2.2 2.8 5. 6 28 5. 9 0.04 0.04 0.02 0.02 â- A Icc sax I 27 5.4 4 9 13 45 20.1 0.04 0.04 0.02 0.02 nA 11H â- ax ALL H 40 20 20 20 ... | OCR Scan |
1 pages, |
7427 74260 I426 LS 7402 datasheet abstract |
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| Abstract: HEF4072B HEF4072B gates DUAL 4-INPUT OR GATE The HEF4072B HEF4072B provides the positive dual 4-input OR function. The Outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. Fig. 1 Functional diagram. .ra näijiijiii i^un m. LU LU Lll IaI ILI LU LzJ 7Z69508 7Z69508 Fig. 2 Pinning diagram. HEF4072BP HEF4072BP : 14-lead DIL;plastic (SOT-27). HEF4072BD HEF4072BD: 14-lead DIL.ceramic (cerdip) (SOT-73). HEF4072BT HEF4072BT : 14-lead mini-pack; plastic (SO-14 SO-14; SOT-io8a). Ol 7 Z7542 Z7542 7.1 Fig. 3 Logic diagram (one ... | OCR Scan |
2 pages, |
Z7542 HEF4072BP HEF4072B 7Z69508 HEF4072B abstract |
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| Abstract: SN54/74LS40 SN54/74LS40 DUAL 4-INPUT NAND BUFFER DUAL 4-INPUT NAND BUFFER VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN54LSXXJ SN74LSXXN SN74LSXXN SN74LSXXD SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 ... | Original |
2 pages, |
751A-02 74LS40 truth table NOT gate 74 SN54/74LS40 SN54/74LS40 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| Xdelay Report File: Design: ftope.lca (4005EPG156-3 4005EPG156-3 4005EPG156-3 4005EPG156-3) Program: xdelay 5.0.24 Speedsfile: File 4005e.spd, Version 4000E 4000E 4000E 4000E.1, Revision 4005E 4005E 4005E 4005E.3 Xdelay path report options: TimeSpec `TS01' from group `FIFOFFS' to group `FFS' is 16.7ns. TimeSpec `TS02' from group `FIFOFFS' to group `FIFORAMS' is 16.7ns. TimeSpec `TS03' from group `PADS' to group `FIFOFFS' is 16.7ns. TimeSpec `TS04' from group `FIFOFFS' to group `PADS' is 16.7ns. Output will be sorted by decreasing path delays. A maximum o www.datasheetarchive.com/files/xilinx/pci/xc4000e/ftope.xrp |
Xilinx | 12/10/1995 | 14.27 Kb | XRP | ftope.xrp |
| XDelay: CLDB8H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XACT 4.8.2, Sat Mar 12 14:16:49 1994 XDelay Report File: Design: CLDB8H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XACT 4.8.2 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.3 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. - Paths not used in TimeSpecs : Logical Path www.datasheetarchive.com/download/82155996-960566ZC/xapp002v.zip (CLDB8H.XRP) |
Xilinx | 05/09/1996 | 193.16 Kb | ZIP | xapp002v.zip |
| XDelay: CLDB8H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XACT 4.8.2, Sat Mar 12 14:16:49 1994 XDelay Report File: Design: CLDB8H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XACT 4.8.2 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.3 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. - Paths not used in TimeSpecs : Logical Path www.datasheetarchive.com/download/8224988-988363ZC/wcd036f0.zip (CLDB8H.XRP) |
Xilinx | 12/02/1999 | 193.16 Kb | ZIP | wcd036f0.zip |
| XDelay: CLDB8H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XACT 4.8.2, Sat Mar 12 14:16:49 1994 XDelay Report File: Design: CLDB8H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XACT 4.8.2 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.3 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. - Paths not used in TimeSpecs : Logical Path www.datasheetarchive.com/download/85048902-996229ZC/xapp002v.zip (CLDB8H.XRP) |
Xilinx | 09/04/1997 | 193.16 Kb | ZIP | xapp002v.zip |
| XDelay: CLDB8H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XACT 4.8.2, Sat Mar 12 14:16:49 1994 XDelay Report File: Design: CLDB8H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XACT 4.8.2 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.3 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. - Paths not used in TimeSpecs : Logical Path www.datasheetarchive.com/download/49705392-987186ZC/wcd02ec8.zip (CLDB8H.XRP) |
Xilinx | 13/07/1998 | 193.16 Kb | ZIP | wcd02ec8.zip |
| .SUBCKT irlz24ns 1 2 3 * * Model Generated by MODPEX * *Copyright(c) Symmetry Design Systems* * All Rights Reserved * * UNPUBLISHED LICENSED SOFTWARE * * Contains Proprietary Information * * Which is The Property of * * SYMMETRY OR ITS LICENSORS * *Commercial Use or Resale Restricted * * by Symmetry License Agreement irlz24ns www.datasheetarchive.com/files/spicemodels/misc/spice/irlz24ns.spi |
Spice Models | 26/10/2011 | 1.57 Kb | SPI | irlz24ns.spi |
| *Aug 17, 2010 *Doc. ID: 90551, Rev. A *File Name: irfz24ns_PS.txt and irfz24ns_PS.spi *This document is intended as a SPICE modeling guideline and does not *constitute a commercial product datasheet. Designers should refer to the *appropriate data sheet of the same number for guaranteed specification *limits. .SUBCKT irfz24ns 1 2 3 * SPICE3 MODEL WITH THERMAL RC NETWORK * RS=0 BV=infinite IBV=1mA .MODEL MD3 D IS=1e-10 N=0.4 .ENDS irfz24ns *SPICE Thermal Model www.datasheetarchive.com/files/vishay/docs/90551/sihfz24s.lib |
Vishay | 18/08/2010 | 2.15 Kb | LIB | sihfz24s.lib |
| Xdelay Report File: Design: ftops.lca (4005EPG156-3 4005EPG156-3 4005EPG156-3 4005EPG156-3) Program: xdelay 5.0.24 Speedsfile: File 4005e.spd, Version 4000E 4000E 4000E 4000E.1, Revision 4005E 4005E 4005E 4005E.3 Xdelay path report options: TimeSpec `TS01' from group `FIFOFFS' to group `FFS' is 16.7ns. TimeSpec `TS02' from group `FIFOFFS' to group `FIFORAMS' is 16.7ns. TimeSpec `TS03' from group `PADS' to group `FIFOFFS' is 16.7ns. TimeSpec `TS04' from group `FIFOFFS' to group `PADS' is 16.7ns. Output will be sorted by decreasing path delays. A maximum o www.datasheetarchive.com/files/xilinx/pci/xc4000e/ftops.xrp |
Xilinx | 12/10/1995 | 14.54 Kb | XRP | ftops.xrp |
| V 50 K 138073377100 lvt16245 Y 0 D 0 0 1700 1100 Z 1 i 110 I 92 tisop74as:245 1 670 330 0 1 ' A 780 530 10 0 3 3 REFDES=U? A 780 330 10 0 1 1 @INTOOUT0=1NS:2.3NS:4.1NS A 780 320 10 0 1 1 @INTOOUT1=1NS:2.4NS:4.1NS A 780 290 10 0 1 1 @INTOOUTHZ=2.7NS:4.6NS:6.4NS A 780 280 10 0 1 1 @INTOOUTLZ=2.6NS:4.3NS:5.8NS A 780 310 10 0 1 1 @INTOOUTZH=1NS:3NS:5.3NS A 780 300 10 0 1 1 @INTOOUTZL=1NS:3.1NS:5.2NS C 93 1 136 0 C 103 2 135 0 C 104 1 134 0 C 105 1 133 0 C 106 1 132 0 C 107 1 131 0 C 108 2 130 0 C 11 www.datasheetarchive.com/download/60837585-238067ZC/database.zip (lvt16245.1) |
Intel | 17/06/1998 | 150.77 Kb | ZIP | database.zip |
| | Wirelist created using version 4.09. V 4.09 K 138073377100 lvt16245 DW lvt16245 AS tisop74as:245 ]) AS tisop74as:245 DEVICE=SN74AS245 SN74AS245 SN74AS245 SN74AS245 AS tisop74as:245 SIGNAL=VDD;20 AS tisop74as:245 SIGNAL=GND;10 AS tisop74as:245 PKG_TYPE=20PSOIC 20PSOIC 20PSOIC 20PSOIC AS tisop74as:245 PARTS=1 AS tisop74as:245 REFDES=U? AS tisop74as:245 LEVEL=STD AS tisop74as:245 @INTOOUTHZ=2NS:5.5NS AS tisop74as:245 @INTOOUTLZ=2NS:9.5NS AS tisop74as:245 @INTOOUTZL=2NS:8.5NS AS t www.datasheetarchive.com/download/60837585-238067ZC/database.zip (lvt16245.1) |
Intel | 17/06/1998 | 150.77 Kb | ZIP | database.zip |