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LM324NSRE4 Texas Instruments Quadruple Operational Amplifier 14-SO 0 to 70 ri Buy
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LM324NSR Texas Instruments Quadruple Operational Amplifier 14-SO 0 to 70 ri Buy

24ns Datasheet

Part Manufacturer Description PDF Type Ordering
24NS N/A Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
ri

1 pages,
36.75 Kb

Scan Buy
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24NS N/A Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
ri

1 pages,
36.75 Kb

Scan Buy
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24NSTRL N/A Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
ri

1 pages,
36.75 Kb

Scan Buy
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24NSTRL N/A Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
ri

1 pages,
36.75 Kb

Scan Buy
datasheet frame
24NSTRR N/A Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
ri

1 pages,
36.75 Kb

Scan Buy
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24NSTRR N/A Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
ri

1 pages,
36.75 Kb

Scan Buy
datasheet frame

24ns

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 7.5 74 24P,D,28J TU 10 55.5 210 24NS.JS, 28NL TTL 15 37 210 24NS.JS, 28FN TTL 25 25 105 24NS.JS, 28NL TTL 25 25 210 2 -6 PAL® Device , PAL20X8A PAL20X8A PAL20X4A PAL20X4A AmPAL20L10B AmPAL20L10B AmPAL20L10-20 AmPAL20L10-20 AmPAL20L10AL AmPAL20L10AL Package 24NS.JS. 28NL Technology TTL Inputs 14 12 , 210 20X10/ 20X10/ 20L10 20L10 24NS.JS, 28NL TTL 30 22.2 10 RegXOR 8 RegXOR 4RegXOR 165 180 180 , 4 4 9 PlOglMI* : w Sfatr Program mable Program mable EdgeActivated Flip-Flops 24NS.JS 28FN ... OCR Scan
datasheet

4 pages,
478.62 Kb

TTL 555 PAL 16V8 pal20r4b PAL20L10A PAL16L8B-4 PAL16l8A MMI PAL24 PAL16l8 MMI PALCE22V100-25 PAL16R4B TEXT
datasheet frame
Abstract: ©/7.8Ω 24ns/28ns 42ns into 1000pF into 1,000pF 4.5V to 18V SOT-143 MIC4417 MIC4417 Low-Side Driver Single Inverting 1.2A 7.6Ω/7.8Ω 24ns/28ns 37ns into 1000pF into 1 , © 20ns/24ns into 10nF 15ns/35ns 4.5V to 18V PDIP-8, SOIC-8, MIC4421A MIC4421A is recommended upgrade , Inverting 9A 0.8Ω/0.6Ω 20ns/24ns into 10nF 15ns/35ns 4.5V to 18V PDIP-8, SOIC , Driver Single Non-inverting 9A 0.8Ω/0.6Ω 20ns/24ns into 10nF 15ns/35ns 4.5V ... Micrel Semiconductor
Original
datasheet

2 pages,
183.45 Kb

TEXT
datasheet frame
Abstract: /7.8 24ns/28ns into 1000pF 42ns into 1,000pF 4.5V to 18V SOT-143 IttyBitty® Device. MIC4417 MIC4417 Low-Side Driver Single Inverting 1.2A 7.6/7.8 24ns/28ns into 1000pF 37ns into 1 , /24ns into 10nF 20ns/24ns into 10nF 15ns/35ns into 10nF 15ns/35ns into 10nF 4.5V to 18V PDIP , 0.8/0.6 20ns/24ns into 10nF 20ns/24ns into 10nF 15ns/35ns into 10nF 15ns/35ns into 10nF , Driver Single Inverting 12A 0.8/0.6 20ns/24ns into 15nF 15ns/35ns into 15nF 4.5V to 18V ... Original
datasheet

2 pages,
42.65 Kb

5962-8850308PA hex latch high speed mosfet driver MIC4102 MIC4103 MIC4104 MIC4120 MIC4126 mic4127 MIC4425 MIC4424 mosfet driver MIC44F18 MIC4429 MIC4428 SOIC-8 mosfet mic4427 logic level complementary MOSFET MLF8 mosfet driver 5v to 30v TEXT
datasheet frame
Abstract: ­25ppm, ­50ppm, ­100ppm 3.3V­0.3V 25mA 2.4ns 2.4ns 45/55% CFPP-303 CFPP-303 >40.00 to 100.00MHz ­25ppm, ­50ppm, ­100ppm 3.3V­0.3V 25mA 2.4ns 2.4ns 40/60% CFPP ... C-MAC Frequency Products
Original
datasheet

2 pages,
22.95 Kb

CFPP-303 TEXT
datasheet frame
Abstract: (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 Minimum RAS to CAS delay (=tRCD) 24ns 18h 30 Minimum activate precharge time (=tRAS) 50ns , latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 Minimum RAS to CAS delay (=tRCD) 24ns , time (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 ... Samsung Electronics
Original
datasheet

9 pages,
70.68 Kb

M466S1724BT2-L10 M466S1723BT3-L10 M466S1723BT2-L10 M466S0924BT0-L10 K4S281632B-TL10 K4S280832B-TL10 TEXT
datasheet frame
Abstract: (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 Minimum RAS to CAS delay (=tRCD) 24ns 18h 30 Minimum activate precharge time (=tRAS) 50ns , time (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 Minimum RAS to CAS delay (=tRCD) 24ns 18h 30 Minimum activate precharge time (=tRAS) 50ns , time (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 ... Samsung Electronics
Original
datasheet

9 pages,
70.58 Kb

M466S1724MT2-L10 M466S1723MT3-L10 M466S1723MT2-L10 M466S0924MT0-L10 K4S281632M-TL10 K4S280832m TEXT
datasheet frame
Abstract: APLESSEY W Semiconductors, SP9680 SP9680 ULTRA FAST COMPARATOR The SP9680 SP9680 is an ultra fast comparator manufactured using a high performance bipolar process w hich makes possible very short propagation delays (2.4ns typ.). The circuit has differential inputs and complementary E C L outputs, capable of driving 50 O lines. The device is manufactured in a low cost mini-dip package and is intended as an alternative , .)[ V k |-5iV)[ MP8 DP8 FEATURES Propagation Delay 2.4ns Typ. Complem entary ECL Outputs ... OCR Scan
datasheet

1 pages,
59.56 Kb

SP9680MP SP9680DP 552V fast comparator SP9680 SP9685 36MNWO TEXT
datasheet frame
Abstract: PLESSEY W Semiconductors, SP9680 SP9680 ULTRA FAST COMPARATOR The SP9680 SP9680 is an ultra fast comparator manufactured using a high performance bipolar process which makes possible very short propagation delays (2.4ns typ.). The circuit has differential inputs and complementary ECL outputs, capable of driving 50 D lines. The device is manufactured in a low cost mini-dip package and is intended as an , required. FEATURES ■ Propagation Delay 2.4ns Typ. ■ Complementary ECL Outputs ■ 50 Q Line Driving ... OCR Scan
datasheet

2 pages,
90.7 Kb

SP9680DP SP9680 fast comparator SP9680MP sp9685 TEXT
datasheet frame
Abstract: ) 30ns (C) 30ns tAC (A) 24ns (B) 24ns (C) 24ns tRP (A) 30ns (B) 36ns (C) 45ns tRRD (A) 30ns (B) 24ns (C) 30ns tRCD (A) 30ns (B) 36ns (C) 45ns tRAS (A) 50ns (B) 48ns (C) 45ns 64MB - , from Clock tAC (A) 9ns (B) 9ns (C) 10ns tCLK (A) 30ns (B) 30ns (C) 30ns tAC (A) 24ns (B) 24ns (C) 24ns tRP (A) 30ns (B) 36ns (C) 45ns tRRD (A) 30ns (B) 24ns (C) 30ns tRCD (A) 30ns ... Hyundai
Original
datasheet

15 pages,
281.6 Kb

HYM7V64801 HYM7V64800/ HYM7V64801/ HYM7V64830/ HYM7V64831 TEXT
datasheet frame
Abstract: =15ns Manufacturer Information Unused Storage Locations tAC (A) 24ns (B) 24ns (C) 24ns tRP BYTE27 BYTE27 (A) 30ns (B) 36ns (C) 45ns tRRD BYTE28 BYTE28 (A) 30ns (B) 24ns (C) 30ns tRCD BYTE29 BYTE29 (A) 30ns (B , =3, ©Cycle Time=15ns Manufacturer Information Unused Storage Locations tAC (A) 24ns (B) 24ns (C) 24ns tRP (A) 30ns (B) 36ns (C) 45ns tRRD BYTE27 BYTE27 BYTE28 BYTE28 (A) 30ns (B) 24ns (C) 30ns tRCD BYTE29 BYTE29 ... OCR Scan
datasheet

15 pages,
685.22 Kb

HYM7V641601 TEXT
datasheet frame
Abstract: 7.5 74 24P,D,28J TU 10 55.5 210 24NS.JS, 28NL TTL 15 37 210 24NS.JS, 28FN TTL 25 25 105 24NS.JS, 28NL TTL 25 25 210 2 -6 PAL® Device , PAL20X8A PAL20X8A PAL20X4A PAL20X4A AmPAL20L10B AmPAL20L10B AmPAL20L10-20 AmPAL20L10-20 AmPAL20L10AL AmPAL20L10AL Package 24NS.JS. 28NL Technology TTL Inputs 14 12 , 210 20X10/ 20X10/ 20L10 20L10 24NS.JS, 28NL TTL 30 22.2 10 RegXOR 8 RegXOR 4RegXOR 165 180 180 , 4 4 9 PlOglMI* : w Sfatr Program mable Program mable EdgeActivated Flip-Flops 24NS.JS 28FN ... Texas Instruments
Original
datasheet

4 pages,
59.57 Kb

TMS320VC54x TMS320LC541B-66 TMS320LC541B SPRS071 SPRS039B TEXT
datasheet frame
Abstract: /7.8 24ns/28ns into 1000pF 42ns into 1,000pF 4.5V to 18V SOT-143 IttyBitty® Device. MIC4417 MIC4417 Low-Side Driver Single Inverting 1.2A 7.6/7.8 24ns/28ns into 1000pF 37ns into 1 , /24ns into 10nF 20ns/24ns into 10nF 15ns/35ns into 10nF 15ns/35ns into 10nF 4.5V to 18V PDIP , 0.8/0.6 20ns/24ns into 10nF 20ns/24ns into 10nF 15ns/35ns into 10nF 15ns/35ns into 10nF , Driver Single Inverting 12A 0.8/0.6 20ns/24ns into 15nF 15ns/35ns into 15nF 4.5V to 18V ... OCR Scan
datasheet

7 pages,
278.29 Kb

HEF4737VD HEF4737V HEF4737BP HEF4737BD HEF4737B HEF4737VP TEXT
datasheet frame

Archived Files

Abstract Saved from Date Saved File Size Type Download
( 12.7ns) To: RAM Setup (Addr), Blk DOR31 DOR31 : 2.4ns ( 15.1ns) Source clock net ( 12.7ns) To: RAM Setup (Addr), Blk DOR31 DOR31 : 2.4ns ( 15.1ns) Source clock net ( 12.7ns) To: RAM Setup (Addr), Blk DOR29 DOR29 : 2.4ns ( 15.1ns) Source clock net ( 12.7ns) To: RAM Setup (Addr), Blk DOR29 DOR29 : 2.4ns ( 15.1ns) � Logical Path : 2.7ns ( 12.7ns) To: RAM Setup (Addr), Blk DOR27 DOR27 : 2.4ns ( 15.1ns
/datasheets/files/xilinx/pci/xc4000e/ftope.xrp
Xilinx 12/10/1995 14.27 Kb XRP ftope.xrp
MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS28 ugate ( + tplhty=12ns tplhmx=24ns + tphlty=12ns tphlmx=24ns + ) *$ *- * 74LS30 74LS30 8-input Positive-Nand Gates * * The TTL Data Book MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS37 ugate ( + tplhty=12ns tplhmx=24ns + tphlty=12ns tphlmx=24ns + ) *$ *- * 74LS38 74LS38 Quadruple 2-input Positive-Nand Buffers w {IO_LEVEL} .ends * .model D_LS40 ugate ( + tplhty=12ns tplhmx=24ns + tphlty=12ns tphlmx=24ns + ) *$
/datasheets/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/74ls.lib
Spice Models 29/07/2012 571.07 Kb LIB 74ls.lib
MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS28 ugate ( + tplhty=12ns tplhmx=24ns + tphlty=12ns tphlmx=24ns + ) *$ *- * 74LS30 74LS30 8-input Positive-Nand Gates * * The TTL Data Book MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS37 ugate ( + tplhty=12ns tplhmx=24ns + tphlty=12ns tphlmx=24ns + ) *$ *- * 74LS38 74LS38 Quadruple 2-input Positive-Nand Buffers w {IO_LEVEL} .ends * .model D_LS40 ugate ( + tplhty=12ns tplhmx=24ns + tphlty=12ns tphlmx=24ns + ) *$
/datasheets/files/spicemodels/misc/74ls.lib
Spice Models 19/12/2001 571.09 Kb LIB 74ls.lib
CASE( + CLEAR, DELAY(-1,24ns,36ns), + RATE , DELAY(-1,15ns,23ns), + DELAY(-1,24ns,36ns) + ) + } + Z = { + CASE( + STRB & TRN_HL, DELAY(-1,15ns,23ns), + DELAY(-1,24ns,36ns) + ) + , DELAY(-1,15NS,23NS), + DELAY(-1,16NS,24NS)} + TCBAR = { + CASE( + T & TRN_LH, DELAY ), + DELAY(-1,24NS,36NS)} U4 CONSTRAINT(9) DPWR DGND + CP P0 P1 P2 P3 CETBAR CEPBAR U/DBAR
/datasheets/files/spicemodels/misc/modelos/spice_complete/dig167.lib
Spice Models 18/04/2010 359.87 Kb LIB dig167.lib
: 2.4ns ( 15.1ns) Source clock net : "CLK" (Rising edge) Worst case clock delay from origin ( 12.7ns) To: RAM Setup (Addr), Blk DOR16 DOR16 : 2.4ns ( 15.1ns) Source clock net ( 12.5ns) To: RAM Setup (Addr), Blk DOR31 DOR31 : 2.4ns ( 14.9ns) Source clock net ( 12.5ns) To: RAM Setup (Addr), Blk DOR31 DOR31 : 2.4ns ( 14.9ns) � Logical Path : 2.7ns ( 12.5ns) To: RAM Setup (Addr), Blk DOR29 DOR29 : 2.4ns ( 14.9ns
/datasheets/files/xilinx/pci/xc4000e/ftops.xrp
Xilinx 12/10/1995 14.54 Kb XRP ftops.xrp
& TRN_HL, DELAY(1ns,-1,10ns), + TRN_LH, DELAY(5ns,-1,24ns), + TRN_HL, DELAY(1ns,-1
/datasheets/files/spicemodels/misc/modelos/spice_complete/dig604.lib
Spice Models 18/04/2010 459.64 Kb LIB dig604.lib
TRN_HL, DELAY(8NS,-1,24NS), + ENABLE & TRN_HL, DELAY(4NS,-1,19NS), + ENABLE & TRN_LH, DELAY = { + CASE( + SELECT & TRN_LH, DELAY(7NS,-1,24NS), + SELECT & TRN_HL, DELAY(7NS (13NS,24NS,38NS), + ABLE1 & TRN_HL, DELAY( 6NS,13NS,22NS), + ADDR & TRN_LH, DELAY(13NS } + 2Y0_O 2Y1_O 2Y2_O 2Y3_O = { + CASE ( + ABLE2 & TRN_LH, DELAY(13NS,24NS,38NS), + TRN_LH, DELAY(7NS,15NS,24NS), + ENABLE & TRN_LH, DELAY(7NS,14NS,20NS), + DATA & TRN_LH
/datasheets/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/74als.lib
Spice Models 29/07/2012 357.83 Kb LIB 74als.lib
tplhmx=32ns + tphlty=16ns tphlmx=24ns + ) *$ {MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_26 ugate ( + tplhty=16ns tplhmx=24ns + tphlty=11ns tpgqlhmx=30ns tpgqhlty=7ns + tpgqhlmx=15ns tpdqlhty=24ns + tpdqlhmx=40ns tpdqhlty=7ns + tpdqhlmx=15ns +
/datasheets/files/spicemodels/misc/7400.lib
Spice Models 19/12/2001 282.17 Kb LIB 7400.lib
tplhmx=32ns + tphlty=16ns tphlmx=24ns + ) *$ {MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_26 ugate ( + tplhty=16ns tplhmx=24ns + tphlty=11ns tpgqlhmx=30ns tpgqhlty=7ns + tpgqhlmx=15ns tpdqlhty=24ns + tpdqlhmx=40ns tpdqhlty=7ns + tpdqhlmx=15ns +
/datasheets/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/7400.lib
Spice Models 29/07/2012 282.15 Kb LIB 7400.lib
DATA & TRN_LH, DELAY(-1,16ns,24ns), + DATA & TRN_HL, DELAY(-1,25ns,38ns), + LOAD & TRN_LH, DELAY(-1,22ns,33ns), + LOAD & TRN_HL, DELAY(-1,24ns,36ns), + CK2 & TRN_HL, DELAY(-1,14ns,21ns), + DATA & TRN_LH, DELAY(-1,16ns,24ns), + LOAD & TRN_HL, DELAY(-1,24ns,36ns), + DELAY(-1,26ns,39ns) + ) + CK2 & TRN_LH, DELAY(-1,24ns,36ns), + CK2 & TRN_HL, DELAY(-1,28ns,42ns), +
/datasheets/files/spicemodels/misc/modelos/spice_complete/dig195.lib
Spice Models 18/04/2010 169.82 Kb LIB dig195.lib