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LM324NSRG4 Texas Instruments Quadruple Operational Amplifier 14-SO 0 to 70 ri BuyFREE Buy
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24ns Datasheet

Part Manufacturer Description PDF Type Ordering
24NS N/A Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
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1 pages,
36.75 Kb

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24NS N/A Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
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1 pages,
36.75 Kb

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24NSTRL N/A Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
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36.75 Kb

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24NSTRL N/A Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
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36.75 Kb

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24NSTRR N/A Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
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36.75 Kb

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24NSTRR N/A Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
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36.75 Kb

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24ns

Catalog Datasheet Results Type PDF Document Tags
Abstract: 2.4ns 2.4ns 45/55% CFPP-303 CFPP-303 >40.00 to 100.00MHz �ppm, �ppm, �0ppm 3.3V�3V 25mA 2.4ns 2.4ns 40/60% CFPP-303 CFPP-303 Ordering Example Frequency Model Number 24.0MHz CFPP-303 CFPP-303 I ... Original
datasheet

2 pages,
22.95 Kb

CFPP-303 CFPP-303 abstract
datasheet frame
Abstract: APLESSEY W Semiconductors, SP9680 SP9680 ULTRA FAST COMPARATOR The SP9680 SP9680 is an ultra fast comparator manufactured using a high performance bipolar process w hich makes possible very short propagation delays (2.4ns typ.). The circuit has differential inputs and complementary E C L outputs, capable of driving 50 O lines. The device is manufactured in a low cost mini-dip package and is intended as an alternative , )[ V k |-5iV)[ MP8 DP8 FEATURES Propagation Delay 2.4ns Typ. Complem entary ECL Outputs ... OCR Scan
datasheet

1 pages,
59.56 Kb

SP9680MP SP9680DP SP9680 552V fast comparator SP9685 SP9680 abstract
datasheet frame
Abstract: 74 24P,D,28J TU 10 55.5 210 24NS.JS, 28NL TTL 15 37 210 24NS.JS, 28FN TTL 25 25 105 24NS.JS, 28NL TTL 25 25 210 2 -6 PAL® Device , PAL20X4A PAL20X4A AmPAL20L10B AmPAL20L10B AmPAL20L10-20 AmPAL20L10-20 AmPAL20L10AL AmPAL20L10AL Package 24NS.JS. 28NL Technology TTL Inputs 14 12 12 12 16 , / 20L10 20L10 24NS.JS, 28NL TTL 30 22.2 10 RegXOR 8 RegXOR 4RegXOR 165 180 180 180 210 165 105 , 4 4 9 PlOglMI* : w Sfatr Program mable Program mable EdgeActivated Flip-Flops 24NS.JS 28FN ... OCR Scan
datasheet

4 pages,
478.62 Kb

TTL 555 pal20r4b PAL20L10A PAL16L8B-4 PALCE22V100-25 PAL16l8 MMI datasheet abstract
datasheet frame
Abstract: AverLogic Video FIFO Selection Guide FIFO Usage Frame Buffer Bus Width 8-bit 8-bit AL460A-7-PBF/ AL460A-7-PBF/ AL460A-13-PBF AL460A-13-PBF Density 128M AL440B-12-PBF/ AL440B-12-PBF/ AL440B-24-PBF AL440B-24-PBF 4M 3M Max. Speed Key Features Width Expansion AL422B-PBF AL422B-PBF 50Mhz 80Mhz/ 40Mhz 150Mhz/ 75Mhz 20ns 12ns/ 24ns 6ns Input Enable Output Enable 16-bit Window Mode Access Polarity Select Double buffering Power Supply 3.3V or 5V 3.3V 2.5 & 3.3V 5V input ... Original
datasheet

1 pages,
19.75 Kb

80MHz 5V buffering al422b FIFO AL460A-13-PBF AL440B-24-PBF AL460A-7-PBF AL460A AL460A-7 AL440B-12-PBF AL422B-PBF 28-SOP AL460A-7-PBF/ AL440B-12-PBF/ AL422B-PBF abstract
datasheet frame
Abstract: AverLogic Video FIFO Selection Guide FIFO Usage Frame Buffer Bus Width 8-bit 8-bit AL460A-PBF AL460A-PBF Density 128M AL440B-12-PBF AL440B-12-PBF & AL440B-24-PBF AL440B-24-PBF 4M 3M Max. Speed Key Features Width Expansion AL422B-PBF AL422B-PBF 50Mhz 80Mhz/ 40Mhz 150Mhz 20ns 12ns/ 24ns 6ns Input Enable Output Enable 16-bit Window Mode Access Polarity Select Double buffering Power Supply 3.3V or 5V 3.3V 2.5 & 3.3V 5V input tolerant ... Original
datasheet

1 pages,
19.73 Kb

AL460A AL460A-PBF 50mhz FIFO al422b AL440B AL440B-24-PBF al440 40mhz buffering AL440B-12-PBF AL422B-PBF 28-SOP AL422B-PBF abstract
datasheet frame
Abstract: /7.8 24ns/28ns into 1000pF 42ns into 1,000pF 4.5V to 18V SOT-143 IttyBitty® Device. MIC4417 MIC4417 Low-Side Driver Single Inverting 1.2A 7.6/7.8 24ns/28ns into 1000pF 37ns into 1 , MIC4421 MIC4421 MIC4421A MIC4421A(2) Low-Side Driver Single Inverting 9A 0.8/0.6 0.8/0.6 20ns/24ns into 10nF 20ns/24ns into 10nF 15ns/35ns into 10nF 15ns/35ns into 10nF 4.5V to 18V PDIP-8, SOIC-8 , 20ns/24ns into 10nF 20ns/24ns into 10nF 15ns/35ns into 10nF 15ns/35ns into 10nF 4.5V to 18V ... Original
datasheet

2 pages,
42.65 Kb

5962-8850308PA 5962-8850307PA MIC4129 MIC4420 MIC4423 Peak Low-Side MOSFET Driver p-channel mosfet driver MOSFET DRIVER circuits MIC4452A MIC4424 MIC4425 MIC4426 mosfet driver MIC4100 MIC4101 MIC4100 abstract
datasheet frame
Abstract: PLESSEY W Semiconductors, SP9680 SP9680 ULTRA FAST COMPARATOR The SP9680 SP9680 is an ultra fast comparator manufactured using a high performance bipolar process which makes possible very short propagation delays (2.4ns typ.). The circuit has differential inputs and complementary ECL outputs, capable of driving 50 D lines. The device is manufactured in a low cost mini-dip package and is intended as an alternative to , FEATURES - Propagation Delay 2.4ns Typ. - Complementary ECL Outputs - 50 Q Line Driving Capability - ... OCR Scan
datasheet

2 pages,
90.7 Kb

SP9680MP SP9680DP SP9680 fast comparator sp9685 SP9685 SP9680 abstract
datasheet frame
Abstract: CLK1 CLK2 0 12 24 12ns MULTICYCLE=2 HOLD_MULTICYCLE=2 30 clk2 tSU 24ns tH 12ns 12ns 24ns 12ns 24ns 31 12ns MULTICYCLE=2 HOLD_MULTICYCLE=1 26 Altera , 12ns tSU tH 0ns 24ns clk2 clk1 2ns 32 Period = 12nsoffset = 2ns Altera ... Original
datasheet

36 pages,
902.1 Kb

datasheet abstract
datasheet frame
Abstract: (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 Minimum RAS to CAS delay (=tRCD) 24ns 18h 30 Minimum activate precharge time (=tRAS) 50ns , time (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 Minimum RAS to CAS delay (=tRCD) 24ns 18h 30 Minimum activate precharge time (=tRAS) 50ns , time (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 ... Original
datasheet

9 pages,
70.58 Kb

M466S1724MT2-L10 M466S1723MT3-L10 M466S1723MT2-L10 M466S0924MT0-L10 K4S281632M-TL10 K4S280832m datasheet abstract
datasheet frame
Abstract: (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 Minimum RAS to CAS delay (=tRCD) 24ns 18h 30 Minimum activate precharge time (=tRAS) 50ns , latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 Minimum RAS to CAS delay (=tRCD) 24ns , time (=tRP) 24ns 18h 28 Minimum row active to row active delay (tRRD) 20ns 14h 29 ... Original
datasheet

9 pages,
70.68 Kb

M466S1724BT2-L10 M466S1723BT3-L10 M466S1723BT2-L10 M466S0924BT0-L10 K4S281632B-TL10 K4S280832B-TL10 datasheet abstract
datasheet frame
Abstract: SF1111A SF1111A 160 MHz SAW Filter 0 dB -20 -40 -60 -80 -100 800 kHz/DIV 0 dB -2 2.4 ns/DIV -4 -6 -8 -10 200 kHz/DIV RF Monolithics, Inc. 4347 Sigma Road Dallas, Texas 75244 USA Phone: +1(972)233-2903 Fax: +1(972)387-8148 e-mail: info@rfm.com Home page: www.rfm.com European Sales Office sf1111ap 7/22/1999 R ... Original
datasheet

1 pages,
50.96 Kb

SF1111A SF1111A abstract
datasheet frame
Abstract: SPEED/PACKAGE AVAILABILITY 54 F.W 54LS F,W 74 A,F 74 L S A,F 25°c SWITCHING CHARACTERISTICS vcc - 5V, t a 54/74 T EST C ONDITIO NS PARAM ETER Propagation delay time tP L H 54/74LS 54/74LS C L =15pF R(_=2kn MAX M IN TYP M AX UNIT C L =15pF RL =400Q MIN TYP Low-to-high 7 11 5 15 ns tpHL High-to-low 10 15 9 15 ns L o a d circuit a n d typical w aveform s are sh o w n at the front of section. SPEED/PACKAGE AVAILABILITY 54 F,W 54L S F,W 74 A,F 74LS A, ... OCR Scan
datasheet

1 pages,
25.72 Kb

datasheet abstract
datasheet frame
Abstract: GATEARRAYS AND CELL-BASED fCs Lineup of Gate Arrays Available Gate Count Channel Type Gate count LZ95 series « Internal gate Input butter Output butter 1.2 ns/gate (Vcc = 5 V, F.O. = 3, 4 = 2 mm) 2.4 ns (Vcc = 5 V, F.O. = 3 , i = 2mm) 4.0 ns (Vcc = 5 V, 315 gates 650 gates 1 170 gates 1 680 gates 2 000 gates 3 100 gates 4 255 gates 5 000 gates 6 075 gates 8 370 gates 10 032 gates Model No. LZ95300 LZ95300 LZ95650 LZ95650 LZ951170 LZ951170 LZ951600 LZ951600 LZ952000 LZ952000 LZ953000 LZ953000 LZ954000 LZ954000 LZ955000 LZ955000 LZ956000 LZ956000 LZ958000 LZ958000 LZ9510000 LZ9510000 ... OCR Scan
datasheet

1 pages,
139.63 Kb

lz95 datasheet abstract
datasheet frame
Abstract: WFB40A1950CD WFB40A1950CD WCDMA (Band1) RF SAW WFB40A1950CD WFB40A1950CD min. 1950 - 1920 typ. - fn (MHz) max. - 1980 (dB) 1920 1980 MHz - 2.0 2.5 (dB) 1920 1980 MHz - 0.6 1.6 VSWR 1920 1980 MHz - 2.0 2.4 (ns) 1920 1980 MHz 1500 1540 MHz 1540 1570 MHz 2110 2170 MHz - 42 35 13 6 44 43 25 � +85 30 - - - (dB) ( ) ( ) 50 mm CH1 A/R LOG MAG REF 0. ... Original
datasheet

1 pages,
435.77 Kb

WFB40A1950CD WFB40A1950CD abstract
datasheet frame
Abstract: TMS320LC541B TMS320LC541B DSP DATA SHEET ADDENDUM SPRS071 SPRS071 ­ OCTOBER 1998 ADDENDUM TMS320C54x, TMS320LC54x, TMS320VC54x DATA SHEET (SPRS039B SPRS039B) This addendum provides current updated information regarding different speed performance versions and available derivative devices in the '54x family. This addendum provides changed dc characteristics and parameter data that apply to the 66 MIPS version of the TMS320LC541B8 TMS320LC541B8 devices only. Data in the unshaded cells is new and applies only to the TMS320LC541B-6 TMS320LC541B-6 ... Original
datasheet

4 pages,
59.57 Kb

TMS320VC54x TMS320LC541B-66 TMS320LC541B SPRS071 SPRS039B TMS320LC541B abstract
datasheet frame
Abstract: -17- 7402 Quad 2 Input NOR VCC 4V 48 4* 3Y 3B 3* lijiiinininininir IB 2Y ZA 2B GND o-mMi iz t OY=A+B < < m Ml I» ititi OUT » LS ALS ALSK F S AS AC ACT HC HCU HCT BC BCT *fi tpd nax L-H t 15 15 12 8 6.5 5. 5 4.5 10.4 11. 1 23 24 ns tpd max H-L i 15 15 10 7 5. 3 5.5 4.5 10.4 11. 1 23 24 ns Icc nan H IS 3.2 2.2 2.8 5. 6 28 5. 9 0.04 0.04 0.02 0.02 -A Icc sax I 27 5.4 4 9 13 45 20.1 0.04 0.04 0.02 0.02 nA 11H -ax ALL H 40 20 20 20 ... OCR Scan
datasheet

1 pages,
24.15 Kb

7427 7402 hc I426 74260 LS 7402 datasheet abstract
datasheet frame
Abstract: 7404 VCC 6A ev SA 6V «A 4Y ^jïïUiîuiqjïUTjTu y y F (O, l>l J>1 1A IV 2A 2V 3A 3Y GND -19- Hex Inverters 74LS04 74LS04 74 S04 m * Ail IN iftfj OUT N LS ALS ALSK F S AS AC ACT HC HCO HCT BC BCT • ... OCR Scan
datasheet

2 pages,
23.01 Kb

74ls04 7404 hex inverter ls 7400 n 7400 TTL NOT gate 74LS04 TTL 7400 df 42 AC 7400 ls TTL LS 7400 7404 TTL 74LS04 NOT gate 7400 hc 7404 7404 ls datasheet abstract
datasheet frame

Datasheet Content (non pdf)

Abstract Saved from Date Saved File Size Type Download
Over 1.1 million files (1986-2014): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.
 
( 12.7ns) To: RAM Setup (Addr), Blk DOR31 DOR31 DOR31 DOR31 : 2.4ns ( 15.1ns) Source clock net ( 12.7ns) To: RAM Setup (Addr), Blk DOR31 DOR31 DOR31 DOR31 : 2.4ns ( 15.1ns) Source clock net ( 12.7ns) To: RAM Setup (Addr), Blk DOR29 DOR29 DOR29 DOR29 : 2.4ns ( 15.1ns) Source clock net ( 12.7ns) To: RAM Setup (Addr), Blk DOR29 DOR29 DOR29 DOR29 : 2.4ns ( 15.1ns) Logical Path : 2.7ns ( 12.7ns) To: RAM Setup (Addr), Blk DOR27 DOR27 DOR27 DOR27 : 2.4ns ( 15.1ns
www.datasheetarchive.com/files/xilinx/pci/xc4000e/ftope.xrp
Xilinx 12/10/1995 14.27 Kb XRP ftope.xrp
switching speeds (t ON = 24ns, t OFF = 16ns max), handle Rail-to-Rail® analog signals, and consume less Capacity (150mA continuous) 1.8V CMOS Logic Compatible (+3V Supply) Fast Switching: t ON = 24ns, t OFF
www.datasheetarchive.com/files/maxim/0012/quick028.htm
Maxim 02/05/2002 12.35 Kb HTM quick028.htm
No abstract text available
www.datasheetarchive.com/download/82155996-960566ZC/xapp002v.zip (CLDB8H.XRP)
Xilinx 05/09/1996 193.16 Kb ZIP xapp002v.zip
No abstract text available
www.datasheetarchive.com/download/85048902-996229ZC/xapp002v.zip (CLDB8H.XRP)
Xilinx 09/04/1997 193.16 Kb ZIP xapp002v.zip
No abstract text available
www.datasheetarchive.com/download/49705392-987186ZC/wcd02ec8.zip (CLDB8H.XRP)
Xilinx 13/07/1998 193.16 Kb ZIP wcd02ec8.zip
No abstract text available
www.datasheetarchive.com/download/8224988-988363ZC/wcd036f0.zip (CLDB8H.XRP)
Xilinx 12/02/1999 193.16 Kb ZIP wcd036f0.zip
No abstract text available
www.datasheetarchive.com/download/60837585-238067ZC/database.zip (lvt16245.1)
Intel 17/06/1998 150.77 Kb ZIP database.zip
: 2.4ns ( 15.1ns) Source clock net : "CLK" (Rising edge) Worst case clock delay from origin ( 12.7ns) To: RAM Setup (Addr), Blk DOR16 DOR16 DOR16 DOR16 : 2.4ns ( 15.1ns) Source clock net ( 12.5ns) To: RAM Setup (Addr), Blk DOR31 DOR31 DOR31 DOR31 : 2.4ns ( 14.9ns) Source clock net ( 12.5ns) To: RAM Setup (Addr), Blk DOR31 DOR31 DOR31 DOR31 : 2.4ns ( 14.9ns) Logical Path : 2.7ns ( 12.5ns) To: RAM Setup (Addr), Blk DOR29 DOR29 DOR29 DOR29 : 2.4ns ( 14.9ns
www.datasheetarchive.com/files/xilinx/pci/xc4000e/ftops.xrp
Xilinx 12/10/1995 14.54 Kb XRP ftops.xrp
to low, or a total of 24ns . Allowing for minimum usable pulse widths of 10ns and 3ns skew variations
www.datasheetarchive.com/files/intersil/device_pages/faq_775.html
Intersil 13/10/2005 8.33 Kb HTML faq_775.html
No abstract text available
www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (mip405.c)
Xilinx 11/11/2004 9180.01 Kb ZIP xapp542.zip