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24-bpp

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Abstract: YPbPr: 480i/p, 576i/p, 720p, 1080i Single-link DVI: 1600x1200 60Hz 24bpp Q2-08 Dual-link DVI: 2048x1536 60Hz 24bpp Single-link LVDS: 1280x1024 60Hz 24bpp Dual-link LVDS: 2048x1536 60Hz 24bpp HDMITM: 1920x1080i 60Hz 24bpp DVO: 220MHz pixel clk Q2-10 AMD Embedded Solutions, cont. AMD , /p Single-link DVI: 1600x1200 60Hz 24bpp Dual-link DVI: 2048x1536 60Hz 24bpp Q1-10 Single-link LVDS: 1280x1024 60Hz 24bpp Dual-link LVDS: 2048x1536 60Hz 24bpp DisplayPort 1.1a: 2560x1600 Advanced Micro Devices
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E4690 GET56NGBB22GVE AMD Athlon 64 X2 dual 4800 pin out GDDR5 phy E6460 TEN54LSDV23GME 43838Q
Abstract: Entertainment (RSE) ­ Navigation Display ­ 18bpp or 24bpp Color Depth ­ WQVGA to XGA Support · WQVGA Resolution (400 X 240), 24bpp, ~6MHz · WVGA resolution (800 X 480), 18bpp or 24bpp, ~30MHz · DWVGA Resolution (1600 X 480), 18bpp or 24bpp, ~65MHz · XGA resolution (1024 X 768), 24bpp, ~65MHz 6 Color , ) ­ 18-bpp, 262k colors ­ 24-bpp, 16.7M colors (True) 8 ­ bits per pixel image 256 colors ­ , FPD-Link II / DS9OUR905/906 Enhancements! Full 24-bpp Color 5 to 65 MHz PCLK NEW SIGCON NEW National Semiconductor
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DS90UR905 DS90UR906 DS90UR905 DS90UR906 18-bpp WQVGA Programmable LVDS Receiver 24-Bit RGB DS90UR905/DS90UR906 DS90UR905/906 412210V M1000000
Abstract: -layers + 16bit YUV x 1-layer + 24BPP x 1-layer 8BPP(L0-Layer) 16bit YUV(Video Capture, L1-Lyaer) 8BPP(L2-Layer) 24BPP(L3-Layer) Background Color Limitation Case 2 :16BPP x 1-layer + 16bit YUV x 1-layer + 24BPP x 1-layer 16BPP(L0-Layer) 16bit YUV(Video Capture, L1-Lyaer) 24BPP(L2-Layer) Background Color -
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video capture 166MH 133MH
Abstract: into 2 channels of 4D+C LVDS streams. For all the modes, the device supports 18bpp and 24bpp color , for single and dual pixel applications supporting either 24bpp or 18bpp color depths. In the Dual Pixel / 24bpp mode, eight LVDS data lines are provided along with two LVDS clock lines (8D+2C). The De , i^ ) R R R R ) R R ) ( FIGURE 16. Single Pixel / 24bpp LVDS Mapping s Current Cycle \ O , Pixel / 24bpp 8D+2C LVDS Interface Mapping is shown in Figure 14. A Dual Pixel / 1 8bpp mode is also -
OCR Scan
DS90C187
Abstract: 18bpp and 24bpp color. The DS90C187 is offered in a small 92 pin dual row QFN package and features , applications supporting either 24bpp or 18bpp color depths. In the Dual Pixel / 24bpp mode, eight LVDS data , . The Dual Pixel / 24bpp 8D+2C LVDS Interface Mapping is shown in Figure 14. A Dual Pixel / 18bpp mode , save power. Their respective inputs are ignored. (Figure 15) In the Single Pixel / 24bpp mode, four , ignored, used for L/R signaling or function as a general purpose bit. The Single Pixel / 24bpp 4D+C LVDS Texas Instruments
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H18B LVDS display tcon old ferrite ER6 SIZE AN-1187 AN-1108 AN-905 LFA92A
Abstract: 18bpp and 24bpp color. The DS90C187 is offered in a small 92 pin dual row QFN package and features , applications supporting either 24bpp or 18bpp color depths. In the Dual Pixel / 24bpp mode, eight LVDS data , . The Dual Pixel / 24bpp 8D+2C LVDS Interface Mapping is shown in Figure 14. A Dual Pixel / 18bpp mode , save power. Their respective inputs are ignored. (Figure 15) In the Single Pixel / 24bpp mode, four , ignored, used for L/R signaling or function as a general purpose bit. The Single Pixel / 24bpp 4D+C LVDS Texas Instruments
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T-CON BOARD diagrams B27 QFN INA27 lcd 7" 18-bit digital lvds switch tcon with lvds input
Abstract: EPSON Graphics Controller Graphic Controller Roadmaps September 2005 January 2007 EPSON EUROPE ELECTRONICS GmbH LCD Controller/ Mobile Graphics Engines Product Roadmap Frame Buffer WVGA 24bpp LCD Controller/ Mobile Graphic Engines S1D13513 S1D13513 16.0 MB 2.5 MB S1D13505 S1D13505 1.2 MB 16MB/64MB external SDRAM, VGA camera IF, 2D-engine, Sprite engine BGA, QFP , kB QVGA 24bpp - MOQ: 1kpcs - Projects with min. 5Kpcs will be supported for: - S1D13715 - EPSON
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S1D13506 S1D13743 S1D13719 S1D13700 S1D13706 S1D13714 s1d13748 s1d13742 27mhz toys s1d13717 S1D13748 S1D13742 S1D13717
Abstract: 18bpp and 24bpp color. The DS90C187 is offered in a small 92 pin dual row VQFN package and features , operation for single and dual pixel applications supporting either 24bpp or 18bpp color depths. In the Dual Pixel / 24bpp mode, eight LVDS data lines are provided along with two LVDS clock lines (8D+2C). The , its implementation. The Dual Pixel / 24bpp 8D+2C LVDS Interface Mapping is shown in Figure 15. A Dual , / 24bpp mode, four LVDS data lines are provided along with a LVDS clock line (4D+C). The 28 bit interface Texas Instruments
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ina26 t-con lvds 2560x2048 LVDS Serializer SNLS401B 105MH 185MH ISO/TS16949
Abstract: corrected. 2. 65545/65548. Switch to 24bpp mode was allowed when in Simultaneous/LCD display mode. This has been changed to allow 24bpp modes only when CRT display mode is selected. Revision: Release , window. 13. Fixed problem with 24bpp Transparent SRC/DST bitblt operations in Direct Draw. 14. Modified Chips and Technologies
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chips 65554 chips 65555 65545 64K-color chips 69000 DR655XX DR655
Abstract: link up to 1Mbps bandwidth - Support resolutions up to WQXGA (2560x1600, 60Hz, 24bpp) with pixel clock , No. ANX1122FN-AB-T ANX1123TN-AB-T Description DisplayPortTM to LVDS translator with 24-bpp LVDS , DisplayPortTM to LVDS translator with 24-bpp LVDS output DisplayPortTM to LVDS translator with 30-bpp LVDS Analogix Semiconductor
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ANX1123 ANX1122 ANX1121 HDMI to dp converter ic LVDS to vga converter ic ANX1120 analogix ANX1122 ANX1122/ 270MH ANX1122/1123
Abstract: 2MB SDRAM CRT mode: 1280 x 1024 @ 16bpp (60Hz), 1024 x 768 @16bpp (85Hz) 800 x 600 @ 24bpp (85Hz) LCD/Simultaneous mode: 1280 x 1024 @ 8bpp, 1024 x 768 @ 16bpp, 800 x 600 @ 24bpp Supports up to SXGA -
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SBC8360 SBC8360VEA AX8501 ES1938 69000 asiliant manual M-Systems diskonchip LCD Kit DSTN usb Blaster 10/100B RJ-45 PC/104 256MB 440BX
Abstract: -bit TFT and 16 or 24-bit DSTN panels up to 1280x1024 resolution VGA only: Up to 1280 x 1024 24bpp colors @ 60Hz Simultaneous mode: Up to 1024 x 768 24bpp colors @ 60Hz DualView mode: Display 1 up to Axiomtek
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AX12600 PCI104 SMI712EM 95/98/NT/2000 E112600101
Abstract: BPP 16 BPP, 24BPP) RC_BITBLT (0001h) RC_BANDING (0002h) RC_SCALING (0004h) RC_SAVEBITMAP (0040h) RC_PALETTE (0100h) (8 BPP) RC_DIBTODEV (0200h) , (8 BPP 16 BPP, 24BPP) RC_BIGFONT (0400h) , (8 BPP 16 BPP, 24BPP) RC_STRETCHBLT (0800h) , (8 BPP 16 BPP, 24BPP) RC_FLOODFILL (1000h) RC_STRETCHDIB (2000h) , (8 BPP 16 BPP, 24BPP) RC_DEVBITS (8000h) , (8 BPP 16 BPP, 24BPP) Level of Intel
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OpenGL 3D Accelerator graphics accelerator intercast polygon mirror RGB565 740TM MCDSRV32 OPENGL32 MCD32 GFX40
Abstract: Product Brief ANX1120AC Low Cost DisplayPortTM to LVDS Converter with Single / Dual Channel 24-bpp Output Features VESA Compliant DisplayPortTM 1.1a Receiver - Configurable 1 or 2 lane operation - 1.62 / 2.7Gbps data rate support - AUX channel link up to 1Mbps bandwidth - All DisplayPortTM receiver , converter with single / dual channel LVDS 24-bpp output (64 pin, 9x9 mm, QFN) ANX1120 Evaluation Kit , to LVDS translator DisplayPortTM to LVDS translator with 24-bpp LVDS output DisplayPortTM to LVDS Analogix Semiconductor
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AA-000453-PB ANX9832 ANX1120FN-AC-T DisplayPort LVDS Converter ANX9830 LVDS 30 pin to vga LVDS to DP 1.1a 205MH
Abstract: 1400 x 1050 @ 60 fps are supported with 24bpp in color depth. 18bpp may also be supported by a , interfaces with either 24bpp or 18bpp color depths. The DS90C185 provides four LVDS data lines along with an , L/R signaling or function as a general purpose bit. The single pixel 24bpp 4D+C LVDS interface , G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 DE VS HS GP Note LSB MSB 24bpp / MSB on CH3 DS90C187 Input , D10 D9 D8 D7 Note D6 D17 D16 D15 D14 D13 D12 D20 D19 D18 MSB 24bpp / LSB on CH3 DS90C187 Input Texas Instruments
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DAP D18 SQF48A
Abstract: . Displays up to 1400x1050 at 60 fps are supported with 24-bpp color depth. 18 bpp may also be supported by , 24bpp or 18bpp color depths. The DS90C185 provides four LVDS data lines along with an LVDS clock line , or function as a general purpose bit. The single pixel 24bpp 4D+C LVDS interface mapping is shown , / TCON device that is used to ensure compatible mapping for the application. Table 2. 24bpp / MSB on CH3 , '" FEBRUARY 2012 â'" REVISED FEBRUARY 2013 www.ti.com Table 2. 24bpp / MSB on CH3 (continued) DS90C187 Texas Instruments
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SNLS402D 75-MH 105-MH
Abstract: interface - 1 Port 2nd RMII or Camera (8bit) interface 24bpp RGB LCD Interface USB Host 2.0 - 1 Port , Camera (8bit) x 1 24bpp RGB LCD x 1 USB Host 2.0 x 1 USB OTG 2.0 x 1 I2S/SAI Audio x 1 I2C iWave Systems Technologies
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W-G16M-
Abstract: illustrates a Dual-Link 24 bpp application using Format 2, controlled by CHA_24BPP_FORMAT1 (CSR 0x18.1) and CHB_24BPP_FORMAT1 (CSR 0x18.0). In data Format 2, the two MSB per color are transferred on the Y3P/N , panel. This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to `1' and CHA_24BPP , disabled (default) 3 0x18 2 CHA_24BPP_MODE 0 ­ Force 18bpp; LVDS channel A lane 4 (A_Y3P/N) is disabled (default) 1 ­ Force 24bpp; LVDS channel B lane 4 (B_Y3P/N) is enabled CHB_24BPP_MODE 0 ­ Force 18bpp; LVDS Texas Instruments
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SN65DSI84 RGB666 RGB888
Abstract: . Figure 11 illustrates a Dual-Link 24 bpp application using Format 2, controlled by CHA_24BPP_FORMAT1 (CSR 0x18.1) and CHB_24BPP_FORMAT1 (CSR 0x18.0). In data Format 2, the two MSB per color are transferred on , transmission to an 18 bpp panel. This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to â'˜1â'™ and CHA_24BPP_MODE (CSR 0x18.3) to â'˜0â'™. In this configuration, the SN65DSI84 will not transmit Texas Instruments
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Abstract: Product Brief ANX3110 High Performance DisplayPortTM Converter with Single / DualLVDS 24bpp Output Features y VESA compliant DisplayPortTM 1.1a receiver 1lane (1.62Gbps) or 2lane(2.7Gbps) data rate operation AUX Channel link up to 1Mbps bandwidth eDP content protection y Low BoM cost, no local MCU required Fully controllable via DisplayPortTM through AUX channel y 24bpp Single or Dual channel LVDS output DualLVDS output up to WUXGA Analogix Semiconductor
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ANX9804 lvds to eDP DVI converter ANX9805 ANX9834 anx311
Abstract: YPbPr: 480i/p, 576i/p, 720p, 1080i Single-link DVI: 1600x1200 60Hz 24bpp Q2-08 Dual-link DVI: 2048x1536 60Hz 24bpp Single-link LVDS: 1280x1024 60Hz 24bpp Dual-link LVDS: 2048x1536 60Hz 24bpp HDMITM: 1920x1080i 60Hz 24bpp DVO: 220MHz pixel clk Q2-10 AMD Embedded Solutions, cont. AMD , /p Single-link DVI: 1600x1200 60Hz 24bpp Dual-link DVI: 2048x1536 60Hz 24bpp Q1-10 Single-link LVDS: 1280x1024 60Hz 24bpp Dual-link LVDS: 2048x1536 60Hz 24bpp DisplayPort 1.1a: 2560x1600 QuickLogic
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MIPI to RGB
Abstract: Entertainment (RSE) ­ Navigation Display ­ 18bpp or 24bpp Color Depth ­ WQVGA to XGA Support · WQVGA Resolution (400 X 240), 24bpp, ~6MHz · WVGA resolution (800 X 480), 18bpp or 24bpp, ~30MHz · DWVGA Resolution (1600 X 480), 18bpp or 24bpp, ~65MHz · XGA resolution (1024 X 768), 24bpp, ~65MHz 6 Color , ) ­ 18-bpp, 262k colors ­ 24-bpp, 16.7M colors (True) 8 ­ bits per pixel image 256 colors ­ , FPD-Link II / DS9OUR905/906 Enhancements! Full 24-bpp Color 5 to 65 MHz PCLK NEW SIGCON NEW Chips and Technologies
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386SX video overlay 150KB 300KB
Abstract: , controlled by CHA_24BPP_FORMAT1 (CSR 0x18.1) and CHB_24BPP_FORMAT1 (CSR 0x18.0). In data Format 2, the two , to 18 bpp data for transmission to an 18 bpp panel. This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to â'˜1â'™ and CHA_24BPP_MODE (CSR 0x18.3) to â'˜0â'™. In this configuration, the Texas Instruments
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LVDS to mipi bridge LVDS to MIPI DSI MIPI DSI to lvds LVDS to MIPI DSI Bridge temperature controller CHB 402 MIPI to LVDS bridge
Abstract: application. Figure 11 illustrates a Dual-Link 24 bpp application using Format 2, controlled by CHA_24BPP_FORMAT1 (CSR 0x18.1) and CHB_24BPP_FORMAT1 (CSR 0x18.0). In data Format 2, the two MSB per color are , transmission to an 18 bpp panel. This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to `1' and CHA_24BPP_MODE (CSR 0x18.3) to `0'. In this configuration, the SN65DSI85 will not transmit the Texas Instruments
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Abstract: application. Figure 11 illustrates a Single-Link 24 bpp application using Format 2, controlled by CHA_24BPP , . This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to â'˜1â'™ and CHA_24BPP QuickLogic
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lvds to mipi
Abstract: application. Figure 11 illustrates a Dual-Link 24 bpp application using Format 2, controlled by CHA_24BPP_FORMAT1 (CSR 0x18.1) and CHB_24BPP_FORMAT1 (CSR 0x18.0). In data Format 2, the two MSB per color are , transmission to an 18 bpp panel. This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to `1' and CHA_24BPP_MODE (CSR 0x18.3) to `0'. In this configuration, the SN65DSI84 will not transmit the , configuration; Channel A output enabled and Channel B output disabled (default) 3 0x18 2 CHA_24BPP_MODE 0 ­ Texas Instruments
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Abstract: application. Figure 11 illustrates a Dual-Link 24 bpp application using Format 2, controlled by CHA_24BPP_FORMAT1 (CSR 0x18.1) and CHB_24BPP_FORMAT1 (CSR 0x18.0). In data Format 2, the two MSB per color are , transmission to an 18 bpp panel. This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to `1' and CHA_24BPP_MODE (CSR 0x18.3) to `0'. In this configuration, the SN65DSI85 will not transmit the Texas Instruments
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SN65DSI83
Abstract: application. Figure 11 illustrates a Dual-Link 24 bpp application using Format 2, controlled by CHA_24BPP_FORMAT1 (CSR 0x18.1) and CHB_24BPP_FORMAT1 (CSR 0x18.0). In data Format 2, the two MSB per color are , transmission to an 18 bpp panel. This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to `1' and CHA_24BPP_MODE (CSR 0x18.3) to `0'. In this configuration, the SN65DSI84 will not transmit the , configuration; Channel A output enabled and Channel B output disabled (default) 3 0x18 2 CHA_24BPP_MODE 0 ­ Texas Instruments
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rgb888 to rgb666 RGB MIPI dsi DSI RGB Bridge display MIPI DSI version 1.01 RGB mipi bridge
Abstract: -layers + 16bit YUV x 1-layer + 24BPP x 1-layer 8BPP(L0-Layer) 16bit YUV(Video Capture, L1-Lyaer) 8BPP(L2-Layer) 24BPP(L3-Layer) Background Color Limitation Case 2 :16BPP x 1-layer + 16bit YUV x 1-layer + 24BPP x 1-layer 16BPP(L0-Layer) 16bit YUV(Video Capture, L1-Lyaer) 24BPP(L2-Layer) Background Color Texas Instruments
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MARKING 3D SOT-32 RGB TO MIPI DSI MHz MIPI
Abstract: 24 bpp application using Format 2, controlled by CHA_24BPP_FORMAT1 (CSR 0x18.1). In data Format 2 , setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to `1' and CHA_24BPP_MODE (CSR 0x18.3) to `0'. In this , VS is negative polarity driven `0' during corresponding sync (default) CHA_24BPP_MODE 0 ­ Force 18bpp; LVDS channel A lane 4 (A_Y3P/N) is disabled (default) 1 ­ Force 24bpp; LVDS channel A lane 4 (A_Y3P/N) is enabled CHA_24BPP_FORMAT1 This field selects the 24bpp data format 0 ­ LVDS channel A lane A_Y3P/N Texas Instruments
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mipi controller mipi DSI protocol MIPI DSI to RGB
Abstract: , controlled by CHA_24BPP_FORMAT1 (CSR 0x18.1) and CHB_24BPP_FORMAT1 (CSR 0x18.0). In data Format 2, the two , to 18 bpp data for transmission to an 18 bpp panel. This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to â'˜1â'™ and CHA_24BPP_MODE (CSR 0x18.3) to â'˜0â'™. In this configuration, the Texas Instruments
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MIPI dphy MIPI DSI 4 lane MIPI EMI Arasan mipi d-phy MIPI bridge
Abstract: a Dual-Link 24 bpp application using Format 2, controlled by CHA_24BPP_FORMAT1 (CSR 0x18.1) and CHB_24BPP , . This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to â'˜1â'™ and CHA_24BPP Texas Instruments
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