500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Direct from the Manufacturer

Part Manufacturer Description PDF & SAMPLES
ISL26134AVZ Intersil Corporation Low-Noise 24-bit Delta Sigma ADC; TSSOP28; Temp Range: -40° to 105°C
ISL26104AVZ Intersil Corporation Low-Noise 24-bit Delta Sigma ADC; TSSOP28; Temp Range: -40° to 105°C
ISL26104AVZ-T7A Intersil Corporation Low-Noise 24-bit Delta Sigma ADC; TSSOP28; Temp Range: -40° to 105°C
HI7190IBZ-T Intersil Corporation 24-Bit, High Precision, Sigma Delta A/D Converter; PDIP20, SOIC20; Temp Range: -40° to 85°C
HI7190IPZ Intersil Corporation 24-Bit, High Precision, Sigma Delta A/D Converter; PDIP20, SOIC20; Temp Range: -40° to 85°C
HI7190IBZ Intersil Corporation 24-Bit, High Precision, Sigma Delta A/D Converter; PDIP20, SOIC20; Temp Range: -40° to 85°C

Search Stock

Shift+Click on the column header for multi-column sorting 
Part
Manufacturer
Supplier
Stock
Best Price
Price Each
Ordering
Part : TR24BI-TINEL-LOCK-RING Supplier : TE Connectivity Manufacturer : Avnet Stock : - Best Price : $23.5045 Price Each : $33.4127
Part : TR24BI-TINEL-LOCK-RING Supplier : TE Connectivity Manufacturer : Heilind Electronics Stock : - Best Price : - Price Each : -
Part : TR24BI-TINEL-LOCK-RING Supplier : TE Connectivity Manufacturer : Interstate Connecting Components Stock : - Best Price : - Price Each : -
Part : TR24BI-TINEL-LOCK-RING Supplier : TE Connectivity Manufacturer : Master Electronics Stock : 1 Best Price : $22.45 Price Each : $29.52
Part : TR24BI-TINEL-LOCK-RING Supplier : TE Connectivity Manufacturer : Sager Stock : - Best Price : $27.47 Price Each : $36.83
Shipping cost not included. Currency conversions are estimated. 

24-bit

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: JTAG ID = $0180B01D Device ID (IDR) = $000321 JTAG ID = $0181501D Internal Memory 128 K × 24-bit on-chip SRAM 192 K × 24-bit on-chip SRAM Memory maps Memory map includes five switch options , memory 10 K × 24-bit 12 K × 24-bit SRAM access wait states Accesses as 100 MHz or less , Identification Register (IDR) is a 24-bit, read-only factory-programmed register that identifies DSP56300 family , Internal Memory Size The DSP56311 has a total of 128 K × 24-bit on-chip SRAM compared to a total of 192 K Motorola
Original
DSP56321 DSP56000 97Pb3Sn smd cod 62Sn-36Pb-2Ag omr 112 MFI3 MSW-01 EB365/D
Abstract: Preview DSP56321 24-BIT DIGITAL SIGNAL PROCESSOR The Motorola DSP56321, a member of the DSP56300 , shifter, 24-bit addressing, instruction cache, and Direct Memory Access (DMA) controller. The DSP56321 , Control 24-Bit Bootstrap ROM DSP56300 Core 18 Address 10 Control DDB Internal Data , fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit Motorola
Original
12 bit alu circuit design 32 bit barrel shifter circuit diagram dab circuitry MSW-2 DSP56321P/D
Abstract: DSP56307 Advance Information 24-BIT DIGITAL SIGNAL PROCESSOR Motorola developed the DSP56307, a , instruction engine (code compatible with Motorola's popular DSP56000 core family), a barrel shifter, 24-bit , EXTAL XTAL RESET PINIT/NMI YAB XAB PAB DAB Y Data RAM 24 K × 24 24-Bit DSP56300 Core , ) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter , 24-bit or 16-bit arithmetic support under software control Ð Program Control Unit (PCU) with Motorola
Original
DSP56000 DATASHEET 4 bit barrel shifter circuit diagram free home theater circuit diagram DSP56303 barrel shifter block diagram 8 BIT ALU design by cmos DSP56307P/D
Abstract: instruction engine (code compatible with Motorola's popular DSP56000 core family), a barrel shifter, 24-bit , XTAL RESET PINIT/NMI YAB XAB PAB DAB Y Data RAM 24 K × 24 24-Bit DSP56300 Core , Semiconductor, Inc. 24-BIT DIGITAL SIGNAL PROCESSOR Program Interrupt Controller PLL Program , parallel instruction set Ð Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit , stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support Motorola
Original
AA136 block diagram for barrel shifter
Abstract: Advance Information 24-BIT DIGITAL SIGNAL PROCESSOR DSP56307 Motorola developed the DSP56307, a , instruction engine (code compatible with Motorola's popular DSP56000 core family), a barrel shifter, 24-bit , Logic Unit (Data ALU) with fully pipelined 24 x 24-bit parallel Multiplier-Accumulator (MAC), 56 , instructions, and 24-bit or 16-bit arithmetic support under software control - Program Control Unit (PCU) with , total - Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable: 24 K x 24-bit -
OCR Scan
design of 18 x 16 barrel shifter design of barrel shifter 18 x 16 ir5b
Abstract: Advance Information 24-BIT DIGITAL SIGNAL PROCESSOR The DSP56303 is a member of the DSP56300 core family , External Address Bus Switch External Bus Interface 18 ADDRESS 24-Bit DSP56300 Core DDB YDB 13 , pipelined 24 x 24-bit parallel multiplier-accumulator 56-bit parallel barrel shifter 24-bit or 16 , disabled enabled Switch Mode disabled disabled enabled enabled Program RAM Size 4096 x 24-bit 3072 x 24-bit 2048 x 24-bit 1024 x 24-bit Instruction Cache Size 0 1024 x 24-bit 0 1024 x 24-bit X Data RAM Size 2048 -
OCR Scan
18 x 16 barrel shifter DSP56303P/D
Abstract: information specific to the DSP56311 Memory 64 K × 24-bit on-chip RAM 128 K × 24-bit on-chip RAM Internal Memory Block Size 256 × 24-bit words 1024 × 24-bit words 3 Voltage The DSP56311 and , Freescale Semiconductor 3 Memory The Device Identification register (IDR) is a 24-bit, read-only , information specific to the DSP56311. 11 Memory The DSP56311 has a total of 128 K × 24-bit on-chip RAM compared to the 64 K × 24-bit on-chip RAM of the DSP56307. In both devices, RAM is partitioned into Freescale Semiconductor
Original
EB344 DSP56L307 Freescale process
Abstract: DSP56311 24-BIT DIGITAL SIGNAL PROCESSOR The Motorola DSP56311, a member of the DSP56300 core family of , with Motorola's popular DSP56000 core family), a barrel shifter, 24-bit addressing, Instruction Cache , 24-Bit DSP56300 Core Bootstrap ROM Clock Generator X Data RAM 48 K × 24 YM_EB , ­ Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel , parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control Motorola
Original
DSP56000 motorola DSP56311P/D
Abstract: Freescale Semiconductor Product Brief DSP56311PB Rev. 3, 2/2005 DSP56311 24-Bit Digital , Data RAM 48 K × 24 bits 24-Bit DSP56300 Core Bootstrap ROM DDB YDB XDB PDB GDB , code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA , instruction set · Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel , parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control · Freescale Semiconductor
Original
DSP56300 finite impulse response DSP56300FM DSP56311UM
Abstract: Internal Memory 128 K × 24-bit on-chip SRAM 192 K × 24-bit on-chip SRAM Memory maps Memory map , default) EFCOP/Core shared 10 K × 24-bit memory 12 K × 24-bit SRAM access wait states , Identification Register Contents for DSP56311 and DSP56321 The device Identification Register (IDR) is a 24-bit , of 128 K × 24-bit on-chip SRAM compared to a total of 192 K × 24-bit on-chip SRAM in the DSP56321 , RAM Size* Instruction Cache (CE) Switch Mode (MS) MSW1 MSW0 32 K × 24-bit 0 Motorola
Original
Abstract: DSP56L307 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral , 24 bits 24-Bit DSP56300 Core Bootstrap ROM External Address Bus Switch External Bus , (DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory , ALU) with fully pipelined 24 × 24-bit parallel multiplier-accumulator (MAC), 56-bit parallel barrel , , and 24-bit or 16-bit arithmetic support under software control · Program control unit (PCU) with Freescale Semiconductor
Original
iir lms DSP56L307UM DSP56L307PB DSP56
Abstract: Advance Information 24-BIT DIGITAL SIGNAL PROCESSOR Motorola designed the ROM-based DSP56304 to support , Lock Loop (PLL), External Memory Interface (EMI), Data Arithmetic Logic Unit (Data ALU), 24-bit , 24-Bit DSP56300 Core Bootstrap ROM YM_EB ESSI Interface Program RAM 1024 × 24 , with the DSP56000 core ­ Highly parallel instruction set ­ Fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC) ­ 56-bit parallel barrel shifter ­ 24-bit or 16 Motorola
Original
9216 ROM ram expansion module RAM POWER DISTRIBUTION DIAGRAM DSP56304P/D
Abstract: specific to the DSP56311 Memory 64 K × 24-bit on-chip RAM 128 K × 24-bit on-chip RAM Internal Memory Block Size 3 JTAG and Device ID registers information specific to the DSP56307 256 × 24-bit words 1024 × 24-bit words Voltage The DSP56311 and DSP56307 are dual-voltage devices. The , Identification register (IDR) is a 24-bit, read-only factory-programmed register that identifies DSP56300 family , . 11 Memory The DSP56311 has a total of 128 K × 24-bit on-chip RAM compared to the 64 K × 24-bit Motorola
Original
12000-13FFF EB344/D
Abstract: Advance Information 24-BIT DIGITAL SIGNAL PROCESSOR The DSP56302 is a member of the DSP56300 core family , External Address Bus Switch External Bus Interface 18 ADD RESS 24-Bit DSP56300 Core DDB YDB 13 & , DSP56000 core Highly parallel instruction set Fully pipelined 24 x 24-bit parallel multiplier-accumulator 56-bit parallel barrel shifter 24-bit or 16-bit arithmetic support under software control Position , enabled Program RAM Size 20480 x 24-bit 19456 x 24-bit 25576 x 24-bit 24552 x 24-bit Instruction Cache -
OCR Scan
4 bit barrel shifter block diagram DSP56302P/D
Abstract: Conditional ALU instructions ­ · Fully pipelined 24 x 24-bit parallel multiplier-accumulator 24-bit , Switch Mode Program RAM Size Instruction Cache Size disabled disabled 4096 × 24-bit 0 2048 × 24-bit 2048 × 24-bit enabled disabled 3072 × 24-bit 1024 × 24-bit 2048 × 24-bit 2048 × 24-bit disabled enabled 2048 × 24-bit 0 3072 × 24-bit 3072 × 24-bit enabled enabled 1024 × 24-bit 1024 × 24-bit 3072 × 24-bit 3072 × 24-bit · X Data RAM Motorola
Original
digital lock using PIC DSP56303/D DSP56300FM/AD DSP56303UM/AD
Abstract: , rev. 1.08, July 1993 Features: â'¢ Preloadable 24-bit Up/Down Counter ° Choice of two 20 , '¢ Divide-by-N â'¢ 24-Bit Comparitor Register â'¢ 4 Control Registers â'¢ Readable Status Register â'¢ 8 , applications. The 24-bit multi-mode counter, registers and logic enable a micro­ processor to track the , Master Control Register b> Input Control Register Output Control Register L_> 24-bit , (206) 696-2468): : ?[ 24-bit Comparitor (800) 736-0194) LS7166 DIP package Price: $3.90 -
OCR Scan
Abstract: development. The 24-bit precision of the DSP56307 Digital Signal Processor (DSP) combined with the onboard 64K , Hardware · 24-bit DSP56307 Digital Signal Processor ­ High -Performance DSP56300 core Object , Logic Unit (ALU) · Fully pipelined 24-x 24-bit parallel multiplier-accumulator · 56-bit parallel barrel shifter · Conditional ALU instructions · 24-bit or 16-bit arithmetic support , Switch Mode MSW1 MSW0 16K × 24-bit 0 24K × 24-bit 24K × 24-bit disabled disabled 15K × 24-bit Motorola
Original
CS4218 MOTOROLA DSP563XX architecture CS4128 ssi RS-232 converter DSP56002 MIPS 24k processor motorola 16M CMOS DRAM DSP56307EVMP/D DSP56307EVM
Abstract: offers a complete portfolio of 16- and 24-bit fixed point and 32-bit floating point DSPs. In addition , DSP56000-24-Bit Digital Signal Processors The DSP56000 family of 24-bit, fixed point, general purpose , compatibility with the 24-bit family into the 16-bit DSP56100 and 32-bit DSP96002 products helping to preserve our customer software investment. The DSP56000 family of HCMOS, 24-bit DSP devices consists of the , , control, and audio applications. The DSP56000 family's unique 24-bit architecture has made these products Motorola
Original
XC56156FE60 XC56004FJ50 XC56001AFC27 XC96002RC40 XC56004 XC96002RC33 DSP56100--16-B DSP56800--16-B DSP56000--24-B DSP56300--24-B DSP56600--16-B DSP96002--32-B
Abstract: .2 . 2. Two Address Modes: 24-bit Address Mode and 32-bit Adress Mode , Flash Application in System Reset 1. Introduction MX25L25635E provides 24-bit and 32-bit address , will remain in 32-bit address mode and will not be able to boot by 24-bit addressing. This application note is designed specifically for those systems which can only be booted by 24-bit addressing but , solutions provided in this document, the Flash device can return to 24-bit addressing mode and boot Macronix International
Original
MX25L256 mx25l25635 mxic MX25L25 MXIC serial Flash an053 AN-053
Abstract: : 24-BIT DIGITAL SIGNAL PROCESSOR 24-Bit DSP56300 Core Bootstrap ROM External Address Bus , compatible with the DSP56000 core ­ Highly parallel instruction set ­ Fully pipelined 24 x 24-bit parallel multiplier-accumulator ­ 56-bit parallel barrel shifter ­ 24-bit or 16-bit arithmetic , disabled 4096 × 24-bit 0 2048 × 24-bit 2048 × 24-bit enabled disabled 3072 × 24-bit 1024 × 24-bit 2048 × 24-bit 2048 × 24-bit disabled enabled 2048 × 24-bit 0 3072 × Motorola
Original
DSP56303UM DSP56303PB/D
Abstract: 128 K × 24-bit on-chip SRAM 192 K × 24-bit on-chip SRAM Memory maps 9 Memory map includes , default) EFCOP/Core shared memory 10 10 K × 24-bit 12 K × 24-bit SRAM access wait states , DSP56311 and DSP56321 The device Identification Register (IDR) is a 24-bit, read-only factory-programmed , DSP56311 and DSP56321 8 Internal Memory Size The DSP56311 has a total of 128 K × 24-bit on-chip SRAM compared to a total of 192 K × 24-bit on-chip SRAM in the DSP56321. In both devices, SRAM is Freescale Semiconductor
Original
EB365 97Pb 62-SN
Abstract: Chapter 1 Overview This manual describes the DSP56311 24-bit digital signal processor (DSP), its , Motorola's popular DSP56000 core family), a barrel shifter, 24-bit addressing, instruction cache, and DMA , pipelined 24 24-bit parallel multiplier-accumulator s Bit field unit, comprising a 56-bit parallel , instructions s Software-controllable 24-bit, 48-bit, or 56-bit arithmetic support s Four 24-bit or , significant product:least significant product (EXT:MSP:LSP). The multiplier executes 24-bit 24-bit parallel -
Original
iir filter diagrams DSP56311/D
Abstract: specific to the DSP56311 Memory 64 K × 24-bit on-chip RAM 128 K × 24-bit on-chip RAM Internal Memory Block Size 3 JTAG and Device ID registers information specific to the DSP56307 256 × 24-bit words 1024 × 24-bit words Voltage The DSP56311 and DSP56307 are dual-voltage devices. The , Identification register (IDR) is a 24-bit, read-only factory-programmed register that identifies DSP56300 family , . 11 Memory The DSP56311 has a total of 128 K × 24-bit on-chip RAM compared to the 64 K × 24-bit Toshiba
Original
TC9446FG P-QFP100-1420-0 AD0-AD16
Abstract: barrel shifter, 24-bit addressing, an instruction cache, and direct memory access (DMA). The DSP56309 , RAM 7168 × 24 7168 × 24 YAB XAB PAB DAB Six Channel DMA Unit 24-Bit DSP56300 Core , 6 PM_EB 16 PIO_EB Freescale Semiconductor, Inc. 24-BIT GENERAL PURPOSE DIGITAL , stream generation and parsing) ­ Conditional ALU instructions ­ · Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC) ­ Freescale Semiconductor, Inc. ­ 24-bit or 16 Motorola
Original
Showing first 20 results.