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2/divider

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Abstract: ) CLOCK INPUT CLK IN 1 TEST OUTPUT TEST2 3 ONE-SHOT PULSE OUTPUT PULSE 4 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT FEATURES · 5V single power supply (5V ±5%) · , frequency as input clock, and its inversion (2) 1/2 divider clock output and its inversion (3) One-shot , DIVIDER SYNC CLOCK OUTPUT 6 CKO/2 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT 9 CNTCK CONTINUOUS , inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous clock ... Original
datasheet

5 pages,
59.44 Kb

M66236FP M66236 M66236FP abstract
datasheet frame
Abstract: ) CLOCK INPUT CLK IN 1 TEST OUTPUT TEST2 3 ONE-SHOT PULSE OUTPUT PULSE 4 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT FEATURES · 5V single power supply (5V ±5%) · , frequency as input clock, and its inversion (2) 1/2 divider clock output and its inversion (3) One-shot , OUTPUT 10 CKO SYNC CLOCK INVERTED OUTPUT 7 CKO/2 1/2 DIVIDER SYNC CLOCK OUTPUT 6 CKO/2 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT 9 CNTCK CONTINUOUS CLOCK OUTPUT 4 PULSE SYNC ... Original
datasheet

5 pages,
61.72 Kb

Pulse generator wiring diagram M66235FP M66235 M66235FP abstract
datasheet frame
Abstract: /2 divider clock output and its inversion (3) One-shot pulse output (4) Continuous clock output ♦ , TEST INPUT TEST OUTPUT ONE-SHOT PULSE OUTPUT iti DIVIDER Si NO CLOCK IIWERTEDOUTPUT 1/2 DIVIDER SYNC , DIVIDER SYNC CLOCK OUTPUT 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT CONTINUOUS CLOCK OUTPUT ONE-SHOT PULSE , inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous clock inverted , inverted output (CKO), inverted signal of sync clock output from CKO is output. From 1/2 divider ... OCR Scan
datasheet

6 pages,
1531.95 Kb

M66235FP M66235 ku band signal generator datasheet abstract
datasheet frame
Abstract: /2 divider clock output and its inversion (3) One-shot pulse output (4) Continuous clock output ♦ , TEST INPUT TEST OUTPUT ONE-SHOT PULSE OUTPUT 1® DWIDER SYNC CLOCK INSERTED OUTPUT 1/2 DIVIDER SYNC , DIVIDER SYNC CLOCK OUTPUT 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT CONTINUOUS CLOCK OUTPUT ONE-SHOT PULSE , ), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous , divider synchronous clock output (CKO/2), 1/2 divider signal of sync clock output from CKO is output. From ... OCR Scan
datasheet

6 pages,
1535.95 Kb

M66236FP M66236 datasheet abstract
datasheet frame
Abstract: input clock, and its in version (2) 1/2 divider clock output and its inversion (3) One-shot pulse output , noise killer circuit E -S H O T P U L S E p . . . , p OUTPUT r U L o b r G N D 1/2 DIVIDER SYNC , DELAY CLOCK GENERATION CIRCUIT PULSE SYNC CLOCK O UTPUT SYNC CLOCK INVERTED OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT o CONTINUOUS CLOCK OUTPUT ONE-SHO T PULSE , ), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous ... OCR Scan
datasheet

5 pages,
101.84 Kb

M66236FP M66236FP abstract
datasheet frame
Abstract: frequency as input clock, and its in version (2) 1/2 divider clock output and its inversion (3) One-shot , by built-in noise killer circuit 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT 1 /2 D IV ID E R S Y N C C , OUTPUT SYNC CLOCK INVERTED OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT , ), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous , output from CKO is output. From 1/2 divider synchro nous clock output (CKO/2), 1/2 divider signal of sync ... OCR Scan
datasheet

5 pages,
101.83 Kb

M66235FP M66235FP abstract
datasheet frame
Abstract: (2) 1/2 divider clock output and its inversion (3) One-shot pulse output (4) Continuous clock output , ) open. BLOCK DIAGRAM Vcc Vcc SYNC CLOCK OUTPUT SYNC CLOCK INVERTED OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT CONTINUOUS CLOCK OUTPUT CLOCK INPUT r|K |N . C L K IN ' ! ' , outputs: synchronous clock output (CKO), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous clock inverted output (CKO/2), one-shot pulse output ... OCR Scan
datasheet

5 pages,
143.56 Kb

M66236FP M66236 M66236FP abstract
datasheet frame
Abstract: (2) 1/2 divider clock output and its inversion (3) One-shot pulse output (4) Continuous clock output , O U S C LO C K O U TPU T \ n DIVIDER SYNC CLOCK i- t INVEfiTCD OUTPUT C K O /2 4 - L £ . 1/2 D , CLOCK O U TPU T 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT C NTCK CLOCK INPUT CLK IN t l DELAY CLOCK , of outputs: synchronous clock output (CKO), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous clock inverted output (CKO/2), one-shot pulse output ... OCR Scan
datasheet

5 pages,
144.81 Kb

M66235FP M66235 M66235FP abstract
datasheet frame
Abstract: ): ±3ns · Output types (1) Output of the same frequency as input clock, and its in version (2) 1/2 divider , TEST2 , SYNC CLO CK INVERTED O U TPUT ) CKO/2 ) CKO/2 (C N TC K I PULSE 1/2 DIVIDER SYNC CLO CK OUTPUT 1/2 , ), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous c lo c k in ve rte d outp u t , divider synchro nous clock output (CKO/2), 1/2 divider signal of sync clock output from CKO is output. ... OCR Scan
datasheet

6 pages,
1280.51 Kb

m66235 datasheet abstract
datasheet frame
Abstract: in version (2) 1/2 divider clock output and its inversion (3) One-shot pulse output (4) Continuous , INVERTED OUTPUT 1/2 DIVIDER SYNC CLO CK OUTPUT 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT CO NTINUO US CLO CK , clock output (CKO), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous c lo c k in ve rte d ou tp u t (C K O /2 ), o n e -s h o t p u lse output , signal ol sync clock output from CKO is output. From 1/2 divider synchro nous clock output (CKO/2), 1 ... OCR Scan
datasheet

6 pages,
1283.65 Kb

m66236 datasheet abstract
datasheet frame

Datasheet Content (non pdf)

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SY10/100EP32V SY10/100EP32V SY10/100EP32V SY10/100EP32V 5V/3.3V ÷ 2 Divider General Description Features The SY10/100EP32V SY10/100EP32V SY10/100EP32V SY10/100EP32V is an integrated ÷2 divider with differential clock inputs. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias
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SY10/100EL32V SY10/100EL32V SY10/100EL32V SY10/100EL32V 5V/3.3V ÷ 2 DIVIDER General Description The SY10/100EL32V SY10/100EL32V SY10/100EL32V SY10/100EL32V are integrated ÷2 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01mF capacitor. Also note that the VBB is designed to
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Simultaneous output. (1/1, 1/2, 1/4, 1/8 and 1/16 output frequency ratio). Builtin cylindrical-type AT-cut crystal unit assures high reliability. DIP 14-pin plastic package allows automatic mounting. External clock select function, dividing circuit reset function and 1/2 divider select function. Oscillation source frequency: 17.7340MHz to 40.000MHz.
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Spezial Electronic 11/08/1998 0.35 Kb TXT mg-3020.txt
Simultaneous output. (1/1, 1/2, 1/4, 1/8 and 1/16 output frequency ratio). Builtin cylindrical-type AT-cut crystal unit assures high reliability. DIP 14-pin plastic package allows automatic mounting. External clock select function, dividing circuit reset function and 1/2 divider select function. Oscillation source frequency: 17.7340MHz to 40.000MHz.
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Design Elektronik 11/08/1998 0.35 Kb TXT mg-3020.txt
) SY10/100EL32V SY10/100EL32V SY10/100EL32V SY10/100EL32V 5V/3.3V ÷ 2 Divider SY10/100EL33/L SY10/100EL33/L SY10/100EL33/L SY10/100EL33/L 5V/3.3V ÷ 4 Divider SY10/100EL34/L SY10/100EL34/L SY10/100EL34/L SY10/100EL34/L 5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip SY10/100EL38/L SY10/100EL38/L SY10/100EL38/L SY10/100EL38/L 5V/3.3V ÷2, ÷4/6 Clock Generation Chip SY10/100EP32V SY10/100EP32V SY10/100EP32V SY10/100EP32V 5V/3.3V ÷ 2 Divider SY10/100EP33V SY10/100EP33V SY10/100EP33V SY10/100EP33V 5V/3.3V ÷ 4 Divider SY100S834/L SY100S834/L SY100S834/L SY100S834/L 5V/3.3V (÷1,÷2,÷4) or (÷2,÷4,÷8) Clock Gen. Chip SY100S838/L SY100S838/L SY100S838/L SY100S838/L
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) SY10/100EL32V SY10/100EL32V SY10/100EL32V SY10/100EL32V 5V/3.3V ÷ 2 Divider SY10/100EL33/L SY10/100EL33/L SY10/100EL33/L SY10/100EL33/L 5V/3.3V ÷ 4 Divider SY10/100EL34/L SY10/100EL34/L SY10/100EL34/L SY10/100EL34/L 5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip SY10/100EL38/L SY10/100EL38/L SY10/100EL38/L SY10/100EL38/L 5V/3.3V ÷2, ÷4/6 Clock Generation Chip SY10/100EP32V SY10/100EP32V SY10/100EP32V SY10/100EP32V 5V/3.3V ÷ 2 Divider SY10/100EP33V SY10/100EP33V SY10/100EP33V SY10/100EP33V 5V/3.3V ÷ 4 Divider SY100S834/L SY100S834/L SY100S834/L SY100S834/L 5V/3.3V (÷1,÷2,÷4) or (÷2,÷4,÷8) Clock Gen. Chip SY100S838/L SY100S838/L SY100S838/L SY100S838/L
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OUT Div 1/2/4/8, and Div 2/4/8/16 Clock Divider MC100EP139 MC100EP139 MC100EP139 MC100EP139 3.3V / 5V ECL ÷2/4, ÷4/5/6 Clock Generation Chip MC100LVEP34 MC100LVEP34 MC100LVEP34 MC100LVEP34 2.5V ECL ÷2 Divider MC100EP33 MC100EP33 MC100EP33 MC100EP33 3.3V / 5V ECL ÷4 Divider NB7L32M NB7L32M NB7L32M NB7L32M 2.5V / 3.3V 12GHz Divide by 2 with CML Output NB6L239 NB6L239 NB6L239 NB6L239 2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT Dual Bank Divide by 1/2/4/8 and 2/4
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SY10/100EP32V SY10/100EP32V SY10/100EP32V SY10/100EP32V 5V/3.3V ÷ 2 Divider SY10/100EP33V SY10/100EP33V SY10/100EP33V SY10/100EP33V 5V/3.3V ÷ 4 Divider SY10/100EP58V SY10/100EP58V SY10/100EP58V SY10/100EP58V 3.3V/5V 3GHz PECL/ECL 2:1 Multiplexer SY10/100EL32V SY10/100EL32V SY10/100EL32V SY10/100EL32V 5V/3.3V ÷2 Divider SY10/100EL33/L SY10/100EL33/L SY10/100EL33/L SY10/100EL33/L 5V/3.3V ÷4 Divider SY10/100EL34/L SY10/100EL34/L SY10/100EL34/L SY10/100EL34/L 5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip SY10EP08V SY10EP08V SY10EP08V SY10EP08V Differential 2-Input XOR/XNOR SY10EP16V SY10EP16V SY10EP16V SY10EP16V High-Speed
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SY10/100EP32V SY10/100EP32V SY10/100EP32V SY10/100EP32V 5V/3.3V ÷ 2 Divider SY10/100EP33V SY10/100EP33V SY10/100EP33V SY10/100EP33V 5V/3.3V ÷ 4 Divider SY10/100EP58V SY10/100EP58V SY10/100EP58V SY10/100EP58V 3.3V/5V 3GHz PECL/ECL 2:1 Multiplexer Flip-Flop with Set and Reset SY10/100EL32V SY10/100EL32V SY10/100EL32V SY10/100EL32V 5V/3.3V ÷2 Divider SY10/100EL33/L SY10/100EL33/L SY10/100EL33/L SY10/100EL33/L 5V/3.3V ÷4 Divider SY10/100EL34/L SY10/100EL34/L SY10/100EL34/L SY10/100EL34/L 5V/3.3V ÷2, ÷4 SY10EP08V SY10EP08V SY10EP08V SY10EP08V Differential 2-Input XOR/XNOR SY10EP16V SY10EP16V SY10EP16V SY10EP16V High-Speed
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with Accurate VDDQ/2 Divider Reference Glitch-free Transitions During State Changes ACPI Compliant ISL6532BCR ISL6532BCR ISL6532BCR ISL6532BCR Active Comm 20 Ld QFN 2 2.94 ISL6532BCR-T ISL6532BCR-T ISL6532BCR-T ISL6532BCR-T Active Comm 20 Ld QFN T+R 2 2.94 ISL6532BCRZ ISL6532BCRZ ISL6532BCRZ ISL6532BCRZ Active Comm 20 Ld QFN 3 2.95 ISL6532BCRZ-T ISL6532BCRZ-T ISL6532BCRZ-T ISL6532BCRZ-T S3 state. During Run mode, a fully integrated sink-source regulator generates an accurate (VDDQ/2) high current VTT voltage without the need for a negative supply. A buffered version of the VDDQ/2
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