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2/divider

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Abstract: divider has eight settings of 1, 2, 4, 5, 6, 7, 8, and 10; giving a maximum total divide of 5190. The A , A6:A0 7 VDD 2 INA Divider A (7-Bit) OUTA INB Divider B (9-Bit) 3 Post Divider , output. Divider A output. IDTTM / ICSTM USER CONFIGURABLE DIVIDER 2 ICS674-01 ICS674-01 REV E 082305 , Word (DBW) = 4 to 511 (0, 1, 2, 3 are not permitted) Post Divider (PD) = values on page 2 For , /2)+1 VDD/2 VDD/2 2.4 0.4 3 5 (VDD/2)-1 IDTTM / ICSTM USER CONFIGURABLE DIVIDER 5 ICS674 ICS674 ... Integrated Device Technology
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8 pages,
142.88 Kb

ICS674-01 ICS673 TEXT
datasheet frame
Abstract: divide by 12 to 519. The post divider has eight settings of 1, 2, 4, 5, 6, 7, 8, and 10; giving a , Diagram A6:A0 VDD 7 INA Divider A (7-Bit) INB 2 Divider B (9-Bit) 9 B8:B0 , Post Divider Table A5 1 28 A4 2 27 A3 S2 Pin 5 S1 Pin 4 S0 Pin 3 , Pin Number Pin Name Pin Type 1, 2, 24 - 28 A5, A6, A0-A4 Input Divider A word , output. IDTTM / ICSTM USER CONFIGURABLE DIVIDER Pin Description 2 ICS674-01 ICS674-01 REV G 110409 ... Integrated Device Technology
Original
datasheet

8 pages,
95.67 Kb

ICS674-01 ICS673-01 TEXT
datasheet frame
Abstract: divider has eight settings of 1, 2, 4, 5, 6, 7, 8, and 10; giving a maximum total divide of 5190. The A , V ICS674-01 ICS674-01 Block Diagram A6:A0 7 VDD 2 INA Divider A (7-Bit) OUTA INB , details. Divider B output. Divider A output. MDS 674-01 E Integrated Ci rcu it Systems l 2 525 Ra , o m ICS674-01 ICS674-01 IDTTM / ICSTM USER CONFIGURABLE DIVIDER 2 ICS674-01 ICS674-01 ICS674-01 ICS674-01 USER , Word (DBW) = 4 to 511 (0, 1, 2, 3 are not permitted) Post Divider (PD) = values on page 2 For example ... Integrated Device Technology
Original
datasheet

8 pages,
259.25 Kb

ICS674-01 ICS673 TEXT
datasheet frame
Abstract: divider has eight settings of 1, 2, 4, 5, 6, 7, 8, and 10; giving a maximum total divide of 5190. The A , A6:A0 7 VDD 2 INA Divider A (7-Bit) OUTA INB Divider B (9-Bit) 3 Post Divider , output. Divider A output. IDTTM / ICSTM USER CONFIGURABLE DIVIDER 2 ICS674-01 ICS674-01 REV E 082305 , Word (DBW) = 4 to 511 (0, 1, 2, 3 are not permitted) Post Divider (PD) = values on page 2 For , mA (VDD/2)+1 VDD/2 VDD/2 2.4 0.4 3 5 (VDD/2)-1 IDTTM / ICSTM USER CONFIGURABLE DIVIDER 5 ... Integrated Device Technology
Original
datasheet

8 pages,
137.51 Kb

ICS674-01 674R-01 ICS673 TEXT
datasheet frame
Abstract: divider has eight settings of 1, 2, 4, 5, 6, 7, 8, and 10; giving a maximum total divide of 5190. The A , A6:A0 7 VDD 2 INA Divider A (7-Bit) OUTA INB Divider B (9-Bit) 3 Post Divider , output. Divider A output. IDTTM / ICSTM USER CONFIGURABLE DIVIDER 2 ICS674-01 ICS674-01 REV F 090709 , Word (DBW) = 4 to 511 (0, 1, 2, 3 are not permitted) Post Divider (PD) = values on page 2 For , /2)+1 VDD/2 VDD/2 2.4 0.4 3 5 (VDD/2)-1 IDTTM / ICSTM USER CONFIGURABLE DIVIDER 5 ICS674 ICS674 ... Integrated Device Technology
Original
datasheet

8 pages,
70.91 Kb

ICS674-01 ICS673 TEXT
datasheet frame
Abstract: frequency range : 5 ~ 15 MHz Reference divider range : 2 ~ 33 (5-bit programmable divider) Feedback divider range : 2 ~ 257 (8-bit programmable divider) Dual Power supplies 1.8V/3.3V is required. Maximum , . 3V BPNR FIN R PD F Reference Divider R+2 Bandgap Reference M ux , Filter Feedback Divider F+2 Divider 1/2 OEB FOUT M ux BP OD @2003 Hynix , Output 1/2 divider enable BPNR INPUT Input divider bypass R4 INPUT Input 5-bit divider ... Hynix Semiconductor
Original
datasheet

7 pages,
259.18 Kb

H18GPL21M TEXT
datasheet frame
Abstract: frequency range : 5 ~ 15 MHz Reference divider range : 2 ~ 33 (5-bit programmable divider) Feedback divider range : 2 ~ 257 (8-bit programmable divider) Dual Power supplies 1.8V/3.3V is required. Maximum , . 3V BPNR FIN R PD F Reference Divider R+2 Bandgap Reference M ux , Filter Feedback Divider F+2 Divider 1/2 OEB FOUT M ux BP OD @2003 Hynix , 1/2 divider enable BPNR INPUT Input divider bypass R4 INPUT Input 5-bit divider ... Hynix Semiconductor
Original
datasheet

7 pages,
259.18 Kb

H18GPL21M TEXT
datasheet frame
Abstract: divide by 12 to 519. The post divider has eight settings of 1, 2, 4, 5, 6, 7, 8, and 10; giving a , voltage of 3.3 V or 5 V Block Diagram A6:A0 VDD 7 INA Divider A (7-Bit) INB 2 , CLOCK DIVIDER Pin Assignment Post Divider Table A5 1 28 A4 2 27 A3 S2 Pin , OUTA Output Divider A output. IDTTM / ICSTM USER CONFIGURABLE DIVIDER Pin Description 2 , following equations: Divide A = DAW + 2 Where Divider A Word (DAW) = 1 to 127 (0 is not permitted ... Integrated Device Technology
Original
datasheet

8 pages,
92.24 Kb

ICS674-01 ICS673-01 TEXT
datasheet frame
Abstract: . . . . . 2 I2C Frequency Divider Register (I2CFDR/I2CnFDR) 2 Determining the Frequency Divider . , sampling rate and the frequency divider ratio. 2 I2C Frequency Divider Register (I2CFDR/I2CnFDR , for SCL, Rev. 5 2 Freescale Semiconductor I2C Frequency Divider Register (I2CFDR/I2CnFDR , Devices Bit Values FDR Bit Locations Divider Group A Bits 5, 1, 0 for MPC824x devices Bits 2 , Locations Divider Group A Bits 5, 1, 0 for MPC824x devices Bits 2, 6, 7 for MPC83xx, MPC85xx, and ... Freescale Semiconductor
Original
datasheet

20 pages,
503.12 Kb

0B10000 MPC8568 MPC85xx MPC8610 MPC8641 p2020 MPC83xx p2020 processor registers MPC8544 MPC86xx AN2919 TEXT
datasheet frame
Abstract: PRELIMINARY INFORMATION ICS674-01 ICS674-01 User Configurable Divider Description Features The ICS674-01 ICS674-01 consists of 2 separate configurable dividers. The A Divider is a 7 bit divider and can divide , divider can divide by 12 to 519. The post divider has eight settings of 1, 2, 4, 5, 6, 7, 8 and 10 , ICS674-01 ICS674-01 can be determined by the following simple equations: Divide A = DAW+2 Where Divider A Word , 511 (0,1,2,3, are not permitted). Post Divider (PD) = values on Page 2 For example, suppose Divide ... Integrated Circuit Systems
Original
datasheet

6 pages,
51.69 Kb

ICS674R-01T ICS674R-01IT ICS674R-01I ICS674R-01 ICS674-01 ICS673-01 TEXT
datasheet frame
Abstract: frequency as input clock, and its in version (2) 1/2 divider clock output and its inversion (3) One-shot , by built-in noise killer circuit 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT 1 /2 D IV ID E R S Y N C C , OUTPUT SYNC CLOCK INVERTED OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT , ), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous , output from CKO is output. From 1/2 divider synchro nous clock output (CKO/2), 1/2 divider signal of sync ... OCR Scan
datasheet

5 pages,
101.83 Kb

M66235FP TEXT
datasheet frame
Abstract: (2) 1/2 divider clock output and its inversion (3) One-shot pulse output (4) Continuous clock output , CLOCK O U TPU T 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT C NTCK CLOCK INPUT CLK IN t l DELAY CLOCK , types of outputs: synchronous clock output (CKO), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous clock inverted output (CKO/2), one-shot pulse output , sync clock output from CKO is output. From 1/2 divider synchro nous clock output (CKO/2), 1/2 ... OCR Scan
datasheet

5 pages,
144.81 Kb

M66235FP M66235 TEXT
datasheet frame
Abstract: (2) 1/2 divider clock output and its inversion (3) One-shot pulse output (4) Continuous clock output , ) open. BLOCK DIAGRAM Vcc Vcc SYNC CLOCK OUTPUT SYNC CLOCK INVERTED OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT CONTINUOUS CLOCK OUTPUT CLOCK INPUT r|K |N . C L K IN ' ! ' , outputs: synchronous clock output (CKO), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous clock inverted output (CKO/2), one-shot pulse output ... OCR Scan
datasheet

5 pages,
143.56 Kb

M66236FP M66236 TEXT
datasheet frame
Abstract: its inversion (2) 1/2 divider clock output and its inversion (3) One-shot pulse output (4 , 1/2 DIVIDER SYNC CLOCK OUTPUT OLKIN->fT testi ->nr TEST2 , CLOCK OUTPUT SYNC CLOCK INVERTED OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT 1/2 DIVIDER SYNC CLOCK INVERTED , : synchronous clock output (CKO), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous clock inverted output (CKO/2), one-shot pulse output (PULSE) and ... OCR Scan
datasheet

6 pages,
1531.95 Kb

M66235FP M66235 ku band signal generator TEXT
datasheet frame
Abstract: ) CLOCK INPUT CLK IN 1 TEST OUTPUT TEST2 3 ONE-SHOT PULSE OUTPUT PULSE 4 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT FEATURES · 5V single power supply (5V ±5%) · , frequency as input clock, and its inversion (2) 1/2 divider clock output and its inversion (3) One-shot , DIVIDER SYNC CLOCK OUTPUT 6 CKO/2 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT 9 CNTCK CONTINUOUS , inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous clock ... Mitsubishi
Original
datasheet

5 pages,
59.44 Kb

M66236FP M66236 TEXT
datasheet frame
Abstract: ) CLOCK INPUT CLK IN 1 TEST OUTPUT TEST2 3 ONE-SHOT PULSE OUTPUT PULSE 4 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT FEATURES · 5V single power supply (5V ±5%) · , frequency as input clock, and its inversion (2) 1/2 divider clock output and its inversion (3) One-shot , OUTPUT 10 CKO SYNC CLOCK INVERTED OUTPUT 7 CKO/2 1/2 DIVIDER SYNC CLOCK OUTPUT 6 CKO/2 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT 9 CNTCK CONTINUOUS CLOCK OUTPUT 4 PULSE SYNC ... Mitsubishi
Original
datasheet

5 pages,
61.72 Kb

Pulse generator wiring diagram M66235FP M66235 TEXT
datasheet frame
Abstract: in­ version (2) 1/2 divider clock output and its inversion (3) One-shot pulse output (4 , ) CKO/2 1/2 DIVID ER SYNC CLOCK O U TP U T ) CKO/2 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT , output (CKO), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous clock inverted output (CKO/2), one-shot pulse output (PULSE) and continuous , clock output from CKO is output. From 1/2 divider synchro­ nous clock output (CKO/2), 1/2 divider ... OCR Scan
datasheet

5 pages,
108.78 Kb

M66235FP TEXT
datasheet frame
Abstract: its inversion (2) 1/2 divider clock output and its inversion (3) One-shot pulse output (4 , OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT clkin^E TESTI ->Q[ TEST2 , SYNC CLOCK INVERTED OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT , outputs: synchronous clock output (CKO), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous clock inverted output (CKO/2), one-shot pulse output ... OCR Scan
datasheet

6 pages,
1535.95 Kb

M66236FP M66236 TEXT
datasheet frame
Abstract: ): ±3ns · Output types (1) Output of the same frequency as input clock, and its in version (2) 1/2 divider , TEST2 , SYNC CLO CK INVERTED O U TPUT ) CKO/2 ) CKO/2 (C N TC K I PULSE 1/2 DIVIDER SYNC CLO CK OUTPUT 1/2 , ), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous c lo c k in ve rte d outp u t , divider synchro nous clock output (CKO/2), 1/2 divider signal of sync clock output from CKO is output ... OCR Scan
datasheet

6 pages,
1280.51 Kb

m66235 TEXT
datasheet frame
Abstract: in version (2) 1/2 divider clock output and its inversion (3) One-shot pulse output (4) Continuous , INVERTED OUTPUT 1/2 DIVIDER SYNC CLO CK OUTPUT 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT CO NTINUO US CLO CK , clock output (CKO), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous c lo c k in ve rte d ou tp u t (C K O /2 ), o n e -s h o t p u lse output , signal ol sync clock output from CKO is output. From 1/2 divider synchro nous clock output (CKO/2), 1 ... OCR Scan
datasheet

6 pages,
1283.65 Kb

m66236 TEXT
datasheet frame

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