NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| Part | Manufacturer | Description | Type | Ordering |
| 13NS360056 | N/A | NS Series 240 - 960 Watt Power Supply Unit |
5 pages, |
Scan | |
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: x 124 112 140 13ns ... | OCR Scan |
1 pages, |
S020G ECIS020M ECIS020L ECIS020J ECICM500 CM600 eel -16-2005 datasheet abstract |
| Abstract: utilizes exemption 7a. Single-ended (1 delay element) Time delays of 0.1ns to 1.3ns Tolerances as , ~ 1.3nS 0.250 max. (DJ) Schematic: Marking: Product marking will be composed of the , 0.9ns ~ 1.3ns Product Height (inches) 0.250" 0.250" Time delay increments 0.05ns steps , (0.1ns to 1.0ns) 1.0 /ns max. (1.1ns to 1.3ns) DC Resistance Typical Rise Time (20-80% max. , 0.6ns = 80ps 1.3ns = 140ps 0.1ns = 3.5 GHz 0.5ns = 3.5 GHz 0.6ns = 3.5 GHz 1.3ns = 2.4 GHz ... | Original |
2 pages, |
datasheet abstract |
| Abstract: Time delay values: 0.1 to 0.8ns: 0.05ns steps 0.9 to 1.3ns: 0.10ns steps Above 1.3ns: in development - call factory Time delay tolerance 0.1 to 0.8ns: �ps 0.9 to 1.3ns: �ps DC Resistance: 0.1 , time: (20-80% max) 0.1ns: 75ps 0.5ns: 80ps 0.6ns: 80ps 1.3ns: 140ps Other values: in , 1.3ns: 2.4 GHz Other values: in development - call factory Rated current: 100mA Temp. coef. of Td ... | Original |
3 pages, |
datasheet abstract |
| Abstract: Non-Inverting 6A 1.5 12ns/13ns into 2500pF 45ns/50ns into 2,500pF 4.5V to 20V EPAD-SOIC-8, MLF-8 , 13ns/15ns into 1000pF 37ns/40ns into 1000pF 4.5V to 20V EPAD-SOIC-8, EPAD-MSOP-8, MLF-8 (3x3mm , ) Low-Side Driver Dual Non-Inverting 1.5A 6 13ns/15ns into 1000pF 37ns/40ns into 1000pF 4.5V to , 1.5A 6 13ns/15ns into 1000pF 37ns/40ns into 1000pF 4.5V to 20V EPAD-SOIC-8, EPAD-MSOP-8 , MIC4129 MIC4129(2) Low-Side Driver Single Inverting 6A 1.5 12ns/13ns into 2500pF 45ns/50ns into 2 ... | Original |
2 pages, |
MIC4102 MIC4101 MIC4100 high speed mosfet driver hex latch MIC4424 MIC4425 MIC4426 Peak Low-Side MOSFET Driver p-channel mosfet driver MIC4452A MOSFET DRIVER circuits MIC4429 mosfet driver MIC4100 abstract |
| Abstract: VDD Max. VDD = +1.8V 3mA Typ. 4mA Typ. 5mA Typ. 6mA Typ. 1.3nS Typ. 1.3nS Typ. 3mS Typ. ... | Original |
1 pages, |
25PPM datasheet abstract |
| Abstract: 12ns 13ns 32ns 35ns 40ns 121ns 136ns 151ns 35ns 40ns 45ns 2.5mA 2.5mA 2.5mA 75mA 70mA 65mA 4.4ms 4.4ms , 12ns 13ns 32ns 35ns 40ns 121ns 136ns 151ns 37ns 41ns 46ns 2.5mA 2.5mA 2.5mA 75mA 70mA 65mA 4.4ms 4.4ms ... | OCR Scan |
1 pages, |
AAA280XX datasheet abstract |
| Abstract: ±50ps 1.3ns ±50ps ±100ppm/°C 1.4ns ±50ps 50 ±10% 1.5ns ±50ps 1.6ns ±50ps 1.7ns ±50ps 1.8ns ±50ps , FDD9005 FDD9005 9.0ns ±0.5ns 1.3ns 300MHz E,S,T FDD9505 FDD9505 9.5ns ±0.5ns 1.3ns 250MHz E,S,T FDD10005 FDD10005 10.0ns , 300MHz E,S,T FDD9010 FDD9010 9.0ns ±0.5ns 1.3ns 300MHz E,S,T FDD9510 FDD9510 9.5ns ±0.5ns 1.3ns 250MHz E,S,T , 83MHz E,S,T FDD25010 FDD25010 25.0ns ±1.3ns 3.7ns 80MHz E,S,T FDD27010 FDD27010 27.0ns ±1.4ns 4.0ns 74MHz E,S,T ... | Original |
15 pages, |
FDD8005 FDC0105 FDC0205 FDC02505 FDC0305 FDC03505 FDC0405 FDC04505 FDC00505 FDD11005 FDC2405 FDC3010 FDC50 FDD7005 FDD15005 100KH 100KH abstract |
| Abstract: CS# Active Hold Time tCHSH 5ns(min.) 5ns(min.) 5ns(min.) 13ns(min.) 13ns(min.) 9us (typ , Active Hold Time tCHSH 5ns(min.) 5ns(min.) 5ns(min.) 13ns(min.) 13ns(min.) 9us (typ) ; 300us ... | Original |
9 pages, |
REMS 88us mxic xtrarom MX25L512C MX25L1006E MX25L1006 MX25L512E MX25L512 mx25l1005 MX25L512/512C MX25L1005/1005C MX25L512/MX25L512C MX25L1005/MX25L1005C MX25L512E abstract |
| Abstract: DSASW00248335 33MHz: 13ns 104MHz: 4.5ns 50MHz: 9ns 86MHz: 5.5ns 33MHz: 13ns tCL 86MHz: 5.5ns 33MHz: 13ns 104MHz: 4.5ns 50MHz: 9ns 86MHz: 5.5ns 33MHz: 13ns Byte 9us(typ.) ; 300us(max. ... | Original |
10 pages, |
rdid AN-069 MXIC serial Flash AN069 WSON* 8x6mm mxic Macronix MX25L6405 8x6mm MX25L6445E application note data mx25L6406E mxic mx25l6406e MX25L6406 MX25L6445* input id MX25L6406E MX25L6405D MX25L6406E abstract |
| Abstract: PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74157 13ns 30mA 74LS157 74LS157 13ns 9.7mA 74S157 74S157 7.4ns 50mA 74158 13ns 30mA 74LS158 74LS158 13ns 4.8mA 74S158 74S158 6ns 40mA ORDERING CODE PACKAGES COMMERCIAL RANGES VCC = ... | OCR Scan |
5 pages, |
N74S157N 74LS158 74LS157 74157 ttl LS157 TTL 74158 IC 74LS 190s multiplexor 74157 pin diagram multiplexer 74157 74157 ic IC 74LS157 74158 74157 pin configuration LS157 abstract |
| Abstract: 2010 4 1 NEC http://www.renesas.com 2010 4 1 http://www.renesas.com http://japan.renesas.com/inquiry 1. 2. 3. 4. 5. 6. 7. OA AV 8. 9. 10. RoHS 11. 12. 1. 2. 1 MOS MOS Integrated Circuit uPD705100 uPD705100 V830TM V830TM 32 PD705100V830NECV800TMV830 PD705100V830NECV800TMV830 ... | Original |
62 pages, |
V830 V800 uPD705100GJ uPD705100 n16n datasheet abstract |
| Abstract: MOS MOS Integrated Circuit uPD705100 uPD705100 V830TM V830TM 32 PD705100V830NECV800TMV830TM PD705100V830NECV800TMV830TM V830 V830 U10064J U10064J V830U12496J V830U12496J 32 16 16 K K RAM RAM K RAM K 16/32 G 100 MHz 3232 50/33 MHz CMOS3.3 V 16 PD705100GJ-100-8EU PD705100GJ-100-8EU 144LQFP20 144LQFP20 mm U11483JJ3V0DS00 U11483JJ3V0DS00 December 1997 N © NEC Corporation 1995,1996 uPD705100 uPD705100 144LQFP20 144LQFP20 mm 108 107 106 105 104 103 10 ... | Original |
60 pages, |
V830 V800 uPD705100GJ uPD705100 PD705100 V830TM PD705100V830NECV800TMV830TM PD705100 abstract |
| Abstract: Atmel Gate Arrays/Embedded Arrays Device Number ATL50 ATL50 Raw Gates Routable Gates Max Pin Count Max I/O Pins Gate Speed ATL50/4 ATL50/4 4,000 3,000 44 36 200 ps ATL50/15 ATL50/15 ATL50/25 ATL50/25 15,000 25,000 10,000 16,900 68 84 60 76 200 ps 200 ps ATL50/40 ATL50/40 38,000 25,400 100 92 200 ps ATL50/60 ATL50/60 58,000 34,600 120 112 200 ps ATL50/85 ATL50/85 86,000 51,900 144 136 200 ps ATL50/110 ATL50/110 110,000 65,900 160 15 ... | Original |
1 pages, |
ATL50 ATL50/4 ATL50/15 ATL50/25 ATL50/40 ATL50/60 ATL50/85 ATL50/110 ATL50/150 ATL50/200 ATL50/235 ATL50/300 ATL50/435 ATL50/550 ATL50 abstract |
| Abstract: National Semiconductor Application Brief 9 Tim Garverick Rusty Meier January 1986 If one desires the fastest possible operation of the DP8408A DP8408A 9A multi-mode dynamic RAM controller driver in accessing DRAMs mode 4 externally controlled access mode should be considered In using mode 4 there are three input signals which must be considered 1) RASIN generates RAS The equation for the delay between R C and CASIN that guarantees the specified DRAM tASC is 2) R C switches between ro ... | Original |
2 pages, |
DP8408A C1995 DP8408A abstract |
| Abstract: Appendix PLL701-04 PLL701-04 Low EMI Spread Spectrum Multiplier Clock AC Specification PARAMETERS CONDITIONS Input - Output Delay " t d" (first rising edge after input rising edge) Group Delay " t g" (first falling edge after input rising edge) MIN. TYP. MAX. UNITS Input clock = 16.5MHz Output clock = 66MHz (Fin x 4) Load = 15pF SSC = OFF 0 2.5 5 ns Input clock = 10~30MHz Output clock = 40~120MHz (Fin x 4) Load = 15pF SSC = OFF 7 10 13 ns Te ... | Original |
1 pages, |
multiplier PLL701-04 PLL701-04 abstract |
| Abstract: CXA1693Q CXA1693Q kic um. m cxai693Q(±, a-kic. fcfT'=)-fflADC(CXA1496AQ3 CXA1496AQ3Â¥) > IflA-ir^-d: i, i i C i >) , KfifS? • -t^-TU vi'IHife» : 20MHz(m)n) • ADCB? n y • ADCAI*ÃŒSS«IEÌÌÌÈ|DJ»I*J* : REF OUT=- 2 V,typ) • ««*EE : ± 5 V± 5 % •ie.mmm.ti : 2oomw • AÃŒjSIBKSM : -2.2-+0.2V • = 9 ns/13ns(,P) < K/.v = 2.0V,.-p) • : yrnV/^s«™, (VW=-2V, 0 V) • "7 -f - K • X/U" : - 63dB(typ) (T^/a = 1 Vp-p, 5 MHz) • Mik : 32P-QFP 32P-QFP • «ìME : ± 7 V • iM^ÃŒS)* : 0 ~75°c • tìMÃŒSffi : -65- +150'C CT) ffe - 405 -SONY â- as^sut EI ... | OCR Scan |
1 pages, |
LT 405 CXA1693Q CXA1496AQ CXA1496AQ3 CXA1693Q abstract |
| Abstract: 54/74H 54/74H TEST CONDITIONS C|_=15pF RU=280S2 280S2 PARAMETER FROM INPUT TO OUTPUT MIN TYP MAX UNIT 'Clock Clock frequency 25 30 MHz Propagation delay time tpi_H Low-to-high Preset 6 13 ns tpni_ High-to-low 12 24 tpm Low-to-high Clock 6 14 21 ns tpHL High-to-low 10 22 27 Load circuit and typical waveforms are shown at the tront of section. SPEED/PACKAGE AVAILABILITY 54 F,W 74 A, F 54H F,W 74H A,F TRUTH TABLE PIN CONFIGURATION A,F PACKAGE tn tn+1 J K Q 0 0 On 0 ... | OCR Scan |
1 pages, |
54/74H 280S2 54/74H abstract |
| Abstract: Atmel Programmable Logic Devices (PLDs) PLDs - Pins Vcc ... | Original |
2 pages, |
ATL60 ATF1500L AT6010 AT6005 AT6003 AT6002 UV diode datasheet 6.000 mhz atmel 424 datasheet abstract |
| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| -Full Flags Cascadable in Word Width and/or Word Depth Fast Access Times of 13ns With a 50 "> processes data at rates up to 50 MHz and access times of 13 ns in a bit-parallel format. Data outputs are www.datasheetarchive.com/files/texas-instruments/data/html/sgas004.htm |
Texas Instruments | 28/08/1997 | 2 Kb | HTM | sgas004.htm |
| Output-Ready Flag Synchronized to Read Clock Fast Access Times of 13 ns With a 50-pF Load and asynchronous data paths at 50-MHz clock rates and 13-ns access times and is designed for 3-V to 3.6-V V CC www.datasheetarchive.com/files/texas-instruments/data/html/sdas274-v1.htm |
Texas Instruments | 13/08/1997 | 3.4 Kb | HTM | sdas274-v1.htm |
| and glitch-energy performance. The MAX5012 MAX5012 MAX5012 MAX5012 is an ECL-compatible device. It features a fast 13ns Superior Performance over AD9712 AD9712 AD9712 AD9712: Improved Settling Time: 13ns Improved Glitch Energy: 15pV-s Master www.datasheetarchive.com/files/maxim/0010/quick178.htm |
Maxim | 04/04/2001 | 5.82 Kb | HTM | quick178.htm |
| and glitch-energy performance. The MAX5013 MAX5013 MAX5013 MAX5013 is a TTL-compatible device. It features a fast 13ns Superior Performance over AD9713 AD9713 AD9713 AD9713: Improved Settling Time: 13ns Improved Glitch Energy: 15pV-s Master www.datasheetarchive.com/files/maxim/0010/quick180.htm |
Maxim | 04/04/2001 | 5.82 Kb | HTM | quick180.htm |
| Output-Ready Flag Synchronized to Read Clock Fast Access Times of 13 ns With a 50-pF Load and asynchronous data paths at 50-MHz clock rates and 13-ns access times and is designed for 3-V to 3.6-V V CC www.datasheetarchive.com/files/texas-instruments/data/html/sdas274.htm |
Texas Instruments | 17/11/1997 | 3.4 Kb | HTM | sdas274.htm |
| -Ready, Output-Ready, and Half-Full Flags Cascadable in Word Width and/or Word Depth Fast Access Times of 13ns MHz and access times of 13 ns in a bit-parallel format. Data outputs are noninverting with respect to www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/sgas004a.htm |
Texas Instruments | 01/06/1998 | 5.81 Kb | HTM | sgas004a.htm |
| Output-Ready Flag Synchronized to Read Clock Fast Access Times of 13 ns With a 50-pF Load and clock rates and 13-ns access times. These devices are designed for 3-V to 3.6-V V CC operation. The www.datasheetarchive.com/files/texas-instruments/data/html/scas436b.htm |
Texas Instruments | 17/11/1997 | 3.62 Kb | HTM | scas436b.htm |
| Output-Ready Flag Synchronized to Read Clock Fast Access Times of 13 ns With a 50-pF Load and clock rates and 13-ns access times. These devices are designed for 3-V to 3.6-V V CC operation. The www.datasheetarchive.com/files/texas-instruments/data/html/scas436b-v1.htm |
Texas Instruments | 18/08/1997 | 3.62 Kb | HTM | scas436b-v1.htm |
| Output-Ready Flag Synchronized to Read Clock Fast Access Times of 13 ns With a 50-pF Load and All clock rates and 13-ns access times and is designedfor 3-V to 3.6-V V CC operation. The 56-pin www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/sdas274.htm |
Texas Instruments | 01/06/1998 | 8.06 Kb | HTM | sdas274.htm |
| fast switching speeds (t ON = 13ns, t OFF = 13ns). Cell phones, for example, often face ASIC W Fast Switching Action (V+ = 3.0V) t ON 13ns t OFF 13ns ESD HBM Rating >8kV 1.8V Logic www.datasheetarchive.com/files/intersil/device_pages/device_isl43l710.html |
Intersil | 07/09/2006 | 28.7 Kb | HTML | device_isl43l710.html |