NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| DS1972-F5+A0F | Maxim Integrated Products | 1024-Bit EEPROM iButton | 
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| DS2431P-001-00+T | Maxim Integrated Products | 1024-Bit 1-Wire EEPROM |
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| DS25LV02R-00A+T&R | Maxim Integrated Products | Low Voltage 1024-Bit EPROM |
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| DS2431P-103-01+T | Maxim Integrated Products | 1024-Bit 1-Wire EEPROM |
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| DS2431P-002-00/T | Maxim Integrated Products | 1024-Bit 1-Wire EEPROM |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: SiQïlOtiCS 1024-BIT BIPOLAR READ ONLY MEMORY (256x4 ROM) FEBRUARY 1975 DIGITAL 8000 SERIES TTL , ) are Bipolar 1024-Bit Read Only Memories, organized as 256 words by 4 bits per word. They are fully TTL , organizations. Both the 82S226 82S226 and 82S229 82S229 are also fully compatible with the 82S126/129 82S126/129, Signetics' 1024-Bit , CODE CONVERSION ORDERING INFORMATION Customer may specify patterns for the 1024-Bit Read Only Memory by , ]03 Ground e 3°« •B - PlMtic F - Ccrdip BLOCK DIAGRAM 40 SIGNETICS 1024-BIT BIPOLAR READ ONLY ... | OCR Scan |
3 pages, |
82S229 82S226 1024bit 1024-BIT 82S126/129 N82S226/229 S82S226/229 1024-BIT abstract |
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| Abstract: CS1024-RSA CS1024-RSA Data Sheet Device Pin Out CS1024-RSA CS1024-RSA 1024-bit Offload Processor General Operation The CS1024-RSA CS1024-RSA is an optimal RSA processor designed to support a variety of applications over almost a 10:1 performance scale. The Host processor invokes a particular operation by writing the , exponentiation. Performance Supported Modular Functions: The CS1024-RSA CS1024-RSA 1024-bit "mod exp" performance , perform 512-bit and 1024-bit computations. (c) 2010 Crack Semiconductor The enhanced 64-bit ... | Original |
2 pages, |
RSA 2048-bit 1024-BIT CS1024-RSA design processor using verilog 16 bit multiplier VERILOG CS1024-RSA abstract |
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| Abstract: 1024-Bit Programmable ROM (pROM) 33040C 33040C C36 DM8575N DM8575N Programmable Logic Array (Active) 33041C 33041C C37 DM8576N DM8576N , 4096-Bit (512 x 8) ROM 33046D 33046D C44 DM8597N DM8597N TRI-STATE 1024-Bit ROM TRI-STATE DM74187 DM74187 31038C 31038C C45 DM8598N DM8598N , 1024-bit programmable ROM (pROM) I 1 1 1 Me, me2 y *2 *3 *«. - MEMORY ENABLE OUTPUTS 7 BINARY , C36 DM8K74N DM8K74N 1024-bit programmable ROM (pROM) (Tri-istate) Vcc C34 DMS556N DMS556N Trt-State Programmable ... | OCR Scan |
2 pages, |
DM8574D DM8576N DM8595N DM8596N DM8597N DM8601N panaplex dm8601 DM8575N DM8880 SN75361 33040C 33041C DM8574D abstract |
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| Abstract: Accelerates Public Key Operations - Average of 45 ms for 1024-bit expo · Synchronous SRAM Interface · Low , intensive mathematical operations. Able to perform 1024-bit exponentiations on an average of 45 , 1024-bit number, a 1024-bit modulus and up to a 1024-bit exponent. The following equation is considered ... | Original |
2 pages, |
1024bit VMS115 VMS115 abstract |
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| Abstract: GXB10415A GXB10415A 1024-bit RAM The GX family of ECL silicon monolithic integrated circuits is designed for high , recommended for high speed large system design. The GXB10415 GXB10415 and 10415A are 1024-bit random access memories , corresponds to the ECL 10 000 series. 1024-BIT, 1-BIT PER WORD RANDOM ACCESS MEMORIES Pin abbreviations CS , 1024-bit RAM 7 16 2 A0 3 Ai 4 A 2 5 A3 6 A4 X DECODER /DRIVER 14 CS. 13 WE, 15 D Vcc LINE , 0 X = state is immaterial Mullard r> GX family yv GXB10415 GXB10415 GXB10415A GXB10415A 1024-bit RAM Ag to Ag ... | OCR Scan |
9 pages, |
GXB10415D GXB10415AD GXB10415A GXB10415 1024-BIT GXB10415 abstract |
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| Abstract: ® MOTOROLA PRODUCT PREVIEW 1024-BIT RANDOM ACCESS MEMORY The MCM93412 MCM93412 is a 1024-bit Read/Write RAM organized 256 words by 4 bits. The MCM93412 MCM93412 is designed for buffer control storage and high performance main memory applications, and has a typical access time of 35 ns. MCM93412 MCM93412 has full decoding on-chip, separate data input and data output lines, two chip selects, an output enable and write enable. The device is fully compatible with standard DTL and TTL logic families and features an uncommitted ... | OCR Scan |
1 pages, |
MCM93412 1024-BIT 1024-BIT abstract |
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| Abstract: MCM10144L MCM10144L 16x4 Register File (RAM) MCM10145L MCM10145L 1024-Bit Random Access Memory MCM 10146 128-Bit Random Access Memory MCM10147L MCM10147L 64-Bit Random Access Memory (50 Î2 ) MCM10148L MCM10148L 1024-Bit Programmable Read-Only ... | OCR Scan |
1 pages, |
memories 1024bit 14552 MCM10142L MCM10143L MCM10144L MCM10145L MCM10147L MCM10148L MCM10149L MCM14505 MCM5003L MCM5004L "Random Access Memory" MCM14505 abstract |
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| Abstract: ® MOTOROLA PRODUCT PREVIEW 1024-BIT RANDOM ACCESS MEMORY The MCM93L422 MCM93L422 is a 1024-Bit Read/Write RAM, organized 256 words by 4 bits. The MCM93L422 MCM93L422 has full decoding on-chip, separate data input and data output lines, two-chip selects, an output enable and write enable. The device is fully compatible with standard DTL and TTL logic families. A three-state output is provided to drive bus-organized systems and/or highly capacitive loads. • Low Power Dissipation • Three-State Output • TTL Inputs and ... | OCR Scan |
1 pages, |
MCM93L422 1024-BIT 1024-BIT abstract |
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| Abstract: ® MOTOROLA, 1024-BIT RANDOM ACCESS MEMORY The MCM93425 MCM93425 is a 1024-bit Read/Write RAM, organized 1024 words by 1 bit. The MCM93425 MCM93425 is designed for high performance main memory and control storage applications and has a typical address time of 35 ns. The MCM93425 MCM93425 has full decoding on-chip, separate data input and data output lines, and an active low-chip select and write enable. The device is fully compatible with standard DTL and TTL logic families. A three-state output is provided to drive bus-organized ... | OCR Scan |
1 pages, |
1024-BIT MCM93425 1024-BIT abstract |
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| Abstract: multi-application cards with high level of security. 1408-bit crypto engine optimized for 1024-bit and 2048-bit RSA , 1024-bit and 2048-bit RSA calculation, Elliptic Curves. Certified CC EAL5+ high. SLE 88CF(X)4000P 4000P , crypto engine optimized for 1024-bit and 2048-bit RSA calculation, Elliptic Curves. Certified CC EAL5+ , cards with high level of security. 1408-bit crypto engine optimized for 1024-bit and 2048-bit RSA , 1024-bit and 2048-bit RSA calculation, Elliptic Curves. Certification target CC EAL5+ high. SLE 88CF(X ... | Original |
4 pages, |
mais 88CFX4002P 88C1640P 4002p 184-kByte 88CNFX6600PM nxp nfc nfc chip datasheet abstract |
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| Abstract: Semiconductors Connection Diagrams B127 SN74182N SN74182N Look ahead carry Vcc P2 G2 cn Cn+xCn+y G P3 P GND " OUT B130 SN74187N SN74187N SN74L187AN SN74L187AN 1024-bit ROM (256 x 4) BIN BINARV SELECT B128 SN74184N SN74184N BCD-to-Binary converter ENAB Vcc G ' BINARY SELECT Y1 Y2 Y3 Y* Y8 Y6 Y7 GND B129 SN74185AN SN74185AN Binary-to-BCD converter BINARY SELECT ENAB / Vcc G E Y1 Y2 Y3 Y4 Y5 Y6 Y7 GND B131 SN74189N SN74189N 64-bit RAM B132 SN74190N SN74190N Up/Down decade counter INPUTS INPUTS ,-«-^ OUT ,- DATA RPL MAX DATA DATA Vcc A CNT CNT MIN ... | OCR Scan |
1 pages, |
SN74L187AN B127 B128 B129 SN74182N SN74187N B131 6132 RAM SN74189N SN74184N SN74185AN SN74182N abstract |
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| Abstract: sequentially access the entire 1024-bit contents (burst). Interface cost to a microprocessor is minimized by , characteristics, bus timing, and signal descriptions other than VBAT, see the DS1201 DS1201 Electronic Tag 1024-Bit data ... | Original |
1 pages, |
DS1201 DS1200 DS1200 abstract |
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| Abstract: INTEGRATED CIRCUITS MEMORY 1024-BIT STATIC RANDOM ACCESS MIEMORY GENERAL DESCRIPTION Tin; 2 11,02 is ... | OCR Scan |
1 pages, |
LT A04 1024-BIT 1024-BIT abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| incorporate the latest 1024-bit flexible modular encryption unit, which can perform complex cryptography ) and the M68HC05SC50 M68HC05SC50 M68HC05SC50 M68HC05SC50 (SC50). The SC49A SC49A SC49A SC49A chip is an 8-bit microcontroller with 1024-bit modular arithmetic co-processor, 20Kb ROM, 4Kb EEPROM, 896 bytes of RAM and an operating voltage of 3-5V. The 1024-bit modular encryption unit can also efficiently handle 512 and 786 bit keys. The SC50 chip uses the bit flexible modular encryption co-processor which is capable of implementing 1024 bit cryptography www.datasheetarchive.com/files/motorola/cdcsic2/web/whatsnew/pressrls/pr961028.htm |
Motorola | 08/03/1998 | 11.09 Kb | HTM | pr961028.htm |
| incorporate the latest 1024-bit flexible modular encryption unit, which can perform complex cryptography ) and the M68HC05SC50 M68HC05SC50 M68HC05SC50 M68HC05SC50 (SC50). The SC49A SC49A SC49A SC49A chip is an 8-bit microcontroller with 1024-bit modular arithmetic co-processor, 20Kb ROM, 4Kb EEPROM, 896 bytes of RAM and an operating voltage of 3-5V. The 1024-bit modular encryption unit can also efficiently handle 512 and 786 bit keys. The SC50 chip uses the bit flexible modular encryption co-processor which is capable of implementing 1024 bit cryptography www.datasheetarchive.com/files/motorola/web/whatsnew/pressrls/pr961028.htm |
Motorola | 10/02/1997 | 10.11 Kb | HTM | pr961028.htm |
| engine defaults to generating 1024-bit keys using pre-calculated * base, prime, and subprime values values between 512 and * 1024 bits inclusives. * * @param modlen The modulus length www.datasheetarchive.com/download/79262054-393174ZC/mplabc30v2_05.tgz |
Microchip | 09/11/2006 | 27045.95 Kb | TGZ | mplabc30v2_05.tgz |
| ) Exponentiator / multiplier - Accelerates Public Key operations - Average of 45 ms for 1024-bit www.datasheetarchive.com/files/philips/pip/pip_2-v1.html |
Philips | 14/02/2002 | 5.04 Kb | HTML | pip_2-v1.html |
| - Average of 45 ms for 1024-bit Synchronous SRAM interface Low power mode available Interrupt www.datasheetarchive.com/files/philips/pip/pip_2.html |
Philips | 24/04/2003 | 3.35 Kb | HTML | pip_2.html |
| advanced functions - Software selectable operand length up to 1024 bits n SECURITY FIREWALLS FOR MAP verification (e=$10001) 100 ms RSA 1024 bits signature with CRT 400 ms RSA 1024 bits signature without CRT N/A RSA 1024 bits verification (e=$10001) 150 ms 2 2 2 2 Micromodule (D4) Wafer BD. CF68 /9809VP /9809VP /9809VP /9809VP 5 bit architecture, it processes modular multiplication and squaring up to 1024 bit operands. The ST for any modulo length up to 1024 bits long or DSA signature and veri- fication . - full internal www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5005.htm |
STMicroelectronics | 20/10/2000 | 7.61 Kb | HTM | 5005.htm |
| of advanced functions - Software selectable operand length up to 1024 bits n SECURITY FIREWALLS FOR CRT 200 ms RSA 768 bits signature without CRT N/A RSA 768 bits verification (e=$10001) 100 ms RSA 1024 bits signature with CRT 400 ms RSA 1024 bits signature without CRT N/A RSA 1024 bits verification (e and squaring up to 1024 bit operands. The ST19 CF68 is based on a STMicroelectronics 8 bit CPU core authentications for any modulo length up to 1024 bits long or DSA signature and veri- fication . - full internal www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5005-v1.htm |
STMicroelectronics | 02/04/1999 | 5.56 Kb | HTM | 5005-v1.htm |
| of advanced functions - Software selectable operand length up to 1024 bits n SECURITY FIREWALLS FOR CRT 200 ms RSA 768 bits signature without CRT N/A RSA 768 bits verification (e=$10001) 100 ms RSA 1024 bits signature with CRT 400 ms RSA 1024 bits signature without CRT N/A RSA 1024 bits verification (e and squaring up to 1024 bit operands. The ST19 CF68 is based on a STMicroelectronics 8 bit CPU core authentications for any modulo length up to 1024 bits long or DSA signature and veri- fication . - full internal www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5005-v2.htm |
STMicroelectronics | 14/06/1999 | 5.52 Kb | HTM | 5005-v2.htm |
| . Fast Map Performance - 512 and 1024 bit The MAP, which is based on 512 bit or 1024 bit RSA, 512 bit verification 3 ms RSA, 1024 bit signature, with CRT 110 ms RSA, 1024 bit signature, no CRT 380 ms RSA, 1024 bit -function Cryptocomputers - with Modular Arithmetic Processor using up to 1024 bit keys ST19CF ST19CF ST19CF ST19CF www.datasheetarchive.com/files/stmicroelectronics/stonline/prodpres/memory/smartcar/flsc9808.htm |
STMicroelectronics | 14/06/1999 | 9.17 Kb | HTM | flsc9808.htm |
| . Fast Map Performance - 512 and 1024 bit The MAP, which is based on 512 bit or 1024 bit RSA, 512 bit verification 3 ms RSA, 1024 bit signature, with CRT 110 ms RSA, 1024 bit signature, no CRT 380 ms RSA, 1024 bit -function Cryptocomputers - with Modular Arithmetic Processor using up to 1024 bit keys ST19CF ST19CF ST19CF ST19CF www.datasheetarchive.com/download/38214880-840820ZC/scupdate-v1.zip (flsc9808.htm) |
STMicroelectronics | 26/11/1998 | 38.27 Kb | ZIP | scupdate-v1.zip |