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LTC7541ABSW#TR Linear Technology LTC7541A - Improved Industry Standard CMOS 12-Bit Multiplying DAC; Package: SO; Pins: 18; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC7541AKSW Linear Technology LTC7541A - Improved Industry Standard CMOS 12-Bit Multiplying DAC; Package: SO; Pins: 18; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC7541AJN#PBF Linear Technology LTC7541A - Improved Industry Standard CMOS 12-Bit Multiplying DAC; Package: PDIP; Pins: 18; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC7541AKSW#TR Linear Technology LTC7541A - Improved Industry Standard CMOS 12-Bit Multiplying DAC; Package: SO; Pins: 18; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC7541AJSW#PBF Linear Technology LTC7541A - Improved Industry Standard CMOS 12-Bit Multiplying DAC; Package: SO; Pins: 18; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC7541AKN Linear Technology LTC7541A - Improved Industry Standard CMOS 12-Bit Multiplying DAC; Package: PDIP; Pins: 18; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy

0.5-um CMOS standard cell library

Catalog Datasheet MFG & Type PDF Document Tags

MOS RM3

Abstract: mos rm3 data 0.35 µm CMOS Process Family XO035 MIXED-SIGNAL FOUNDRY EXPERTS 0.35 Micron Modular CMOS , RF performance - High Density up to 18000 gates per mm2 - I/O cell library with 4kV HBM ESD , world is analog. XO035 - Foundry-specific optimized libraries - Standard core library for high , Standard MOS module SIngle poly, triple metal CMOS 3.3V NMOS/PMOS and resistors This main module can , optimized for best synthesis results in high speed applications. - The standard low noise core library
X-FAB Semiconductor Foundries
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MOS RM3 mos rm3 data Silicon Image 1364 cmos transistor 0.35 um 6E-08

0.25-um CMOS standard cell library inverter

Abstract: OLIVETTI General Description The CB55000 standard cell series uses a high performance, low-voltage, 0.25 µm drawn (0.20 µm effective), six metal levels CMOS process HCMOS7 to a 90 pico-second internal delay , : · SSI cell library · I/O cell library · Macrofunctions 3.1 SSI Cell Library , offered with CB55000, one 80 µm pad in line pitch library and one 50 µm staggered pad library to support , differential receivers and converts them into standard CMOS receivers. This allows lddq test methodologies to
STMicroelectronics
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0.25-um CMOS standard cell library inverter OLIVETTI CMOS GATE ARRAY stmicroelectronics CB45000

b55qs

Abstract: ultra fine pitch BGA perspective view CMOS 0.25 µm, Shallow Trench Isolation, M1: Tungsten 2/15 CB55000 Series 1 GENERAL DESCRIPTION The CB55000 standard cell series uses a high performance, low-voltage, 0.25 µm drawn (0.20 µm effective), six metal levels CMOS process HCMOS7 to a 90 pico-second internal delay , organized into three categories: ­ SSI cell library ­ I/O cell library ­ Macrofunctions 3.1 SSI Cell , CB55000, one 80 µm pad in line pitch library and one 50 µm staggered pad library to support pad limited
STMicroelectronics
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b55qs ultra fine pitch BGA CB55Q CMOS GATE ARRAY BGA stmicroelectronics D950 b55q

8mm pitch BGA 256 pin 14x14

Abstract: CB45000 perspective view CMOS 0.25 µm, Shallow Trench Isolation, M1: Tungsten 2/15 CB55000 Series 1 GENERAL DESCRIPTION The CB55000 standard cell series uses a high performance, low-voltage, 0.25 µm drawn (0.20 µm effective), six metal levels CMOS process HCMOS7 to a 90 pico-second internal delay , organized into three categories: ­ SSI cell library ­ I/O cell library ­ Macrofunctions 3.1 SSI Cell , CB55000, one 80 µm pad in line pitch library and one 50 µm staggered pad library to support pad limited
STMicroelectronics
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8mm pitch BGA 256 pin 14x14 ST10 ST100 ST20 of BGA Staggered pins bga 10x10

CMOS

Abstract: pmos4 0.8 µm CMOS Process CX08 MIXED-SIGNAL FOUNDRY EXPERTS 0.8 Micron Modular Mixed Signal , target applications are standard cell, semi-custom and full custom designs for Industrial, Tele­ om , optimized libraries - Standard core library for high speed digital blocks - Low-power library, 50% less , ] Spacing [µm] Standard N-well 5.0 5.0 HV deep N-well 5.0 11.0 HV shallow N-well , applications. The standard core library includes more then 200 cells. Functionality and layouts are optimised
X-FAB Semiconductor Foundries
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CMOS pmos4

MOS RM3

Abstract: 0.35 µm CMOS Process Family XO035 MIXED-SIGNAL FOUNDRY EXPERTS 0.35 Micron Modular CMOS , Competitive RF performance - High Density up to 18000 gates per mm2 - I/O cell library with 4kV HBM ESD , Foundry-specific optimized libraries - Standard core library for high speed digital blocks - Pad-limited IO , bandwidth photo diodes arrays or CMOS image sensors for such applications as optical data storage, optical , the art 0.35 μm CMOS Processes. Comprehensive design rules, accurate SPICE models, analog and
X-FAB Semiconductor Foundries
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MOS RM3

Abstract: mos rm3 data 0.35 µm CMOS Process Family XA035 MIXED-SIGNAL FOUNDRY EXPERTS 0.35 Micron High Temperature , beyond AEC Q100 requirement. - High Density up to 18000 gates per mm2 - I/O cell library with 4kV HBM , libraries - Standard core library for high speed digital blocks - Pad-limited IO library - Core-limited , Applicaitons MOS 14 Standard MOS module SIngle poly, triple metal CMOS 3.3V NMOS/PMOS and , Cell height for core limited I/O cells is 248.8m and minimum pad pitch is 173m - The TTL and CMOS
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XH035 ESD "p-well" n-well" 0.18 um CMOS Spiral Inductor technology RM3 transistors bsim3v3

mos rm3 data

Abstract: MOS RM3 0.35 µm CMOS Process Family XA035 MIXED-SIGNAL FOUNDRY EXPERTS 0.35 Micron High Temperature Modular CMOS Technology Description The XA035 Series is X-FAB`s 0.35 Micron High Temperature CMOS , beyond AEC Q100 requirement. - High Density up to 18000 gates per mm2 - I/O cell library with 4kV HBM , libraries - Standard core library for high speed digital blocks - Pad-limited IO library - Core-limited , Applicaitons MOS 14 Standard MOS module SIngle poly, triple metal CMOS 3.3V NMOS/PMOS and
X-FAB Semiconductor Foundries
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RM4L DCELL Q100 metal oxide in capacitor analog devices transistor tutorials

AMIS500CXASCM

Abstract: 0.5um amis cmos Standard and slew rate limited availability · PCI 33MHz compliant · CMOS, TTL, LVCMOS, LVTTL, PCI (33MHz) levels SC5 0.5µ µm CMOS Standard Cell Feature Sheet · Automatic test program generation (ATPG) · , AMI Semiconductor SC5 0.5µm CMOS Standard Cell Key Features · Excellent performance: · 590MHz , simple analog functions to ASIC designs. SC5 0.5µm CMOS Standard Cell -Feature Feature Sheet Sheet , design: · Complete primary cell and I/O library · Synchronous ROM compiler from 64x1 to 16Kx32 bits ·
AMI Semiconductor
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AMIS500CXASCM 0.5um amis cmos 590MH M-20523-001

zener diode phc

Abstract: zener phc 12 Core Library Cells X-FAB provides a standard cell library optimized for most typical applications , Digital Standard Cell Core Library is available in X-FAB XDM10 technology Name Voltage Range , . - The I/O cell library requires the CMOS module. - I/O cells are optimized for 5.0V +/-10% , /µm] max. VTB [V] PWELLD rpwd CORE 1530 5 - 50 PWELL rpw CMOS , : 2.86 standard digital applications library density: kGE/mm at given routing factor (GE = NAND2
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zener diode phc zener phc 12 zener diode phc 10 zener PH-C zener diode phc 16 zener diode phc 24

zener diode phc 24

Abstract: -20/zener diode phc 24 [â"¦] Zener Zap dzap CMOS 4.8 50 50 Digital Core Library Cells X-FAB provides a standard cell library optimized for most typical applications in mixed signal ASIC. The XDM10 standard cells can be used double-metal routing. The following Digital Standard Cell Core Library is , library cells are available for core-limited designs. - The I/O cell library requires the CMOS module. - , 1.0 µm BCD Process XDM10 MIXED-SIGNAL FOUNDRY EXPERTS Modular 1.0µm 350V Trench Insulated
X-FAB Semiconductor Foundries
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350v ZENER DIODE

nmos transistor 0.35 um

Abstract: npn pnp rf transistor bipolar cross reference Foundry-specific optimized libraries - Standard core library for high speed digital blocks - Low-noise, standard , 0.6 µm BiCMOS Process Family XHB06 MIXED-SIGNAL FOUNDRY EXPERTS 0.6 Micron Modular HV BCD Technology Description The XHB06 is X-FAB's 0.6 Micron High-Voltage Bipolar CMOS DMOS (BCD) Technology , 0.6 process family. Reliable design rules, precise SPICE models, cell libraries, IP's and , transistors - 5V I/O with improved ESD robustness - High precision BSIM3V3 SPICE models for CMOS and Gummel
X-FAB Semiconductor Foundries
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nmos transistor 0.35 um npn pnp rf transistor bipolar cross reference l24c using a zener diode as a varicap NMOS depletion pspice model bsim3 model for 0.18 micron technology for hspice
Abstract: world is analog. XB06 - Foundry-specific optimized libraries - Standard core library for high speed digital blocks - Low-noise, standard core library with separate bulk supply for reduced , for best synthesis results in high speed applications. - The standard low noise core library , 0.6 µm BiCMOS Process Family XB06 MIXED-SIGNAL FOUNDRY EXPERTS 0.6 Micron Modular BiCMOS , 0.6 process family. Reliable design rules, precise SPICE models, cell libraries, IPâ'™s and X-FAB Semiconductor Foundries
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spice model Tunnel diode

Abstract: TUNNEL DIODE spice model per mm2 (2ML/3ML) - Pad-limited 5V I/O cell libraries with CMOS / TTL interfacing capability - , state of the art 0.6 µm CMOS processes. For analog applications several capacitor and resistor , combination of these modules, the 0.6 µm Trench SOI CMOS process family XT06 offers a wide variety of proven , in class results of area, speed, low power and low noise. - The standard core library is , low power library less than standard library NMOS, PMOS with separated bulk supply Digital I/O
X-FAB Semiconductor Foundries
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spice model Tunnel diode TUNNEL DIODE spice model dpsN

"X-Fab" Core cell library

Abstract: nd65d Digital Core Library Cells X-FAB provides a standard cell library optimized for most typical , Digital Standard Cell Core Library is available in X-FAB XDM10 technology Name Voltage Range , library cells are available for core-limited designs. - The I/O cell library requires the CMOS module. - , . CMOS Devices Device Device Name Available with module |VT| [V] min. gate length [µm] |BVDS| [V] IDSAT [µA/µm] max. VDS [V] max. VGS [V] 5V NMOS ne CMOS 0.80 1.2
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XDH10 nd65d pnp transistor 650v 20 PHB zener nd35b

atmel 0726

Abstract: OAI22 Available Gates 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized , 10/20/2004 Product Description Rad Hard 190K Used Gates 0.5 µm CMOS Sea of Gates , Programmable Pads Standard 3, 6, 12 and 24 mA I/Os Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator , 190K Used Gates 0.5 µm CMOS Sea of Gates MG2RTP · · · · · · · · · Description The MG2RTP , : 1. Not available for new designs. Libraries The MG2RTP cell library has been designed to take
Atmel
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atmel 0726 OAI22 0.5-um CMOS standard cell library 4116J

NZ70008H

Abstract: STEPS 30175 ) Ti-Silicide CMOS technology Ultra high density cell structure · Optimised 3.3 Volt transistor , ratio Minimum device cost for high I/O requirement · Large I/O cell library including LVTTL,HSTL , standard devices. 22 The CB-C9VX 3.3 V library features a typical gate delay of 75 ps for a 2 , by connecting basic hard macros Interface Macro Support The CB-C9VX/VM standard interface library , DATA SHEET PRODUCT LETTER CB-C9VX/VM 0.35-Micron CMOS Cell-Based ASICs Description Figure 1
NEC
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GB-MK14 NZ70008H STEPS 30175 STR 6755 k2736 NZ70 NEC V30MX NL-5612 S-18322 F-78142 E-28007 I-20124 I-00139

ST100

Abstract: tristate nand gate Libraries Two basic buffer libraries are offered with CB65000, one 80 µm pad in line pitch library and one 50 µm staggered pad library to support pad limited designs. Apart from standard ESD and latch-up , PRELIMINARY CB65000 Series 1 General Description The CB65000 standard cell series uses a high , library is organized into three categories: · SSI cell library · I/O cell library · Macrofunctions 3.1 SSI Cell Library Overview The design of the CB65000 family has been optimized to
STMicroelectronics
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tristate nand gate

DIN 53018

Abstract: PD65800 must be kept low. In addition, because many development tools and standard cell libraries are available , /VM Standard cell SC-4 SC-5 Custom micro CMICRO-4 CMICRO-5 EA-C10 Embedded , building block type standard cell design technique. Cell-based ICs cannot only realize a density higher , X13769XJ2V0CD00 05-26 Semi-Custom IC Gate Array CMOS Gate Array s CMOS-6/6A/6S Family q Library I/O , % (CMOS level), 5 V ± 5 % (TTL level) * 2-input NAND conversion * Cell utilization rate: 75 % Output
NEC
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DIN 53018 PD65800 PD65654 UPD65625 uPD65656 upc5032

0.18-um CMOS technology characteristics

Abstract: NEC 71055 , LVTTL level, GTL+,HSTL, PCI, pECL Standard cell 0.25 µm (0.18 µm effective) silicon gate CMOS; 3,4 or 5 , .) Ti-Silicide CMOS process Ultra high density cell structure at high performance · Extensive support of , CMOS-10 and EA-C10 product letters to get more information to the 0.25 µm gate array and embedded , DATA SHEET PRODUCT LETTER CB-C10 2.5 Volt 0.25-Micron CMOS Cell-Based ASIC PRELIMINARY Figure 1. Chip Size Package (CSP) Description NEC's 0.25 µm (0.18 µm eff.) CB-C10 family incorporates
NEC
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0.18-um CMOS technology characteristics NEC 71055 DSPG nec asic product letter 71055 A1246 IEEE1394
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