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at28c16 eeprom

Abstract: AT28C64E 5962-8852506 AT28C16 DM AT28C16E AT28C17E AT28C256E AT28C040 AT28C64 AT28C64B
Text: /883, FM/883 5962-8852501 -or- 09 UX, XX, YX , ZX AT28C256-30UM/883, DM/883, LM/883, FM/883 5962-8852502 -or- 10 UX, XX, YX , ZX AT28C256-25UM/883, DM/883, LM/883, FM/883 5962-8852503 -or- 11 UX, XX, YX , ZX AT28C256-20UM/883, DM/883, LM/883, FM/883 5962-8852504 -or- 12 UX, XX, YX , ZX AT28C256E-25UM/883, DM/883, LM/883, FM/883 5962-8852505 -or- 13 UX, XX, YX , ZX AT28C256-15UM/883, DM/883, LM/883, FM/883 5962-8852506 -or- 14 UX, XX, YX , ZX AT28C256F-15UM/883, DM/883, LM/883, FM/883 5962-8852507


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PDF AT28C16 AT28C16E AT28C17 AT28C17E AT28C64 AT28C64E AT28C64B AT28HC64B AT28C256 AT28C256E at28c16 eeprom AT28C64E 5962-8852506 AT28C16 DM AT28C16E AT28C17E AT28C256E AT28C040 AT28C64 AT28C64B
1998 - eeprom 28c64

Abstract: 5962-87514 AT28C64B-20DM at28c64-20dm AT28C64B-25DM 28C64 EEPROM smd code led at28c6425dm 5962-88525 15 ZX AT28C64-25DM
Text: Range (M=Military) Standard Microcircuit Drawing Product Offering 5962-38267 01 M YX Atmel , Number Atmel Similar Part Number 5962-87514 13 XX 5962-87514 13 YX AT28C64-35LM/883 5962-87514 13 ZX AT28C64-35FM/883 5962-87514 14 XX AT28C64-30DM/883 5962-87514 14 YX AT28C64-30LM/883 5962-87514 15 XX AT28C64-25DM/883 5962-87514 15 YX AT28C64-25LM/883 5962-87514 15 ZX AT28C64-25FM/883 5962-87514 16 XX AT28C64-20DM/883 5962-87514 16 YX Atmel Cage No


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PDF MILSTD-883, 0553B 06/98/xM eeprom 28c64 5962-87514 AT28C64B-20DM at28c64-20dm AT28C64B-25DM 28C64 EEPROM smd code led at28c6425dm 5962-88525 15 ZX AT28C64-25DM
2008 - Not Available

Abstract: No abstract text available
Text: €¢ Outputs ( Yx , Yx ), (FBOUT, FBOUT): SSTL_2 • External feedback pins (FBIN,FBIN) are used to synchronize , 2.5V SSTL 2 DDR SDRAM Memory Yx ,FBOUT Yx ,FBOUT t cycle n t cycle n+1 t jit(cc) = t cycle , Offset Yx Yx Yx , FBOUT Yx , FBOUT t sk(o) Figure 5. Output Skew 08-0030 7 PS8545D 02/12/08 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory Yx , FBOUT Yx , FBOUT t cycle n Yx , FBOUT Yx , FBOUT 1 fO t jit(per) = t cycle n 1 fO Figure 6. Period Jitter


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PDF PI6CV855 28-pin PI6CV855 MO-153F/AE 28-Pin, 173-Mil PI6CV855LE PS8545D
2003 - DDR266

Abstract: HD74CDCV857
Text: 12 f = 170 MHz, VDDQ = AVCC = 2.7 V, All Yx , Yx pin = open ICCpd - - 100 Supply , FBOUT FBOUT Yx Yx tsk Yx Yx Yx ' Yx ' tsk Figure 4 Output skew Rev.7.00, Oct.09.2003, page 9 of 12 HD74CDCV857 Yx , FBOUT Yx , FBOUT t cycle n t cycle n+1 t cc = t cycle n - t cycle n+1 Figure 5 Cycle to cycle jitter Yx , FBOUT Yx , FBOUT t cycle n Yx , FBOUT Yx , FBOUT 1 fo t PER = t cycle n - 1 fo Figure 6 Period jitter Yx , FBOUT Yx , FBOUT t half


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2001 - HD74CDCV857

Abstract: DSA003634
Text: 100 Supply current in power down mode Note: All Yx , Yx pin = open µA 1. For conditions , resistor CLKIN CLKIN FBIN FBIN tSPE Figure 3 Static phase offset FBOUT FBOUT Yx Yx tsk Yx Yx Yx ' Yx ' tsk Figure 4 Output skew 9 HD74CDCV857 Yx , FBOUT Yx , FBOUT t cycle n t cycle n+1 t cc = t cycle n - t cycle n+1 Figure 5 Cycle to cycle jitter Yx , FBOUT Yx , FBOUT t cycle n Yx , FBOUT Yx , FBOUT 1 fo t PER = t cycle n - 1 fo Figure 6 Period


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PDF HD74CDCV857 ADE-205-335E HD74CDCV857 PC100 DSA003634
WTB-36

Abstract: wtb36 PCL-FR-370
Text: a U A/, y\x yxFLyX y-iK-• ^ •. x\X *\X yCjAA»*' y yx y\x vsx xx Jv ; ì 'v vpf«^ "i'xjnfyx , :^yv< y< a yXX vx X '\X y\ Sx* ySXy's y vi y1^xSx* y sx y ^ xSX n xSx* ys x y >'v' y^x V^! x x vxX s-XX>X. A^ v*^ x yx vvii vsyjiX x ^x v v*' •■AX^^ y\xX xXx ^ a vx <./ tt •,». v v ^ -, 4 ^ a , . >s>\xys.x yX v\xyxy v^xnx v^.x'y^,v\x>AX yS^> \y\ , , , , v\x s-sxv"^ ^^ >•' SN vsx v y^x v^x' y


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PDF TB-363+ PCL-FR-370 WTB-363+ WTB-36 wtb36
PI6CV857

Abstract: No abstract text available
Text: output pairs. Inputs (CLK,CLK) and (FBIN,FBIN) : SSTL_2 Input PWRDWN : LVCMOS Outputs ( Yx , Yx ), (FBOUT , Reference Clock input Yx 3,5,10,20,22,27, 29,39,44,46 O Clock outputs. Yx 2,6,9,19,23,26 , Clock outputs. Feedback output. I Feedback input. Power down and output disable for all Yx and Yx , Yx ,FBOUT Yx ,FBOUT t cycle n t cycle n+1 t jit(cc) = t cycle n - t cycle n+1 Figure 3 , is a large number of samples) Figure 4. Static Phase Offset Yx Yx Yx , FBOUT Yx , FBOUT t


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PDF PI6CV857 PI6CV857 48-Pin PS8464A
PLL 02 AG

Abstract: No abstract text available
Text: /) : SSTL_2 Input PWRDWN/ : LVCMOS Outputs ( Yx , Yx /), (FBOUT, FBOUT/) : SSTL_2 External feedback pins (FBIN , Pinout Table Pin Name CLK CLK / Yx Yx / FBO UT FBO UT/ FBIN FBIN/ PWRDWN/ Pin No. 13 14 3,5,10 , for all Yx and Yx / outputs. When PWRDWN/ = 0, the part is powered down and the differential clock , Yx /,FBOUT/ Yx ,FBOUT t cycle n t jit(cc) = t cycle n - t cycle n+1 t cycle n+1 Figure 3 , number of samples) N Figure 4. Static Phase Offset Yx / Yx Yx /, FBOUT/ Yx , FBOUT t sk(o


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PDF PI6CV857 PI6CV857 48-Pin PS8464 PLL 02 AG
2000 - HD74CDCV857

Abstract: Hitachi DSA00383
Text: error 10 HD74CDCV857 FBOUT FBOUT Yx Yx tsk Yx Yx Yx ' Yx ' tsk Figure 4 Output skew 11 HD74CDCV857 Yx , FBOUT Yx , FBOUT t cycle n t cycle n+1 t cc = t cycle n ­ t cycle n+1 Figure 5 Cycle to cycle jitter Yx , FBOUT Yx , FBOUT t cycle n Yx , FBOUT Yx , FBOUT 1 fo t PER = t cycle n ­ 1 fo Figure 6 Period jitter Yx , FBOUT Yx , FBOUT t half period n t half period n+1 Yx , FBOUT Yx , FBOUT 1 fo t HPER = t half period n ­ 1 2*fo Figure 7 Half


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PDF HD74CDCV857 ADE-205-335C HD74CDCV857 PC100 Hitachi DSA00383
2000 - Hitachi DSA00167

Abstract: No abstract text available
Text: Supply current in power down mode Note: 8 All Yx , Yx pin = open µA 1. For conditions shown as , CLKIN CLKIN FBIN FBIN tSPE Figure 3 Static phase offset FBOUT FBOUT Yx Yx tsk Yx Yx Yx ' Yx ' tsk Figure 4 Output skew 10 HD74CDCV857 Yx , FBOUT Yx , FBOUT t cycle n t cycle n+1 t cc = t cycle n ­ t cycle n+1 Figure 5 Cycle to cycle jitter Yx , FBOUT Yx , FBOUT t cycle n Yx , FBOUT Yx , FBOUT 1 fo t PER = t cycle n ­ 1 fo Figure 6 Period jitter Yx


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PDF HD74CDCV857 ADE-205-335D HD74CDCV857 PC100 mod2100 Hitachi DSA00167
2009 - PI6CV857

Abstract: PI6CV857L PI6CV857LA
Text: Input PWRDWN: LVCMOS · Outputs ( Yx , Yx ), (FBOUT, FBOUT): SSTL_2 · External feedback pins (FBIN,FBIN , Pinout Table Pin Name Pin No. I/O Type CLK CLK 13 14 I Yx 3,5,10,20,22,27,29,39,44,46 Yx 2,6,9,19,23,26,30,40,43,47 FBOUT FBOUT 32 33 Feedback output, and , all Yx and Yx outputs. When PWRDWN = 0, the part is powered down and the differential clock outputs , tcycle n+1 Yx ,FBOUT Yx ,FBOUT Figure 1. IBIS Model Output Load PI6CV857 VCLK VDD/2 VCLK VDD


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PDF PI6CV857L 48-Pin 240-Mil PI6CV857LA PI6CV857LAE PS8543D PI6CV857 PI6CV857L PI6CV857LA
Not Available

Abstract: No abstract text available
Text: GND Figure 1. Output Load Test Circuit Yx , FBOUT Yx , FBOUT tcycle n tjit(cc) = tcycle n , ˜) Figure 4. Dynamic Phase Offset Yx Yx Yx , FBOUT Yx , FBOUT tsk(o) Figure 5. Output Skew 7 , CIRCUIT AND SWITCHING WAVEFORMS Yx , FBOUT Yx , FBOUT tcycle n Yx , FBOUT Yx , FBOUT 1 fo tjit(per) = tcycle n 1 fo Figure 6. Period jitter Yx , FBOUT Yx , FBOUT thalf period n+1 thalf period n Yx , FBOUT Yx , FBOUT 1 fo tjit(hper) = thalf period n Figure 7. Half-Period


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PDF IDTCSPT855 CSPT855
1996 - ATMEL 350

Abstract: 5962-87514 AT28C64-15DM/883 transistor smd list at28hc64b-70dm AT28C64-20DM atmel 718 smd code book "SMD Code" SMD CODE list
Text: (SMD Code) Lead Finish 5962-38267 01 M YX Atmel Part Number Speed Case Outline (Atmel , 5962-87514 13 XX AT28C64-35DM/883 5962-87514 13 YX AT28C64-35LM/883 5962-87514 13 ZX AT28C64-35FM/883 5962-87514 14 XX AT28C64-30DM/883 5962-87514 14 YX AT28C64-30LM/883 5962-87514 15 XX AT28C64-25DM/883 5962-87514 15 YX AT28C64-25LM/883 5962-87514 15 ZX AT28C64-25FM/883 5962-87514 16 XX AT28C64-20DM/883 5962-87514 16 YX AT28C64-20LM/883 5962-87514 17


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PDF MILSTD-883, lAT28HC256-90LM/883 AT28HC256-90FM/883 AT28HC256F-90UM/883 AT28HC256F-90DM/883 AT28HC256F-90LM/883 AT28HC256F-90FM/883 ATMEL 350 5962-87514 AT28C64-15DM/883 transistor smd list at28hc64b-70dm AT28C64-20DM atmel 718 smd code book "SMD Code" SMD CODE list
2002 - Not Available

Abstract: No abstract text available
Text: FUNCTIONAL BLOCK DIAGRAM EN 14 Q D 25 Dx CP Yx 13 CP CLR CLR OE 11 1 , I When the clear input is LOW and OE is LOW, the Yx outputs are LOW. When clear input is HIGH , the register on the LOW-to-HIGH transition. Yx EN O I OE Yx I CLR Dx I/O , on the Dx input is transferred to the Yx output on the LOW-to-HIGH clock transition. When the clock enable is HIGH, the Yx outputs do not change state, regardless of the data or clock input transitions


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PDF IDTQS74FCT2823AT/BT IDTQS74FCT2823T 2823AT 2823BT L0201-02,
2006 - PI6CV847

Abstract: No abstract text available
Text: (CLK,CLK) and (FBIN,FBIN): SSTL_2 · Outputs ( Yx , Yx ), (FBOUT, FBOUT): SSTL_2 · External feedback pins , VDDQ/2 Figure 1. IBIS Model Output Load Yx R = 60-Ohm VDD/2 R = 60-Ohm Yx VDD , Yx ,FBOUT Yx ,FBOUT t cycle n t cycle n+1 t jit(cc) = t cycle n - t cycle n+1 Figure 3 , is a large number of samples) Figure 4. Static Phase Offset Yx Yx Yx , FBOUT Yx , FBOUT t , Yx , FBOUT Yx , FBOUT t cycle n Yx , FBOUT Yx , FBOUT 1 fO t jit(per) = t cycle n 1


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PDF PI6CV847 200MHz 24-Pin PI6CV847L PI6CV847LE 173-mil PS8764D PI6CV847
2002 - PC2700

Abstract: PI6CV857 PI6CV857B PI6CV857BA PI6CV857L
Text: ): SSTL_2 · Input PWRDWN: LVCMOS · Outputs ( Yx , Yx ), (FBOUT, FBOUT): SSTL_2 · External feedback pins , Pinout Table Pin Name Pin No. I/O Type CLK CLK 13 14 I Yx 3 , 5 , 10 , 2 0 , 2 2 , 2 7 , 2 9 , 3 9 , 4 4 , 4 6 Yx 2,6,9,19,23,26,30,40,43,47 FBOUT FBOUT 32 , down and output disable for all Yx and Yx outputs. When PWRDWN = 0, the part is powered down and the , Yx ,FBOUT Yx ,FBOUT t cycle n t cycle n+1 t jit(cc) = t cycle n - t cycle n+1 Figure 3


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PDF PI6CV857B PC2700 48-Pin PI6CV857BA PS8639 PC2700 PI6CV857 PI6CV857B PI6CV857BA PI6CV857L
Not Available

Abstract: No abstract text available
Text: _2 • Input PWRDWN: LVCMOS • Outputs ( Yx , Yx ), (FBOUT, FBOUT): SSTL_2 • External feedback pins , Pinout Table Pin Name Pin No. I/O Type CLK CLK 13 14 I Yx 3,5,10,20,22,27,29,39,44,46 Yx 2,6,9,19,23,26,30,40,43,47 FBOUT FBOUT 32 33 Feedback output, and , all Yx and Yx outputs. When PWRDWN = 0, the part is powered down and the differential clock outputs , Yx ,FBOUT Yx ,FBOUT t cycle n t cycle n+1 t jit(cc) = t cycle n - t cycle n+1 Figure 3


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PDF PI6CV857 MO-153F/ED 48-Pin 240-Mil PI6CV857AE PS8464F
2002 - R1M 29

Abstract: PI6CV857 PI6CV857L PI6CV857LA PI6CV857LK
Text: Input PWRDWN: LVCMOS · Outputs ( Yx , Yx ), (FBOUT, FBOUT): SSTL_2 · External feedback pins (FBIN,FBIN , Pinout Table Pin Name Pin No. I/O Type CLK CLK 13 14 I Yx 3 , 5 , 10 , 2 0 , 2 2 , 2 7 , 2 9 , 3 9 , 4 4 , 4 6 Yx 2,6,9,19,23,26,30,40,43,47 FBOUT FBOUT 32 , down and output disable for all Yx and Yx outputs. When PWRDWN = 0, the part is powered down and the , Yx ,FBOUT Yx ,FBOUT t cycle n t cycle n+1 t jit(cc) = t cycle n - t cycle n+1 Figure 3


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PDF PI6CV857L 48-Pin PI6CV857LA PI6CV857LK PS8543A R1M 29 PI6CV857 PI6CV857L PI6CV857LA PI6CV857LK
2001 - Not Available

Abstract: No abstract text available
Text: ): SSTL_2 • Input PWRDWN: LVCMOS • Outputs ( Yx , Yx ), (FBOUT, FBOUT): SSTL_2 • External feedback pins , Pinout Table Pin Name Pin No. I/O Type CLK CLK 13 14 I Yx 3,5,10,20,22,27,29,39,44,46 Yx 2,6,9,19,23,26,30,40,43,47 FBOUT FBOUT 32 33 Feedback output, and , all Yx and Yx outputs. When PWRDWN = 0, the part is powered down and the differential clock outputs , Yx ,FBOUT Yx ,FBOUT t cycle n t cycle n+1 t jit(cc) = t cycle n - t cycle n+1 Figure 3


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PDF PI6CV857 48-Pin PI6CV857A PS8464C
2002 - PLL 02 AG

Abstract: PI6CV855 PI6CV855L
Text: _2 Outputs ( Yx , Yx ), (FBOUT, FBOUT): SSTL_2 External feedback pins (FBIN,FBIN) are used to synchronize the , Yx ,FBOUT Yx ,FBOUT t cycle n t cycle n+1 t jit(cc) = t cycle n - t cycle n+1 Figure 3 , is a large number of samples) Figure 4. Static Phase Offset Yx Yx Yx , FBOUT Yx , FBOUT t , Yx , FBOUT Yx , FBOUT t cycle n Yx , FBOUT Yx , FBOUT 1 fO t jit(per) = t cycle n 1 fO Figure 6. Period Jitter Yx , FBOUT Yx , FBOUT t n+1 half period t half period n 1 fO


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PDF PI6CV855 28-Pin PI6CV855L PS8545A PLL 02 AG PI6CV855 PI6CV855L
Not Available

Abstract: No abstract text available
Text: : LVCMOS Outputs ( Yx , Yx ), (FBOUT, FBOUT): SSTL_2 External feedback pins (FBIN,FBIN) are used to , Pinout Table Pin Name CLK CLK Yx Yx FBOUT FBOUT FBIN FBIN PWRDWN VDDQ AVDD AGND GND Pin No. 13 , Output Power down and output disable for all Yx and Yx outputs. When PWRDWN = 0, the part is powered down , Yx ,FBOUT Yx ,FBOUT t cycle n t jit(cc) = t cycle n - t cycle n+1 t cycle n+1 Figure 3 , number of samples) N Figure 4. Static Phase Offset Yx Yx Yx , FBOUT Yx , FBOUT t sk(o) Figure


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PDF PI6CV857L 48-Pin PI6CV857LA PS8543
2004 - ICS95V842

Abstract: MO-137 0830A
Text: 2. Output Load Test Circuit YX , FB_OUTC YX , FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) ± tc(n , ) Figure 4. Static Phase Offset YX # YX YX , FB_OUTC YX , FB_OUTT t(SK_O) Figure 5. Output Skew YX , FB_OUTC YX , FB_OUTT YX , FB_OUTC YX , FB_OUTT 1 fO t(jit_per) = tC(n) - 1 fO Figure 6. Period Jitter 0830A-09/10/04 7 t ( ) n+1 ICS95V842 Parameter Measurement Information YX , FB_OUTC YX , FB_OUTT t (hper_n+1) t (hper_n) 1 fo t(jit_Hper) = t(jit_Hper_n) - 1 2xfO Figure 7


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PDF ICS95V842 60MHz 220MHz) MO-137 ICS95V842yFLF-T 830A--09/10/04 ICS95V842 MO-137 0830A
2003 - R1M 29

Abstract: PC2700 PI6CV857B PI6CV857BA PI6CV857BAE
Text: Input PWRDWN: LVCMOS · Outputs ( Yx , Yx ), (FBOUT, FBOUT): SSTL_2 · External feedback pins (FBIN,FBIN , Pinout Table Pin Name Pin No. I/O Type CLK CLK 13 14 I Yx 3 , 5 , 10 , 2 0 , 2 2 , 2 7 , 2 9 , 3 9 , 4 4 , 4 6 Yx 2,6,9,19,23,26,30,40,43,47 FBOUT FBOUT 32 , down and output disable for all Yx and Yx outputs. When PWRDWN = 0, the part is powered down and the , Yx ,FBOUT Yx ,FBOUT t cycle n t cycle n+1 t jit(cc) = t cycle n - t cycle n+1 Figure 3


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PDF PI6CV857B PC2700 Pb-fr210987654321 48-Pin PI6CV857BA PI6CV857BAE PS8639B R1M 29 PC2700 PI6CV857B PI6CV857BA PI6CV857BAE
2002 - Not Available

Abstract: No abstract text available
Text: FUNCTIONAL BLOCK DIAGRAM EN 14 Q D 25 Dx CP Yx 13 CP CLR CLR OE 11 1 , Flip-Flop Data Inputs I When the clear input is LOW and OE is LOW, the Yx outputs are LOW. When clear , . Enters data into the register on the LOW-to-HIGH transition. Yx EN O I OE Yx I CLR , is LOW, data on the Dx input is transferred to the Yx output on the LOW-to-HIGH clock transition. When the clock enable is HIGH, the Yx outputs do not change state, regardless of the data or clock


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PDF IDTQS74FCT2823AT/BT IDTQS74FCT2823T 2823AT 2823BT L0201-02,
Not Available

Abstract: No abstract text available
Text: YX , FBOUTC YX , FBOUTT tc(n) tc(n+1) tjit(cc) = tc(n) ± tc(n+1) Figure 3. Cycle-to-Cycle , Phase Offset YX # YX YX , FB_OUTC YX , FB_OUTT t(SK_O) Figure 5. Output Skew YX , FB_OUTC YX , FB_OUTT YX , FB_OUTC YX , FB_OUTT 1 fO t(jit_per) = tC(n) - 1 fO Figure 6. Period Jitter 0718E—11/24/08 7 t ( ) n+1 ICS95V847 Parameter Measurement Information YX , FB_OUTC YX


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PDF ICS95V847 45MHz 233MHz) ICSSSTV16857, ICSSSTV16859 ICSSSTV32852 MO-153 95V847yGLF-T 0718Eâ
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