The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
DC392A-C Linear Technology LTC1628 or LTC3728 Evaluation Kit
DC392A-A Linear Technology LTC1628 or LTC3728 Evaluation Kit
DC392A-B Linear Technology LTC1628 or LTC3728 Evaluation Kit
LF198S Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDSO, Sample and Hold Circuit
LF198AJ8 Linear Technology IC SAMPLE AND HOLD AMPLIFIER, CDIP8, Sample and Hold Circuit
LF198AS Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDSO, Sample and Hold Circuit

xor logic table Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2000 - 4-bit even parity using mux 8-1

Abstract: full subtractor implementation using NOR gate 4096 bit RAM 74 full subtractor full subtractor using mux
Text: Programmable Logic Devices (CPLD), Delta39K, architecture is based on its predecessor, Ultra37000. It is built , SELIN Logic Block 0 CC VCC SELIN GCLK[3:0] Cluster PIM 39 16 Logic Block PIM Logic Block PIM 16 39 Logic Block 7 CC GCLK[3:0] Logic Block 1 CC 39 16 Logic Block PIM Logic Block PIM 16 39 Logic Block 6 CC Logic Block 2 39 16 Logic Block PIM Logic Block PIM 16 39 Logic Block 5 , bit RAM 4096 bit RAM Dual-Port FIFO Logic Block 3 39 16 Logic Block PIM Logic Block PIM


Original
PDF Delta39K Delta39K, Ultra37000. Ultra37128 4-bit even parity using mux 8-1 full subtractor implementation using NOR gate 4096 bit RAM 74 full subtractor full subtractor using mux
sc-fr pc cable

Abstract: 61c16 N2960I N2960N code de hamming 81495A dl411
Text: Signetics Logic Products Product Specification Error Detection and Correction (EDC) Unit 2960 Table 1 , table . The XOR function results in an even parity check bit; the XNOR is an odd parity check bit. Data , check bit generation are contained in Table 7. Check bits are generated as either an XOR or XNOR or 16 of the 32 data bits as indicated in the table . The XOR function results in an even parity check bit , bit generation are contained in Table 11. Check bits are generated as either an XOR or XNOR of 32 of


OCR Scan
PDF 60-fold. 16-Bit 32-Bit sc-fr pc cable 61c16 N2960I N2960N code de hamming 81495A dl411
1994 - CRC-32 LFSR

Abstract: CY7C384 cyclic redundancy check CY7C291A CY7B933 CY7B923 CRC-32 CRC-16 vhdl code CRC XOR four inputs
Text: register. · Involution (A XOR A = 0) · Identity (A XOR 0 = A) Table 1. CRC­16 Register after Zero , can see from Table 4 that the largest XOR to be calculated is that for R1, which contains nine terms. A quick calculation of logic levels required in an FPGA can be made if the widest single-level XOR is known. The Cypress pASIC380 FPGAs can calculate a three-input XOR in a single logic cell. It can , with a 15-ns access time, do exist. Table 5 contains the XOR information for the least-significant


Original
PDF CY7B923 CY7B933 CRC-32 LFSR CY7C384 cyclic redundancy check CY7C291A CRC-32 CRC-16 vhdl code CRC XOR four inputs
2010 - tristate xnor gate

Abstract: tristate xor gate Tri-State Buffer CMOS SLG74LB1G99 tristate xor SLG74LB1G99V xnor cmos SN74LVC1G99 cmos tristate inverter SN74AUP1G99
Text: configured as one of several logic functions · TDFN-8 Package · Low static power consumption IDD = 1A · 3.3V logic including, AND, OR, NAND, NOR, XOR , XNOR, inverter, buffer and MUX. No , input1 0 Figure 11. Tri-State NAND/OR Function Tri-State XOR /XNOR functions available Table 12 , 000-0074LB1G99-11 Page 9 of 17 SLG74LB1G99 Table 13. Tri-State XOR Function Function Tri-State XOR , voltage level; X = don't care Figure 13. Tri-State XOR Function Table 14. Tri-State XOR Function


Original
PDF SLG74LB1G99 000-0074LB1G99-11 tristate xnor gate tristate xor gate Tri-State Buffer CMOS SLG74LB1G99 tristate xor SLG74LB1G99V xnor cmos SN74LVC1G99 cmos tristate inverter SN74AUP1G99
1995 - CRC-32 LFSR

Abstract: CRC-16 and CRC-32 CRC-32 CRC 32 cyclic redundancy check CRC-16 crc32 CY7C384 CY7C291A CY7B933
Text: dependent on XOR combinations of the initial loworder byte of the CRC register Table 4 to calculate , are in order. After the Xi values are calcu Table 4 that the largest XOR 2. Shift the CRC , just calculated. calculate a threeinput XOR in a single logic cell. It Repeat these four steps for , four logic cells would be required to calculate a nineinput XOR . Because a register would be feed Table 5 contains the XOR information for the least ing this XOR tree, and a register would be at the


Original
PDF CY7B923 CY7B933 CRC-16 CRC-32 CRC-32) CY7C384A-1JC CRC-32 CY7C384 CRC-32 LFSR CRC-16 and CRC-32 CRC 32 cyclic redundancy check crc32 CY7C291A
1999 - CRC-32

Abstract: CY27H512 PALCE22V10 "XOR Gates" hamming code hamming code FPGA crc32 lfsr
Text: (A XOR B XOR C = A XOR C XOR B). · Involution (A XOR A = 0). A study of Table 4 reveals two , XOR width of 17, it is not possible to implement this in a single level of logic within current Cypress CPLDs. However, XOR factoring makes it is possible to implement this in two levels of logic . With , R7 and R8, can be calculated in a small PLD like a PALCE22V10. Table 5 contains the XOR , logic , as one would do with a Field Programmable Gate Array (FPGA) or CPLD. From Table 4, the largest


Original
PDF CY7B923/CY7B933 CRC-32 CY27H512 PALCE22V10 "XOR Gates" hamming code hamming code FPGA crc32 lfsr
N2960N

Abstract: N2960I
Text: Signetics Logic Products Product Specification Error Detection and Correction (EDC) Unit 2960 Table 1 , check bit is generated as either an XOR or XNOR of the eight data bits noted by an "X" in the table , for check bit generation are contained in Table 4. Each check bit is generated as either an XOR or XNOR of eight of the 16 data bits as indicated in the table . The XOR function results in an even parity , Signetics Logic Products Product Specification Error Detection and Correction (EDC) Unit 2960 Table 6


OCR Scan
PDF 60-fold. 64-Bit LD03T8IS N2960N N2960I
Not Available

Abstract: No abstract text available
Text: generated as either an XOR or XNOR of the eight data bits noted by an "X" in the table . Control Mode , generated as either an XOR or XNOR of eight of the 16 data bits as indicated in the table . The XOR , modes. an XOR or XNOR or 16 of the 32 data bits as indicated in the table . The XOR function results , Logic Products 2960 Error Detection and Correction (EDC) Unit Table 7. 32-Bit Modified Hamming , bit is generated as either an XOR or XNOR of the sixteen data bits noted by an ” X" in the table


OCR Scan
PDF 60-fold. 64-Bit L003750S
Z8000

Abstract: "hamming code"
Text: XOR or XNOR of eight of the 16 data bits as indicated in the table . The XOR function results in an , check bit generation are contained in Table VII. Check bits are generated as either an XOR or XNOR or 16 of the 32 data bits as indicated in the table . The XOR function results in an even parity check bit , errors are detected. in Table X. Check bits are generated as either an XOR or XNOR TABLE X. 64 , the table . The XOR function results in an even parity check bit, the XNOR in an odd parity check bit


OCR Scan
PDF Am2960 16-Bit Am2960s 32-bit 64-bit Z8000 "hamming code"
PAL 011a

Abstract: PAL VIHH programming pulse 16P2 EPL10P8
Text: : 15V, 20B : 13.5V) to Pin 11 (PGM/OE) Table 2 Feature S1 S2 Cell 0 0 OR 0 1 XOR 1 0 Polarity , It TJl JL CMOS EPL Series 20 A/B RICOH EPL Series 20A/B are field-programmable logic arrays , family. Group I consists of AND-FIXED OR, XOR arrays, (EPL 10P8,12P6,14P4, and 16P2) available in 55ns or 35ns versions. Group II consists of AND-FIXED OR, XOR array (EPL 16P8) and three Registered AND-FIXED OR, XOR arrays (EPL 16RP8,16RP6, and 16RP4). EPL Series 20A/B devices allow users to program by


OCR Scan
PDF 16RP8 16RP6, 16RP4) 16RP6 16RP4 20-Pin PAL 011a PAL VIHH programming pulse 16P2 EPL10P8
PAL 011a

Abstract: Ricoh Electronics
Text: pulse and Vihh (20A : 15V, 20B : 13.5V) to Pin 11 (PGM/OE) Table 2 Feature S1 S2 Cell 0 0 OR 0 1 XOR , utmm CMOS EPL Series 20 A/B CMOS Electronically Programmable Logic RICOH EPL Series 20A/B are field-programmable logic arrays made possible by CMOS EPROM process technology. Two product groups make up the EPL Series 20 A/B family. Group I consists of AND-FIXED OR, XOR arrays, (EPL 10P8,12P6,14P4, and 16P2) available in 55ns or 35ns versions. Group II consists of AND-FIXED OR, XOR array (EPL 16P8) and three


OCR Scan
PDF 16RP8, 16RP6, 16RP4) 16RP8 16RP6 16RP4 16RP4 20-Pin PAL 011a Ricoh Electronics
2009 - JTAG xdp CONNECTOR

Abstract: xdp CONNECTOR 321060-001US ITP700FLEX INTEL embedded processors Core 2 duo
Text: a logic high and the output of the last XOR device in the chain is connected to a pin which is , CPU with all logic except chipset (in that table as "Other Devices") Designing Embedded Systems For , an output from the XOR chain at all times. I/O not in the chain will be active at a given logic , XOR chain input pins with pattern produced via the JTAG boundary scan logic of the attached devices , . 6 3.3 XOR Chains


Original
PDF 321060-001US IEEE1149 JTAG xdp CONNECTOR xdp CONNECTOR 321060-001US ITP700FLEX INTEL embedded processors Core 2 duo
Not Available

Abstract: No abstract text available
Text: COM’L E PAL32VX10/A 24-Pin Versatile with XOR Programmable Array Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS ■Increased logic power - Up to 32 inputs and 10 outputs , the output of the OR logic array. The XOR gate output feeds the input of the D flip-flop. The way In , Logic (PAL®) device which implements a sum-ofproducts transfer function via a user-programmable AND logic array and a fixed OR logic array. Featured are ten highly flexible input/output macrocells which


OCR Scan
PDF PAL32VX10/A 24-Pin 300-mil
PAL32VX10

Abstract: No abstract text available
Text: COM'L PAL32VX10/A 24-Pin Versatile with XOR Programmable Array Logic DISTINCTIVE CHARACTERISTICS Increased logic power - Up to 32 inputs and 10 outputs Advanced Micro Devices Global , macrocell logic diagram , one input of the XOR gate is connected to a single product term, while the second input is connected to the output of the OR logic array. The XOR gate output feeds the input of the D , configuration, the XOR gate on the input of the flip-flop can be used to program the logic polarity of the


OCR Scan
PDF PAL32VX10/A 24-Pin 300-mil PAL32VX10
PAL 011a

Abstract: 16P2 PAL VIHH programming pulse
Text: -Output, 4-Registered AND-OR, XOR array Part Numbering System EPL 16 RP - Electronically Programmable Logic - , (20A : 15V, 20B: 13.5V) to Pin 11 (PGM/OE) Table 2 Feature S1 S2 Cell 0 0 OR 0 1 XOR 1 0 Polarity 1 , KOM ili. 006743 o; CMOS EPL Sériés 20 A/B RICOH EPL Sériés 20A/B are field-programmable logic , family. Group I consists of AND-FIXED OR, XOR arrays, (EPL 10P8,12P6, 14P4, and 16P2) available in 55ns or 35ns versions. Group II consists of AND-FIXED OR, XOR array (EPL 16P8) and three Registered


OCR Scan
PDF 16RP8 16RP6, 16RP4) 16RP6 16RP4 16RP4 20-Pin PAL 011a 16P2 PAL VIHH programming pulse
2005 - "XOR Gate"

Abstract: EPM3064A EPM3128A EPM3256A EPM3512A EPM7128AE EPM7256AE EPM7512AE Applications of "XOR Gate"
Text: depends on whether the output pin macrocell uses its XOR gate as an inverter. Table 4 shows the fast , devices, addresses known device issues, and includes workarounds for those issues. Refer to Table 1. Table 1. MAX 7000AE, MAX 7000B, & MAX 3000A Device Family Issues Issue Affected Devices Specific , Table 1: (1) (2) MAX 7000B I/O Current During Power Sequencing Altera Corporation , I/O pins may source or sink current greater than 300 A. Table 2 describes the two power sequence


Original
PDF 7000AE, 7000B, 7000B 7000AE 7000B "XOR Gate" EPM3064A EPM3128A EPM3256A EPM3512A EPM7128AE EPM7256AE EPM7512AE Applications of "XOR Gate"
2000 - IT8761E

Abstract: 8042 keyboard mouse controller 16c550 to isa slot scheme 16c550 isa slot 8042 kbc IT8761 SERIRQ PC99 intel LPC interface spec 1.0 DMAC-8237
Text: . 5-4 Table 5-3. XOR Chain Order , . 5-4 IT8761E Table 5-3. XOR Chain Order Pin # Signal Name 1 VCC 2 CLK48 3 , . 5-2 Figure 5-2. Logic Diagrams of GPIO1X and GPIO2X , . 6-5 ii IT8761E TABLES Table 4-1. LPC Bus Interface Signals . 4-1 Table 4-2. KBC/Misc. Interface Signals


Original
PDF IT8761E IT8761E 02BSC 50BSC 039REF 00REF 8042 keyboard mouse controller 16c550 to isa slot scheme 16c550 isa slot 8042 kbc IT8761 SERIRQ PC99 intel LPC interface spec 1.0 DMAC-8237
SL4 diode

Abstract: SR330 8 bit half adder 74 TUL5014 DM10900 CD62 CD61 CD60 ZD3,9 Z03 Series
Text: enabled, OPA and OPB select ALU functions Sum, XOR , X + Y, or X • Y (see Figure 11). See Table 4. Table 4 Function ZP CD61 OPA OPB Not Enabled See Table 3 H X X Sum Sum PAR L L L XOR XOR PAR L L H X , . When Comp is at a logic L, Y data is passed. When Comp is at a logic H, Y is complemented. Table 5 , 8-bit adder accessed by two latched Input ports. In addition, various logic operations can also be , – Manufactured from high performance, oxide-Isolated ECL macrocell array. ■Performs all necessary logic and


OCR Scan
PDF DM10900 TUL5014 24-Bit SL4 diode SR330 8 bit half adder 74 TUL5014 CD62 CD61 CD60 ZD3,9 Z03 Series
1999 - "XOR Gate"

Abstract: Applications of "XOR Gate" XAPP313 XOR GATE CoolRunner data sheet for 3 input xor gate MC19 XCR960 SIGNAL PATH designer
Text: macrocells in the logic block. Note that there is also a two-input hardware XOR gate with an input from the , Architecture Each Fast Module consists of four logic blocks with 20 macrocells interconnected by a local ZIA as shown in Figure 2. Each logic block has a fan-in of 36 from the local ZIA. The 32 I/O pins for the Fast Module are equally distributed ­ eight per logic block. Therefore, eight macrocells from each logic block are bonded-out to pins, the other remaining 12 macrocells are buried. XAPP313 (v1


Original
PDF XCR3960 XAPP313 XCR3960 NX5406. nx5406) nx5406 "XOR Gate" Applications of "XOR Gate" XAPP313 XOR GATE CoolRunner data sheet for 3 input xor gate MC19 XCR960 SIGNAL PATH designer
1996 - 4 bit pn sequence generator

Abstract: pn sequence generator direct sequence spread spectrum LFSR 3 bit pn sequence generator code 4 bit LFSR direct sequence spread spectrum transmitter generate pn code gold sequence generator pn sequence generator 32 bit
Text: ) megafunction is based on linear XOR or XNOR feedback logic in which the initial value of the shift register , XOR or XNOR logic and then fed back into the shift register input. The LFSR megafunction is designed , reduces logic usage and optimizes area and performance. Table 2 describes these parameters. Table 2 , ) Specified by user. Feedback logic configuration 2 2 to 32 bits XOR Can be customized for , acquisition process. XOR logic is configured on the received data stream with the various PN sequence phases


Original
PDF
2011 - 5 inputs OR gate truth table

Abstract: 6 inputs OR gate truth table truth table for 7 inputs OR gate 4 inputs OR gate truth table Logic Gates truth table for 4 inputs OR gate psoc inverter of the basic logic gates Digital logic gates Components NOT GATE
Text: of the inputs. There are seven basic logic gates: AND, OR, Inverter (NOT), NAND, NOR, XOR , and XNOR , : 001-50454 Rev. *C Page 3 of 7 Digital Logic Gates PSoC® CreatorTM Component Datasheet Table 1 , inputs. Otherwise, the output is false. Table 6. XOR Truth Table Input 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 , operates as an XOR gate followed by a NOT gate. It has two or more inputs and one output. As shown in Table , PSoC CreatorTM Component Datasheet ® Digital Logic Gates 1.0 Features Industry-standard


Original
PDF
ELLS 110

Abstract: MC10905 DL10 truth table xor gate 74 TD-408 hdl4 76DATA
Text: subset of the 64-bit configuration). Table 1 shows logic levels that must be applied to the slice , -6 outputs for the bottom three devices are rotated (see Table 8) to the XOR gates and rotated back into the , to CBO, pos. 64A) + XOR = 10.7 ns + XOR Data In to Error Detect (Use Table 15) 32 (Dl to SYO, pos , , pos. 64A) = 13.2 ns + XOR + 11 ns = 24.2 ns + XOR Data In to Single Error (SE) Out (Use Table 15) 32 , generate the syndrome bits used in error detection (See Table 4), The GENERATE pin when a HIGH selects the


OCR Scan
PDF MC10905 16-BIT MC10905 50-ohm ELLS 110 DL10 truth table xor gate 74 TD-408 hdl4 76DATA
ve32

Abstract: LSL4 SL4 diode
Text: at a logic L or CD61 Is held at a logic H, no shift operation Is performed: Table 2 Illustrates the 1 , See Table 4. ` ' " Table 4 ZP See Table 3 Sum PAR XOR PAR AND PAR OR PAR CD61 H L L L L OPA X L L H H , L, Y data Is passed. When Comp Is at a logic H, Y is complemented. Table 5 Operation Pass Y , specifications shown in the test table , after thermal equilibrium has been established. The circuit is in a test , Power Supply Drain Current Input Current CD61, X L, Y L , ZL, Cjpg, OPA All Othejs Logic High Output


OCR Scan
PDF DM10900 68VDCto-5 72VDC 50Sto-2 ve32 LSL4 SL4 diode
Not Available

Abstract: No abstract text available
Text: XOR gate on the input of the flip-flop can be used to program the logic polarity of the transfer , indicated in the macrocell logic diagram, one input of the XOR gate is connected to a single product term, while the second input is connected to the output of the OR logic array. The XOR gats output feeds the , ADV MICRO P L A / P L E / A R R A Y S Military Programmable Array Logic 13E D , Programmable Array Logic Conforms to MIL-STD-883, Class B* £ ro < DISTINCTIVE CHARACTERISTICS x


OCR Scan
PDF MIL-STD-883,
1997 - atmel 844

Abstract: F1500AT ATF1500A FIT1500 0609C ATF-1500 programming
Text: configuration. Logic functions are implemented with the OR/ XOR /CASCADE logic structure. Up to 5 product terms , fitter can also use the XOR gate for logic minimization or for polarity control. 8-43 Foldback , specified manually by declaring a foldback logic term node (see node numbers table ) or by using a macro or , Flash-based complex PLD. It has flexible macrocells which allow implementation of complex logic functions , % connectivity between macrocells. This eliminates routing bottlenecks, increases logic utilization and enables


Original
PDF ATF1500/A atmel 844 F1500AT ATF1500A FIT1500 0609C ATF-1500 programming
Supplyframe Tracking Pixel