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wn 537 a transistor Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
equivalent for transistor tt 2222

Abstract: wn 537 a transistor wn 537 transistor 2N6669 2N6690 D105 ic SL 1626 2N6689 7827 Transistor 2N6675
Text: MIL-S-19500/ 537 (USAF) tt October 1980 MILITARY SPECIFICATION SEMICONDUCTOR DEVICE, TRANSISTOR , Force - 11, 19, 85, 99 OLA - ES DLA - ES (Project 5961-F778) V MIl-S-19500/ 537 (USAF) T »stE  , -19500/ 537 (USAF) TABLE T. flmnn A 537 (USAF) 4,0 J. T V X A T transistor types 2N6674 and 2N6675. 13 MIL-S-19500/ 537 (03AF) Symbol


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PDF MIL-S-19500/537 2N6674, 2N6675, 2N6689, 2N6690 MIL-S-19500. ZH6674, N6675 T0-61) equivalent for transistor tt 2222 wn 537 a transistor wn 537 transistor 2N6669 D105 ic SL 1626 2N6689 7827 Transistor 2N6675
wn 537 a fet

Abstract: No abstract text available
Text: (included in /bb(ofo) m£2 ⠀” 1 fcbfoff) - (iA Wn = 0 Operating current (Pin 1)8> H , s 537 SIEMENS BTS 410 F2 Open-Ioad detection ON-state diagnostic condition: Ifa, < A on , PROFET  © OUT ST GND Any kind of load, (f V qnd > '-In * Wn (t + device stays off > Due to , ⠖ à ´ c !3 s b 0 s m a ⠖ P ÜE  ® B S4 0 2 R F T T 1F SIEMENS Smart Highside Power Switch Features ⠀¢ ⠀¢ ⠀¢ ⠀¢ ⠀¢ ⠀¢ ⠀¢ ⠀¢ ⠀¢ ⠀¢ ⠀¢ ⠀¢ ⠀¢ Overload


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PDF O-220AB/5, E3043 Q67060-S6103-A3 BTS307/308 2fi33 wn 537 a fet
interline 925

Abstract: ccd sony super HAD 2 LCC Package
Text: non-adjusting. Applications^ Ultra-compact cameras PC image input Super HAD CCD * Super HAD CCD is a trademark of Sony Corporation. ^ m a g ^ S e n s o j^ h a ra c te ris tic ^ ^ Item Horizontal resolution , diameter: 3.0 mm) NTSC Interline transfer 537 (H) x 597 (V) approx. 320K pixels 500 (H) x 582 (V) approx. 290K pixels 492 (H) x 575 (V) approx. 280K pixels < - 4.90 |nm (H) x 3.15 | wn (V) Horizontal (H , mm (+0.51 %) 4 :3.005 (+ 0 .1 7 % ) 9.4581 MHz < - ICX097AKE 537 (H) x 505 (V) approx. 270K


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PDF 250K-pixel/290K-pixel ICX096AKE/097AKE ICX096AKE/097AKE ICX086AK/087AK, 250K-pixel ICX097AKE 12-pin interline 925 ccd sony super HAD 2 LCC Package
2001 - Not Available

Abstract: No abstract text available
Text: Boundary Scan function Available in a 144-pin (13mm x 13mm) Plastic Ball Grid Array (PBGA) Easily , HSTL I/0 CONTROL OE EREN 5909 drw01 Q0 -Qn (x18 or x9) ERCLK The IDT logo is a registered trademark and the TeraSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL , TEMPERATURE RANGES PIN CON.IGURATIONS (CONTINUED) A1 BALL PAD CORNER A WCS PRS MRS WHSTL LD FF/IR , controls and a flexible Bus-Matching x18/ x9 data flow. These FIFOs offer several key user benefits: ·


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PDF 18-BIT/9-BIT IDT72T1845, IDT72T1855 IDT72T1865, IDT72T1875 IDT72T1885, IDT72T1895 IDT72T1845 IDT72T1855 IDT72T1865
2001 - Not Available

Abstract: No abstract text available
Text: Boundary Scan function Available in a 144-pin (13mm x 13mm) Plastic Ball Grid Array (PBGA) Easily , HSTL I/0 CONTROL OE EREN 5909 drw01 Q0 -Qn (x18 or x9) ERCLK The IDT logo is a registered trademark and the TeraSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL , TEMPERATURE RANGES PIN CONFIGURATIONS (CONTINUED) A1 BALL PAD CORNER A WCS PRS MRS WHSTL LD FF/IR , controls and a flexible Bus-Matching x18/ x9 data flow. These FIFOs offer several key user benefits: ·


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PDF 18-BIT/9-BIT IDT72T1845, IDT72T1855 IDT72T1865, IDT72T1875 IDT72T1885, IDT72T1895 IDT72T1845 IDT72T1855 IDT72T1865
2001 - Not Available

Abstract: No abstract text available
Text: Boundary Scan function Available in a 144-pin (13mm x 13mm) Plastic Ball Grid Array (PBGA) Easily , HSTL I/0 CONTROL OE EREN 5909 drw01 Q0 -Qn (x18 or x9) ERCLK The IDT logo is a registered trademark and the TeraSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL , TEMPERATURE RANGES PIN CONFIGURATIONS (CONTINUED) A1 BALL PAD CORNER A WCS PRS MRS WHSTL LD FF/IR , controls and a flexible Bus-Matching x18/ x9 data flow. These FIFOs offer several key user benefits: ·


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PDF 18-BIT/9-BIT IDT72T1845, IDT72T1855 IDT72T1865, IDT72T1875 IDT72T1885, IDT72T1895 IDT72T1845 IDT72T1855 IDT72T1865
Not Available

Abstract: No abstract text available
Text: NOT TO SCALE i THIRD ANGLE PROJECTION i ALL DIMENSIONS SM N A ME APPROVED: DE T AI L VIEW S C A L E 10 C=GÆ^!MÎI[M HARWIN USA T E L : 603 893 537 6 F A X : 603 893 5396 mi s à ´ h a r w i n . c o m HARWIN E u r o p e ( U K ) T E L : 023 9231 4545 F A X : 023 9231 4590 misôharw i n . co . uk TEL: FAX: HARWIN A s i a +65 6 7 7 9 4909 +65 6 7 7 9 , . UNLESS =  ±5° STATED S/AREA: DRA WN : MCCULLAGH R. S. ADDE MCCULLAGH CUSTOMER


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PDF ZK3609-00
Trompeter Electronics 40 patch panel

Abstract: trompeter 14949
Text: . . - TABLE 1 . - . - " ". DASH DESCRIPTION NO BASIC NOT LOADED 22 J158' S MDUNTED IN THE FDLLDW HOLE PAIRS: 2-34, 3-35, 5-37 , 6-38, 7-39, 9-41, 10-42, 12-44, 13-45, 14-46, 16-4B , -.015 DETAIL A PANEL HOLES NUMBERED AS FOLLOWS; TOP LEFT TO RIGHT 1-32 BDTTDM LEFT TO RIGHT 33-64 , © © © © © .750 © JSIX-64S SPECIAL PATCH PANEL o o A o 32 o 31 30 29 20 27 26 , ELECTRONICS,INC. 6/16/99 MATERIAL I^TV-R4^ SCPECIAL PATCH PANEL REV WN R L CHK ENGR APPR GUW-. j


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PDF 16-4B, HP-304 EIA-310 Trompeter Electronics 40 patch panel trompeter 14949
2004 - PM100CLB060

Abstract: No abstract text available
Text: (unit : mm) UN IGBT FWDi 39.5 39.3 ­5.2 6.5 VN IGBT FWDi 53.7 54.0 ­5.2 6.5 WN IGBT , PM100CLB060 FEATURE a ) Adopting new 5th generation IGBT (CSTBT) chip, which performance is improved by 1µm , VWPC WFO 11. 12. 13. 14. 15. 16. 17. 18. 19. WP VWP1 VNC VN1 NC UN VN WN Fo , INTERNAL FUNCTIONS BLOCK DIAGRAM NC Fo VNC WN Gnd In Gnd VN1 Fo Vcc Gnd In Si Out , 25°C TC = 25°C (Note-1) Ratings 600 100 200 356 ­20 ~ +150 Unit V A A W °C


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PDF PM100CLB060 PM100CLB060
2004 - PM100CLA060

Abstract: No abstract text available
Text: VN IGBT FWDi 53.7 54.0 ­5.2 6.5 WN IGBT FWDi 75.7 76.0 ­5.2 6.5 Bottom view , PM100CLA060 FEATURE a ) Adopting new 5th generation IGBT (CSTBT) chip, which performance is improved by 1µm , . 16. 17. 18. 19. WP VWP1 VNC VN1 NC UN VN WN Fo Apr. 2004 MITSUBISHI WN Gnd In Gnd VN1 Fo Vcc Gnd In Si Out OT NC Gnd WP VWP1 , -1) Ratings 600 100 200 356 ­20 ~ +150 Unit V A A W °C Ratings Unit 20 V 20 V


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PDF PM100CLA060 PM100CLA060
t1al

Abstract: No abstract text available
Text: AND FOR MUST NOT BE HA RWI N USA T E L : 603 893 537 6 F A X : 603 Ö93 5396 m isQharw in.com H A R W I N E u r o p e ( UK ) TEL: 023 9231 4545 F A X : 023 9231 4590 mis@harwin.co.uk HARWIN A s i , PROJECTION j ALL DIMENSIONS IN mm ORDER CODE : PART No. DIM ' A ' PCB , : ! 00 Ï TIN 0 I .65 +0.20 0 , 8 0 ± 0 . 03 n DI M ' A ' (SEE TABLE) RA 15 , - ROCKI NG 2. 3. THIS MATTER DRAWING OR OUT SET AND ANY ARE DRA WN : CUSTOMER REF, SANDY 5


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PDF CW508L t1al
wn 537 a fet

Abstract: wn 537 transistor ty 542 smd transistor 410F2
Text: current (ISO) Current limitation WrtXAZ) Vbb(on) ñON A _(iso) A -(SCr) V 65 4.7 .4 2 V 220 m fi 1.8 A 2.7 A Application · nC compatible power switch with diagnostic feedback for 12 V and 24 V DC , U a + Vs, U a = 1 3 .5 V f?i3>= 2 fi, f?L= 6.6 £2, h= 400 ms, IN= low or high Load current (Short , 1 5 0 °C , 7c = 1 5 0 °C const. /L = 1 .8 A , Z L = 2.3H , 0 Q: Electrostatic discharge capability , .+150 -5 5 .+ 1 5 0 Unit V V A °C 50 W £ as 4.5 1 2 J kV IN: Ves d all other


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PDF CM05I8S BTS307/308 O-22QAB/5, E3043 Q67060-S6103-A3 wn 537 a fet wn 537 transistor ty 542 smd transistor 410F2
2003 - PM100*060

Abstract: optocoupler PC 187
Text: FWDi 39.3 39.5 6.5 ­5.2 VN IGBT FWDi 54.0 53.7 6.5 ­5.2 WN IGBT FWDi 76.0 75.7 6.5 ­5.2 (unit : mm) Br , PM100RLA060 FEATURE a ) Adopting new 5th generation IGBT (CSTBT) chip, which performance is improved by 1µm , . 13. 14. 15. 16. 17. 18. 19. WP VWP1 VNC VN1 Br UN VN WN Fo P 32 14.5 7 2 0.5 13 , INSULATED PACKAGE INTERNAL FUNCTIONS BLOCK DIAGRAM Br Fo VNC WN VN1 VN UN WP VWP1 VWPC , , VCIN = 15V TC = 25°C TC = 25°C TC = 25°C Ratings 600 100 200 356 ­20 ~ +150 Unit V A A W °C (Note


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PDF PM100RLA060 PM100*060 optocoupler PC 187
2004 - PM100RLA060

Abstract: No abstract text available
Text: PM100RLA060 FEATURE a ) Adopting new 5th generation IGBT (CSTBT) chip, which performance is improved by , VN WN Fo Apr. 2004 MITSUBISHI PM100RLA060 FLAT-BASE TYPE INSULATED PACKAGE INTERNAL FUNCTIONS BLOCK DIAGRAM Br Fo Gnd In Gnd VNC WN Fo Vcc Si , ­20 ~ +150 Unit V A A W °C Ratings 600 50 100 228 600 50 ­20 ~ +150 Unit V A A W V A °C Ratings Unit 20 V 20 V 20 V 20 mA BRAKE PART Symbol


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PDF PM100RLA060 PM100RLA060
2005 - Not Available

Abstract: No abstract text available
Text: IGBT FWDi 39.3 39.5 6.5 ⠀“5.2 VN IGBT FWDi 54.0 53.7 6.5 ⠀“5.2 WN IGBT FWDi 76.0 , ⠀¢ WN ⠀¢ Br-VNC Applied between : UFO-VUPC, VFO-VVPC, WFO-VWPC FO-VNC Sink current at UFO, VFO , between : UP-VUPC, VP-VVPC, WP-VWPC UN ⠀¢ VN ⠀¢ WN ⠀¢ Br-VNC Inverter part ⠀“20 ⠉¤ Tj ⠉¤ 125 , between : UP-VUPC, VP-VVPC, WP-VWPC UN ⠀¢ VN ⠀¢ WN ⠀¢ Br-VNC Using Application Circuit of Fig. 8 For , GND ≥0.1µ 20k  ¡ VD Vcc ≥10µ IF Fo WN ≥0.1µ In IF Vcc Fo


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PDF PM100RLA060
2004 - PM100RLB060

Abstract: ac optocoupler igbt out
Text: FWDi 39.5 39.3 ­5.2 6.5 VN IGBT FWDi 53.7 54.0 ­5.2 6.5 WN IGBT FWDi 75.7 76.0 ­5.2 , PM100RLB060 FEATURE a ) Adopting new 5th generation IGBT (CSTBT) chip, which performance is improved by , . WP VWP1 VNC VN1 Br UN VN WN Fo Apr. 2004 MITSUBISHI WN Fo Vcc Si Out OT Gnd In Gnd VN1 Fo Vcc Gnd In Si Out OT Gnd , 25°C (Note-1) Ratings 600 100 200 356 ­20 ~ +150 Unit V A A W °C Ratings 600


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PDF PM100RLB060 PM100RLB060 ac optocoupler igbt out
2003 - Not Available

Abstract: No abstract text available
Text: trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology , RANGES PIN CONFIGURATIONS A1 BALL PAD CORNER A VCC VCC DNC D1 D4 D7 D9 GND GND Q1 Q3 Q5 Q7 Q9 , and falling edges of clock. The device has a flexible x20/x10 Bus-Matching mode and the option to , rising and falling edges of a clock · User selectable Single or Double Data Rate of input and output ports · A user selectable MARK location for retransmit · User selectable I/O structure for HSTL or LVTTL


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PDF 20-BIT/10-BIT IDT72T2098, IDT72T20108 IDT72T20118, IDT72T20128 IDT72T2098 IDT72T20108 IDT72T20118 250MHz
2002 - Not Available

Abstract: No abstract text available
Text: trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology , RANGES PIN CONFIGURATIONS A1 BALL PAD CORNER A V CC V CC NC D1 D4 D7 D9 GND GND Q1 Q3 Q5 Q7 Q9 , write data on both rising and falling edges of clock. The device has a flexible x20/x10 Bus-Matching , to read and write on both rising and falling edges of a clock · User selectable Single or Double Data Rate of input and output ports · A user selectable MARK location for retransmit · User selectable I/O


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PDF 20-BIT/10-BIT IDT72T2098, IDT72T20108 IDT72T20118, IDT72T20128 IDT72T2098 IDT72T20108 IDT72T20118 IDT72T20128 250MHz
2004 - IDT72T20108

Abstract: IDT72T20118 IDT72T20128 IDT72T2098
Text: Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc , TEMPERATURE RANGES PIN CONFIGURATIONS A1 BALL PAD CORNER A VCC VCC DNC D1 D4 D7 D9 , input and output ports of the device. There are a total of four combinations to choose from, Double , asserted after a rising edge of clock, no read or write operations will be possible on the falling edge of that same pulse. An Output Enable (OE) input is provided for high-impedance control of the outputs. A


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PDF 20-BIT/10-BIT IDT72T2098 IDT72T20108 IDT72T20118 IDT72T20128 250MHz 110MHz 500Mb/s IDT72T20108 IDT72T20118 IDT72T20128 IDT72T2098
2009 - D13-T6

Abstract: IDT72T20108 IDT72T20118 IDT72T20128 IDT72T2098 Q11-R14
Text: TeraSync is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE , BALL PAD CORNER A VCC VCC DNC D1 D4 D7 D9 GND GND Q1 Q3 Q5 Q7 , ports of the device. There are a total of four combinations to choose from, Double Data Rate to Double , after a rising edge of clock, no read or write operations will be possible on the falling edge of that same pulse. An Output Enable (OE) input is provided for high-impedance control of the outputs. A read


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PDF 20-BIT/10-BIT IDT72T2098 IDT72T20108 IDT72T20118 IDT72T20128 250MHz 110MHz 500Mb/s D13-T6 IDT72T20108 IDT72T20118 IDT72T20128 IDT72T2098 Q11-R14
2002 - IDT72T20108

Abstract: IDT72T20118 IDT72T20128 IDT72T2098
Text: Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND , CONFIGURATIONS A1 BALL PAD CORNER A VCC VCC DNC D1 D4 D7 D9 GND GND Q1 Q3 , . There are a total of four combinations to choose from, Double Data Rate to Double Data Rate (DDR to DDR , and WCLK respectively, never on the falling edge. If REN or WEN is asserted after a rising edge of , Enable (OE) input is provided for high-impedance control of the outputs. A read Chip Select (RCS) input


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PDF 20-BIT/10-BIT IDT72T2098, IDT72T20108 IDT72T20118, IDT72T20128 IDT72T2098 IDT72T20118 250MHz IDT72T20108 IDT72T20118 IDT72T20128 IDT72T2098
2003 - Not Available

Abstract: No abstract text available
Text: IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync is a , CORNER A VCC VCC DNC D1 D4 D7 D9 GND GND Q1 Q3 Q5 Q7 Q9 , different data rates on the input and output ports of the device. There are a total of four combinations to , falling edge. If REN or WEN is asserted after a rising edge of clock, no read or write operations will be , high-impedance control of the outputs. A read Chip Select (RCS) input is also provided for synchronous enable


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PDF 20-BIT/10-BIT IDT72T2098 IDT72T20108 IDT72T20118 IDT72T20128 250MHz 500Mb/s drw36
2002 - Not Available

Abstract: No abstract text available
Text: trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology , RANGES PIN CONFIGURATIONS A1 BALL PAD CORNER A VCC VCC DNC D1 D4 D7 D9 GND GND Q1 Q3 Q5 Q7 Q9 , and falling edges of clock. The device has a flexible x20/x10 Bus-Matching mode and the option to , rising and falling edges of a clock · User selectable Single or Double Data Rate of input and output ports · A user selectable MARK location for retransmit · User selectable I/O structure for HSTL or LVTTL


Original
PDF 20-BIT/10-BIT IDT72T2098, IDT72T20108 IDT72T20118, IDT72T20128 IDT72T2098 IDT72T20108 IDT72T20118 250MHz
2002 - Not Available

Abstract: No abstract text available
Text: registered trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device , INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATIONS A1 BALL PAD CORNER A V CC V CC NC D1 D4 D7 D9 GND , device has a flexible x20/x10 Bus-Matching mode and the option to select Single or Double Data clock , Bus-Matching on both read and write ports · Ability to read and write on both rising and falling edges of a clock · User selectable Single or Double Data Rate of input and output ports · A user selectable MARK


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PDF 20-BIT/10-BIT IDT72T2098, IDT72T20108 IDT72T20118, IDT72T20128 IDT72T2098 IDT72T20108 IDT72T20118 IDT72T20128 250MHz
2003 - 72T7285

Abstract: 72T7295 IDT72T72105 IDT72T72115 IDT72T7285 IDT72T7295
Text: Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc , COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATION A1 BALL PAD CORNER A V CC D60 , of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the , data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access


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PDF 72-BIT IDT72T7285, IDT72T7295, IDT72T72105, IDT72T72115 IDT72T7285 IDT72T7295 IDT72T72105 drw43 72T7285 72T7295 IDT72T72105 IDT72T72115 IDT72T7285 IDT72T7295
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