The Datasheet Archive

Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
0484090001 0484090001 ECAD Model Molex USB Connector,
0483910001 0483910001 ECAD Model Molex USB Connector,
0484080003 0484080003 ECAD Model Molex USB Connector
0483910003 0483910003 ECAD Model Molex USB Connector
0685324462 0685324462 ECAD Model Molex USB Connector,
0676433911 0676433911 ECAD Model Molex USB Connector

vl-bus Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1993 - SCSI 2 connector

Abstract: E-Vision User Guide vl-bus 8018g vlbus BT-445S bay26
Text: registered trademarks of their respective companies. Section 1: introduction VL-Bus , Allowed . .2-5 VL-Bus Clock Speed , . .2-22 VL-Bus n n Appendix A: Internal Diagnostics List of Figures l-l. The BT-445s Block , VL-Bus Clock Speed . 2-6 2-3. The Host I/O , =445S AD V A N T A G E S , CO N T I N U E D A VL-Bus ti BusLogic DMA Bus Master SCSI


Original
PDF I29193 SCSI 2 connector E-Vision User Guide vl-bus 8018g vlbus BT-445S bay26
vl-bus

Abstract: No abstract text available
Text: operates as an active high level-triggered interrupt. VL-Bus Interface The 64300 / 301 operates as a 32-bit target on the VL-Bus. It has an optimized direct pin-to-pin connection for all VL-Bus signals to , ( VL-BUS ). Direct interfaces to popular 80486DX, 80486DX2, 80486SX, and 80386D X , processors are also , cycles are not supported The VGA ROM is supported via the ISA bus connector. When a VL-Bus memory cycle , an SMEMR# or SMEMW# to the ROM. The end of the cycle is monitored on the VL-Bus by the 64300 / 301 at


OCR Scan
PDF 32-bit 16-bit 64x64 32x32 vl-bus
1997 - vl-bus

Abstract: circuit diagram of 16-1 multiplexer and explain VESA Video Electronics Standards Association Local Bus ADR30 compaq 7500 7474 D flip-flop circuit diagram
Text: page mode (EDO) DRAM and VL-BusTM · Circuit examples of VL-Bus devices Use This manual assumes , immediately after power-on for devices having reset function. VESA and VL-Bus are trademarks of Video , pertain to the VL-Bus are presented as operation concepts and not as direct operations. Use these concepts , . 12 CHAPTER 2 OVERVIEW OF CONNECTION BETWEEN HYPER PAGE MODE (EDO) DRAM AND VL-Bus . 13 2.1 VL-Bus


Original
PDF M11296EJ2V0AN00 vl-bus circuit diagram of 16-1 multiplexer and explain VESA Video Electronics Standards Association Local Bus ADR30 compaq 7500 7474 D flip-flop circuit diagram
Not Available

Abstract: No abstract text available
Text: output is used to reset all external devices connected to the VL-bus. System Interfaces 4-1 , Signal Name: RSTDRV Asserting the RESET input System Reset ISA Reset VL-Bus Reset Signal Name: V , Re-initializes the VL-bus target to its reset state. After enabling the VL-bus interface, VL RST should be asserted and deasserted before using the VL-bus. Power-On Reset Power-on reset is invoked by asserting , Controller Enabled Not all pins available until programmed VL-Bus Controller Disabled ROM


OCR Scan
PDF lanSC400 lanSC410
TCK9004

Abstract: T306F tvga 386SX chipset 640x400 el display Tvga9200cxr 0636 FL AA8M vl-bus 486DX symphony chip set motherboard
Text: Single-chip solution for IBM PC/AT 32-bit VESA Local Bus ( VL-Bus ) Integrated 24-bit true color DAC Supports up , solution. Compatibility with the VL-Bus standard provides a video subsystem design path for future , applications Provides high performance and cost savings M 386SX/DX Of 486SX/DX VL-Bus , zero-wait state direct memory write, faster base DRAM clock rates, 2 MB linear addressing, and 32-bit VL-Bus , . Linear addressing eliminates bank switching overhead for high resolution drivers. A VL-Bus inter face


OCR Scan
PDF TVGA9200CXr 32-bit 24-bit 512Kx8 256Kx4 16-bit 80/132-colum TCK9004 T306F tvga 386SX chipset 640x400 el display 0636 FL AA8M vl-bus 486DX symphony chip set motherboard
1998 - free crt monitor block diagram

Abstract: Intel 486 DX SPC8110 SPC8110F0A 486DX vl-bus MDB2 mda Signal Generator
Text: -bit PCI or VL-BusTM Interface q 1024KB display memory in two 256Kx16 self-refresh DRAM (asymmetrical or , standards: 486DX local bus interface, VL-Bus interface, and PCI interface, It has a one-stage buffer for , names correspond to the default VL-BusTM configuration. Pin placement subject to change. 6 MVSS , = Power q CPU-Intel486/ VL-Bus Interface Pin Name I/O Pin No. Function ADR[31:2] I 20-3, 206-203, 200-193 VL-Bus Address inputs. DAT[31:0] I/O 22-29, 34-41, 51, 55-61


Original
PDF PF766-03 SPC8110F SPC8110F0A 470mW free crt monitor block diagram Intel 486 DX SPC8110 486DX vl-bus MDB2 mda Signal Generator
vl-bus

Abstract: vlbus intel 486 dx 33mhz mda Signal Generator Intel 486 DX
Text: 32-bit PCI or VL-BusTM Interface · 1024KB display memory in two 256Kx16 self-refresh DRAM , standards: 486DX local bus interface, VL-Bus interface, and PCI interface, It has a one-stage buffer for , : Pin names correspond to the default VL-BusTM configuration. Pin placement subject to change. F , CPU-lntel486/ VL-Bus Interface Pin Name ADR[31:2] DAT[31:0] I/O I I/O Pin No. 20-3,206-203, 200-193 22-29,34-41, 51,55-61, 65-72 30,43,50,62 31 48 44 45 207 46 47 202 VL-Bus Address inputs. VL-Bus Data inputs


OCR Scan
PDF PF766-03 SPC8110Foa SPC81 SPC8110 470mW SPC8110F QFP8-208 QFP22-208 vl-bus vlbus intel 486 dx 33mhz mda Signal Generator Intel 486 DX
LCD EPSON 640 x 200

Abstract: No abstract text available
Text: self-refresh DRAM. ■FEATURES • Hardware VGA Compatible • 32-bit PCI or VL-Bus™ Interface â , three standards: 486DX local bus interface, VL-Bus interface, and PCI interface, It has a one-stage , . Note: Pin names correspond to the default VL-Bus™ configuration. Pin placement subject to change , / VL-Bus Interface I/O Pin No. ADR[31:2] I 20-3,206-203, 200-193 VL-Bus Address inputs. DAT[31:0] I/O 22-29,34-41, 51,55-61, 65-72 VL-Bus Data inputs. These lines are driven by


OCR Scan
PDF PF766-03 SPC81 SPC8110F QFP8-208 QFP22-208 LCD EPSON 640 x 200
74HTC244

Abstract: TCK9002 TCK9004 640X400 Stn 640x200 mono 3c509 Tvga 386SX chipset Hsync Vsync RGB LCD laptop TVGA9100B
Text: Benefits Provides a versatile and high-performance solution. Compatibility with the VL-Bus standard and PI , hardware performance enhancements: Supportforthe VL-Bus specification and Intel's PI interface B uilt-in , PC/AT bus, Micro Channel bus, VL-Bus and PI bus by setting or resetting the configuration bits during , other chip signals are also redefined or redesignated for VL-Bus and PI bus. Please refer to the VL-Bus , W T f lt t H T 015-D O (READ) Figure 6. 386DX VL-Bus Timing Type A Transfer Table 9


OCR Scan
PDF TLCD9100B 16-bit 640x480 65BSC PFP160 74HTC244 TCK9002 TCK9004 640X400 Stn 640x200 mono 3c509 Tvga 386SX chipset Hsync Vsync RGB LCD laptop TVGA9100B
1996 - ARK1000PV

Abstract: vesa local bus video bios vesa local bus ARK LOGIC VGA ramdac addressing modes of pentium vl-bus 486 system bus Graphics Accelerator vesa local bus design
Text: ARK1000PV ARK1000PV PCI/ VL-BUS GUI Accelerator General Description The ARK Logic ARK1000PV is the newest in video acceleration technology on the market today. Its superior features and lightening , million colors, PCI/VESA VL-BUS interface, and comprehensive manufacturing support, the ARK1000PV is the , · Features · · · · Glueless PCI LOCAL BUS Interface (rev 2.0) Direct 32-bit VESA VL-BUS , ) Interface Complete BIOS and GUI Drivers support Complete PCI/ VL-BUS PC board layout and manufacturing


Original
PDF ARK1000PV ARK1000PV 32-bit 160-pin ARK1000PVRevA121495 vesa local bus video bios vesa local bus ARK LOGIC VGA ramdac addressing modes of pentium vl-bus 486 system bus Graphics Accelerator vesa local bus design
ISA bus VGA

Abstract: sbc 486 vl-bus IA 171 vlbus
Text: /93 Pin names shown indicate VL-Bus connections Pin names in brackets <.> indicate ISA bus , Description System Data Bus. CPU Direct/ VL-Bus Interface In 32-bit CPU Local Bus designs these data , Low Description CPU Direct/ VL-Bus Interface (continued) Byte Enable 0. Indicates data transfer , Address Bus In both VL-Bus and 32-bit CPU address interfaces the pins are connected direcdy to the bus , Description CPU Direct/ VL-Bus Interface (continued) Reset. Connect directly to the system reset signal


OCR Scan
PDF GPI02 ISA bus VGA sbc 486 vl-bus IA 171 vlbus
S3 TRIO 64

Abstract: ld18 st ide controller vl-bus ADR30 6560B LA06 1F0H-1F7H configuration pio 1F0H-1F7H LD08
Text: # DD[0.15] VL-BUS CON RDYRTN# GND IRQ9 BRDY# BLAST# ID0 ID1 GND LCLK VDC LBS16


Original
PDF 6560B 6560B CS37XN S3 TRIO 64 ld18 st ide controller vl-bus ADR30 LA06 1F0H-1F7H configuration pio 1F0H-1F7H LD08
promotion 6410

Abstract: Alliance semiconductor promotion 1995 YUV planar packed format vga crtc P105 P108 TQD344T cga to vga converter 3C011 planar YUV display input
Text: .17 5.1 PCI-bus host 5.2 VL-bus , .17 Table 5.3 VL-bus host Table 5.4 DRAM , , read data.29 Waveform 8.2.3 VL-bus timing: ADS, LDEV , timing: Waveform 8.2.6 VL-bus timing: LRDY delay.33 Waveform 8.2.7 VL-bus timing: read data


OCR Scan
PDF ProMotion-6410â 00DU235 ProMotion-6410 DDDDEI76 promotion 6410 Alliance semiconductor promotion 1995 YUV planar packed format vga crtc P105 P108 TQD344T cga to vga converter 3C011 planar YUV display input
1997 - 1F0H-1F7H configuration pio

Abstract: S3 TRIO 64 HT6560A HT6560B DAT00 6560B DD15 LD11 LD12 LD04
Text: ADR04 WBACK# BE0# VDC BE1# BE2# GND BE3# ADS# DD[0.15] VL-BUS CON RDYRTN# GND IRQ9


Original
PDF HT6560B HT6560A HT-6560B/C CS37XN 1F0H-1F7H configuration pio S3 TRIO 64 HT6560B DAT00 6560B DD15 LD11 LD12 LD04
TGUI9400CXi

Abstract: AM 5766 analog 486DX symphony chip set Tvga9200cxr TGUI9400 TGUI9400CX T304L 512kx4 Tvga 3728 lx data
Text: the PCI Rev. 2 and the VL-Bus 2.0 specifications. The TGUI9420DGi significantly boosts graphics perfor , -bit VL-Bus (up to 50 MHz) "Glueless" connection to PCI rev. 2.0 (33 MHz) Supports VESA Display Power , MDA 208-pin PQFP package VL-Bus or PCI Bus Figure 1. TGUI9420DGÌ Application Diagram T R ID E N , TGUI9420DGÌ directly supports VL-Bus and PCI bus interfaces. Both interfaces are 32-bits wide and require no glue logic. VL-Bus speeds up to 50 MHz are supported. PCI bus speeds up to 33 MHz are supported. The


OCR Scan
PDF TDD2162 TGUI9420DGÌ TGUI9420DGi 32-bit 24-bit TGUI9400CXi TVGA9200CXr AM 5766 analog 486DX symphony chip set TGUI9400 TGUI9400CX T304L 512kx4 Tvga 3728 lx data
ADR05

Abstract: 50 pins ide connector S3 TRIO 64 1F0H-1F7H ADR30 vl-bus ide controller DAT12 LD31 ADR27
Text: LEADS# LBS16# VL-BUS CON S3 DAT00 DAT02 DAT04 DAT06 DAT08 GND DAT10 DAT12 VDC DAT14


Original
PDF
mda to vga converter

Abstract: cga to vga converter vl-bus promotion 6410 3E7T 15 pins vga to video converter diagram promotion mmui
Text: .0 - VESA VL-busTM - 2 13M B/second peak bandw idth - 1MB, 2MB, 4MB display m em ory - X4, x8, X l6 , ProMotion-6410 interfaces directly to PCI Bus vZ.O or to VESA VL-bus , without external glue logic. A , strap is undriven or pulled HIGH, the chip configures itself in VL-bus mode. Memory-mapped command , -6410 Clueless VL-bus /ROM interface A0R(31:02] OAT[31:00] A ProMotion-6410 CE ^ VL'bus Control WE , -6410 Glueiess PCI/ROM interface. In VL-bus mode, ProMotion-6410 decodes VGA BIOS addresses and drives a ROM


OCR Scan
PDF pn-64 64-bit x1200 1600X1200 1280X1024 1152x864 1024X768 800X600 640X480 mda to vga converter cga to vga converter vl-bus promotion 6410 3E7T 15 pins vga to video converter diagram promotion mmui
dac 344C

Abstract: cga to vga converter circuits DQ0Q11Q Alliance semiconductor promotion IBM vga registers vl-bus promotion 3210 planar YUV display vlbus
Text: . 14 PCI Configuration Registers. 15 VL-Bus , and Reset Tim ing. 24 VL-Bus Timing: ADS, L D E V . 25 VL-Bus Timing: LRDY D elay. 26 VL-Bus Timing: Read D a ta .26 VL-Bus Timing , . Glueless VL-Bus /ROM Interface ProMotion-3210 A ADR[31:02] DAT[31:00] ROM EN ÜÉ CE ROM


OCR Scan
PDF ProMotion-3210TM 0034L ProMotion-3210 Promotion-3210TM DQ0Q11Q 2E200Q0 dac 344C cga to vga converter circuits Alliance semiconductor promotion IBM vga registers vl-bus promotion 3210 planar YUV display vlbus
1996 - Hsync Vsync VGA

Abstract: PCI-A14 65550 CHIPS VGA 65545 486 motherboard schematic CPU-180 CPU-191 486dx isa bios vl bus PCI-B24
Text: Standards Association. VL-Bus is a trademark of Video Electronics Standards Association. Weitek is a , . 4 2.3 VL-Bus BIOS Interface , such as the size of the VL-Bus address space, power management, 3.3V or 5V logic levels (one or the , (28 bits if the GPIO pins are not used) on the VL-Bus (PCI allows the full 32 address bits to be decoded since addresses are multiplexed with data). For the VL-Bus , this allows the chip to decode its


Original
PDF HiQV32TM AN107 Hsync Vsync VGA PCI-A14 65550 CHIPS VGA 65545 486 motherboard schematic CPU-180 CPU-191 486dx isa bios vl bus PCI-B24
wd9710

Abstract: MRC D30
Text: .9 MULTIPLEXED VL-BUS INTERFACE .10 DE-MULTIPLEXED VL-BUS IN T E R F A C E .11 MULTIPLEXED VESA VL-BUS WITH EXTERNAL RAMDAC INTERFACE (1 6 -B IT , .44 VESA VL-BUS CONNECTIONS


OCR Scan
PDF 64-Bit 79-890018-000-P3 171fl22a WD9710 208-pin 200-PIN wd9710 MRC D30
1997 - SCHEMATIC mda VGA board

Abstract: 241-G4 R-640 SCHEMATIC mda VGA 486dx schematic diagram LCD monochrome 14 pin LG lcd monitor power supply circuit diagram crt monitor block diagram lg 15 b639 RIO 1R1
Text: displays. s KEY FEATURES · Hardware VGA compatible · 32-bit PCI, VL-Bus or 486DX local bus direct , SPC8110F0A s VL-BUS SYSTEM BLOCK DIAGRAM Shown with 1024 KB memory option 32bit VL-BUS LOOP2 , following three standards: Intel486 DX local bus interface, VL-Bus interface and PCI interface. It has a , 20-3, 206-203, 200-193 Unused VL-Bus Address inputs. These pins should be tied high in PCI mode , 11 GRAPHICS SPC8110F0A Intel486/ VL-Bus Pin Name Type Output Type Pin No


Original
PDF SPC8110F0A SPC8110F0A SPC8110 32-bit 486DX 512KB 1024KB X07-DS-001-21 SCHEMATIC mda VGA board 241-G4 R-640 SCHEMATIC mda VGA 486dx schematic diagram LCD monochrome 14 pin LG lcd monitor power supply circuit diagram crt monitor block diagram lg 15 b639 RIO 1R1
F65548

Abstract: f65548 a RCD testers 32KHZ vl-bus 2DLF AD312
Text: nS Note: f VL-Bus timing is compatible with VL-Bus Specification 2.0. 50 MHz VL-Bus operation assumes BVCC and IVCC both at 5V. VL-Bus operation at 3.3V is limited to 40 MHz (refer to the VL-Bus 2.0 , # change 1 3 1 - 20 nS BEn#, AD31-2, M/IO#, W/R# LDEV# Valid Tldv \ «—Tldv ( VL-Bus LDEV


OCR Scan
PDF 208-Pin Gc145b F65548 f65548 a RCD testers 32KHZ vl-bus 2DLF AD312
F65548

Abstract: 32KHZ
Text: Clock Sync 5 - i nS Note: f VL-Bus timing is compatible with VL-Bus Specification 2.0. 50 MHz VL-Bus operation assumes BVCC and IVCC both at 5V. VL-Bus operation at 3.3V is limited to 40 MHz (refer to the VL-Bus 2.0 specification for 33 MHz timing details). Note: The typical input capacitance on LCLK is lOpF , \ «—Tldv ( VL-Bus LDEV# Timing 65548 AC TEST CONDITIONS Symbol Notes 3.3 Volt Signaling 5VoltSignaling


OCR Scan
PDF F65548 208-Pin 32KHZ
THx 206

Abstract: THx 208 vl-bus 14.1 xga 30 pin vlbus thx 203 h
Text: : Pin names in Table J-1 are for '486 or VESA® VL-BusTM implementations. When configuring the CL-GD7548 , 1 1 1 1 1 1 1 Table J-1. Pin-Scan Order CL-GD7548 Pin Names for '486 Bus or VESA VL-Bus , .) CL-GD7548 Pin Names for '486 Bus or VESA VL-Bus Interfaces D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 , .) CL-GD7548 Pin Names for '486 Bus or VESA VL-Bus Interfaces D1 DO S L E E P # / ZVPCTL O S C / XVCLK Pin , Pin Names for '486 Bus or VESA VL-Bus Interfaces FP10 FP11 FP12 FP13 FP14 FP15 F P 1 6 /F C P 2 F P 1


OCR Scan
PDF CL-GD7548 CL-GD7548 THx 206 THx 208 vl-bus 14.1 xga 30 pin vlbus thx 203 h
1996 - ARK2000PV

Abstract: vesa local bus design 8-bit VGA ramdac vesa vga connector 8 pin description vesa local bus "64-bit graphics engine" ramdac VGA ramdac ARK LOGIC
Text: burst cycles Direct 32-bit VESA VL-BUS Interface for Pentium, 486 DX2, DX, and SX series Advanced , ) Support VESA DDCTM for MicrosoftTM Plug and Play TM TM definition Complete PCI/ VL-BUS PC board layout


Original
PDF ARK2000PV ARK2000PV 64-Bit ARK2000PVuses 32-bit 208-pin ARK2000PVRevA121495 vesa local bus design 8-bit VGA ramdac vesa vga connector 8 pin description vesa local bus "64-bit graphics engine" ramdac VGA ramdac ARK LOGIC
Supplyframe Tracking Pixel