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Part Manufacturer Description Datasheet Download Buy Part
LTC1746IFW#TR Linear Technology IC ADC SMPL 14BIT 25MSPS 48TSSOP
LTC1742CFW#TR Linear Technology IC ADC SMPL 14BIT 65MSPS 48TSSOP
LTC2632-LMI8#TRPBF Linear Technology IC 8-BIT DAC, PDSO8, PLASTIC, LEAD FREE, MO-193, TSOT-8, Digital to Analog Converter
LTC2632-HMI10#TRPBF Linear Technology IC 10-BIT DAC, PDSO8, PLASTIC, LEAD FREE, MO-193, TSOT-8, Digital to Analog Converter
LTC2632-LMX8#TRMPBF Linear Technology IC 8-BIT DAC, PDSO8, PLASTIC, LEAD FREE, MO-193, TSOT-8, Digital to Analog Converter
LTC2632-LMI10#TRPBF Linear Technology IC 10-BIT DAC, PDSO8, PLASTIC, LEAD FREE, MO-193, TSOT-8, Digital to Analog Converter

vhdl coding for analog to digital converter Datasheets Context Search

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SPICE As An AHDL

Abstract: analog to digital converter vhdl coding digital to analog converter vhdl coding vhdl coding for analog to digital converter vhdl code for digital to analog converter vhdl code for All Digital PLL IEEE PROGRAMS OR ENGINEERING STUDENT WITH vhdl electronic workbench VHDL code for dac IR1167 spice
Text: compatibility be the starting point for analog extensions to VHDL ? THE Requirements Of An AHDL A variety of , simulator. 13) Uses the same language for both analog and digital models to support continuous time ( analog , addition of analog extensions to VHDL or for adding VHDL as an extension to the mixed mode capabilities now , to various analog (time and temperature, differential equations) and digital (event scheduling , level (system, behavioral, or transistor) ADDING SPICE BASED ANALOG EXTENSIONS TO VHDL The following


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vhdl DTMF

Abstract: No abstract text available
Text: T em ic S e m i c o n d u c t o r s Mixed Analog / Digital Capability The ability to combine , , familiar to users of gate arrays or PLAs. These analog and digital cells are available in a variety of tech , the perceived risk of analog and digital , standard cell ASIC developments, bringing the technology to , work, customers may interface at any Filter Analog Digital desired level. For example, the customer often designs the digital sections and leaves the analog and final integration to TEMIC Semiconductors


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1999 - X9009

Abstract: verilog code for BPSK qpsk implementation using verilog qpsk modulation VHDL CODE branch metric 2 bit address decoder coding using verilog hdl BPSK modulation VHDL CODE verilog code for branch metric unit branch metric unit VHDL coding verilog code for digital modulation
Text: code version of the core, available at extra cost, allows for easy adaptation to a wide variety of , . For the EDIF Netlist format a setting for the parameters has to be submitted before the netlist can be , CAST so they can provide you with an accurate response to , and quote for your requirements , documentation Design File Formats EDIF Netlist, VHDL RTL available extra Constraints File decoder.ucf Verification VHDL testbench Instantiation Templates VHDL , Verilog Reference designs & None application notes


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PDF V50-6 X9009 verilog code for BPSK qpsk implementation using verilog qpsk modulation VHDL CODE branch metric 2 bit address decoder coding using verilog hdl BPSK modulation VHDL CODE verilog code for branch metric unit branch metric unit VHDL coding verilog code for digital modulation
2000 - 5 to 32 decoder using 3 to 8 decoder vhdl code

Abstract: branch metric BPSK modulation VHDL CODE verilog code for BPSK 5 to 32 decoder using 3 to 8 decoder verilog qpsk modulation VHDL CODE QPSK using xilinx vhdl code for modulation X9009 Viterbi Decoder
Text: for easy adaptation to a wide variety of applications. The Viterbi Decoder netlist can also be , parameters has to be submitted before the netlist can be provided. Ask CAST, Inc. for details. The Viterbi , with an accurate response to , and quote for your requirements. Implementation Issues 9 , volume do you expect to ship of the product that will use this core? _ 1. Coding rate (R , SpartanTM-II, VirtexTM, and VirtexTM-E devices Soft Decision Decoder Trace-back method for survivor memory


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2005 - vhdl coding for analog to digital converter

Abstract: analog to digital converter vhdl coding analog to digital converter vhdl coding on soft digital to analog converter vhdl coding CORE8051 vhdl code for digital to analog converter 4460 MOSFET ieee embedded system projects eeprom tutorial ADC rtl code
Text: -bit successive approximation register (SAR) analog to digital converter (ADC) with frequencies up to 600 ksps , library that enables you to manually code a testbench for analog signals. Manually coding a testbench , to digital converter (ADC), and a system frequency of 20 MHz (Figure 1-2 on page 7). The example , coding . To reserve the time slots for jump sequences, you can specify the number in "Use x slots for , tool to simulate the analog signals from the Analog System Builder. Here is sample VHDL code that


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2006 - 4 bit binary multiplier Vhdl code

Abstract: system generator matlab ise rgb yuv vhdl rgb yuv vhdl gray color space converter YUV RGB ITU-R BT.709 conversion of binary data into gray code in vhdl IBM 2568 vhdl code for matrix multiplication C 6492-0 rgb to ycbcr four matrix multipliers
Text: -bit linear-light coding performs poorly for images to be viewed [Ref 2]. 12 or 14 bits per component are necessary , gray background on Figure 3. The Use fabric for adders checkbox, corresponding to the FABRIC_ADDS VHDL , Generator testbench is also provided to visually inspect output results. The code is parameterizable for , value for the R, G, B outputs COFFSET Integer 0 to 2OWIDTH-1 Offset value for the chroma (Cr , ROFFSET Integer 0 to 2OWIDTH-1 Offset value for the R output GOFFSET Integer 0 to


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PDF XAPP931 prov7822-4, JTC1/SC29/WG11 4 bit binary multiplier Vhdl code system generator matlab ise rgb yuv vhdl rgb yuv vhdl gray color space converter YUV RGB ITU-R BT.709 conversion of binary data into gray code in vhdl IBM 2568 vhdl code for matrix multiplication C 6492-0 rgb to ycbcr four matrix multipliers
2006 - 4 bit binary multiplier Vhdl code

Abstract: DSP48 XAPP930 rgb to ycbcr four matrix multipliers color space converter vhdl rgb ycbcr x93003 XC4VSX35 FF668 FG320 SG16
Text: -bit linear-light coding performs poorly for images to be viewed [Ref 2]. 12 or 14 bits per component are necessary , . The Use fabric for adders checkbox, corresponding to the FABRIC_ADDS VHDL parameter, controls whether , Application Note: Virtex-4, Virtex-II, Virtex-II Pro, Spartan-3 R Color-Space Converter : RGB to , Generator testbench is also provided to visually inspect output results. The code is parameterizable for , YMAX Integer 0 to 2OWIDTH-1 Clipping value for the luma (Y) output YMIN Integer 0 to


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PDF XAPP930 4 bit binary multiplier Vhdl code DSP48 XAPP930 rgb to ycbcr four matrix multipliers color space converter vhdl rgb ycbcr x93003 XC4VSX35 FF668 FG320 SG16
2006 - vhdl code for floating point matrix multiplication

Abstract: conversion of binary data into gray code in vhdl vhdl code for matrix multiplication matrix multiplication code in vhdl with testbench file XC3S1000 rgb yuv vhdl rgb yuv vhdl gray XAPP931 SG16 DSP48
Text: coding performs poorly for images to be viewed [Ref 2]. 12 or 14 bits per component are necessary to , gray background on Figure 3. The Use fabric for adders checkbox, corresponding to the FABRIC_ADDS VHDL , Generator testbench is also provided to visually inspect output results. The code is parameterizable for , ) data width 2OWIDTH-1 Clipping value for the R, G, B outputs RGBMAX Integer 0 to RGBMIN Integer 0 to 2OWIDTH-1 Clamping value for the R, G, B outputs COFFSET Integer 0


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PDF XAPP931 prov0-792-7, JTC1/SC29/WG11 vhdl code for floating point matrix multiplication conversion of binary data into gray code in vhdl vhdl code for matrix multiplication matrix multiplication code in vhdl with testbench file XC3S1000 rgb yuv vhdl rgb yuv vhdl gray XAPP931 SG16 DSP48
vhdl coding for analog to digital converter

Abstract: TSMC 0.18 um CMOS analog to digital converter vhdl coding digital to analog converter vhdl coding N-7075 tsmc cmos 0.11 um verilog code pipeline square root vlsi design physical verification vhdl code for digital to analog converter verilog adc pipeline
Text: for the ADC to return to specified characteristics after an out-of-range sample. Analog Input , provided to indicate out-of range conditions. Table 7 shows the digital output coding . A nominal , APPLICATIONS · TIMING GENERATOR DIGITAL CONTROL DIGITAL CORRECTION · · Dual 10-bit ADC Up to 120 , a fully differential multistage pipeline architecture with digital error correction to provide 10 , designed for high dynamic performance at input frequencies up to Nyquist and beyond. It thus represents


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PDF nAD10120x2-13a 10-bit nAD10120x2-13a N-7075 vhdl coding for analog to digital converter TSMC 0.18 um CMOS analog to digital converter vhdl coding digital to analog converter vhdl coding tsmc cmos 0.11 um verilog code pipeline square root vlsi design physical verification vhdl code for digital to analog converter verilog adc pipeline
vhdl coding for analog to digital converter

Abstract: vlsi design physical verification AD8138 AD8351 CL013G N-7075 vhdl coding pipeline adc digital error correction simple ADC Verilog code digital mixer verilog code
Text: TIMING GENERATOR DIGITAL CONTROL DIGITAL CORRECTION · · Dual 10-bit ADC Up to 120 MSPS , differential multistage pipeline architecture with digital error correction to provide 10-bit accuracy from , for high dynamic performance at input frequencies up to Nyquist and beyond. It thus represents an ideal solution for demanding applications like broadband communication, digital imaging and multimedia , voltage that gives mid code. Out of Range Recovery Time The time required for the ADC to return to


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PDF nAD10120x2-13m 10-bit nAD10120x2-13m N-7075 vhdl coding for analog to digital converter vlsi design physical verification AD8138 AD8351 CL013G vhdl coding pipeline adc digital error correction simple ADC Verilog code digital mixer verilog code
TSMC 0.18 um CMOS

Abstract: verilog code pipeline square root verilog code for adc vhdl coding for analog to digital converter TSMC Flash IP vhdl coding for pipeline 0.18-um CMOS technology characteristics AD8138 N-7075 AD8351
Text: for a 10-bit converter . Degradation of the SNDR only due to the effect of aperture jitter is given , digital output drivers are scaled to provide necessary current to drive on-chip logic. For applications , start-up times for the idle modes refer to electrical specifications in Table 2 and Table 3. DIGITAL , APPLICATIONS · TIMING GENERATOR DIGITAL CONTROL DIGITAL CORRECTION · · Dual 10-bit ADC Up to 110 , a fully differential multistage pipeline architecture with digital error correction to provide 10


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PDF nAD10110x2-18a 10-bit nAD10110x2-18a N-7075 TSMC 0.18 um CMOS verilog code pipeline square root verilog code for adc vhdl coding for analog to digital converter TSMC Flash IP vhdl coding for pipeline 0.18-um CMOS technology characteristics AD8138 AD8351
TSMC 0.18 um CMOS

Abstract: 0.18-um CMOS technology characteristics tsmc 0.18 flash tsmc cmos 0.18 um AD8351 N-7075 vhdl coding for analog to digital converter TSMC Flash verilog code for adc verilog code of analog mixed mode
Text: suitable for battery powered devices. Communication Receive Channel WLAN / HiperLan / 802.11x Digital , differential multistage pipeline architecture with digital error correction to provide 10-bit accuracy from , mixed-signal systems. The IP is designed for high dynamic performance at input frequencies up to Nyquist , External Reference Common Mode Voltage POWER SUPPLY Positive Analog Supply Voltage Positive Digital , The analog input frequency for which the measured input signal power has dropped by 3 dB


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PDF nAD10110-18a 10-bit nAD10110-18a N-7075 TSMC 0.18 um CMOS 0.18-um CMOS technology characteristics tsmc 0.18 flash tsmc cmos 0.18 um AD8351 vhdl coding for analog to digital converter TSMC Flash verilog code for adc verilog code of analog mixed mode
2005 - 4 bit binary multiplier Vhdl code

Abstract: low pass Filter VHDL code VHDL code for dac vhdl code of 8 bit comparator vhdl code for serial analog to digital converter xilinx vhdl code for digital clock vhdl code for digital to analog converter IPIF adc controller vhdl code Xilinx analog comparator
Text: OPB Delta-Sigma Analog to Digital Converter (ADC) (v1.01a) Figure 9 shows Timing Diagram for Write , DS 0 OPB Delta-Sigma Analog to Digital Converter (ADC) (v1.01a) DS488 December 1, 2005 0 , Implementation of Analog to Digital Converter using OPB ADC OPB ADC Design Parameters To allow the user to , Product Specification www.xilinx.com 2 OPB Delta-Sigma Analog to Digital Converter (ADC) (v1 , Reference. This is the output of external comparator 3 OPB Delta-Sigma Analog to Digital Converter


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PDF DS488 Virtex-402 4 bit binary multiplier Vhdl code low pass Filter VHDL code VHDL code for dac vhdl code of 8 bit comparator vhdl code for serial analog to digital converter xilinx vhdl code for digital clock vhdl code for digital to analog converter IPIF adc controller vhdl code Xilinx analog comparator
verilog code pipeline square root

Abstract: AD8138 AD8351 N-7075 tsmc cmos 0.13 um tsmc cmos 0.13 um ADC vhdl coding pipeline adc digital error correction TSMC Flash IP
Text: ] are provided to indicate out-of range conditions. Table 7 shows the digital output coding . A nominal , suitable for battery powered devices. Communication Receive Channel WLAN / HiperLan / 802.11x Digital , differential multistage pipeline architecture with digital error correction to provide 10-bit accuracy from , mixed-signal systems. The IP is designed for high dynamic performance at input frequencies up to Nyquist , External Reference Common Mode Voltage POWER SUPPLY Positive Analog Supply Voltage Positive Digital


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PDF nAD10120-13a 10-bit nAD10120-13a N-7075 verilog code pipeline square root AD8138 AD8351 tsmc cmos 0.13 um tsmc cmos 0.13 um ADC vhdl coding pipeline adc digital error correction TSMC Flash IP
vhdl coding for analog to digital converter

Abstract: CL013G N-7075
Text: takes from a digital input is latched in, to the sample is converted and put on the analog output , must be bypassed to ground with 100 nF for stable operation and optimum performance. Digital Inputs , . Table 7 shows the digital input coding for mid and end codes for a full-scale current of 10 mA into , performance for update rates up to 400 MSPS. The IP includes edge-triggered input latches, an internal , Voltage Drift III 0 POWER SUPPLY Analog Positive Supply Voltage Digital Positive Supply Voltage


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PDF nDA10400x2-13m 10-bit nDA10400x2-13m N-7075 vhdl coding for analog to digital converter CL013G
TSMC 0.18 um CMOS

Abstract: vhdl coding for analog to digital converter adc vhdl 0.18-um CMOS technology characteristics cmos tsmc 0.18 TSMC 0.18 um CMOS silicon verilog code pipeline square root vlsi design physical verification N-7075 tsmc 0.18 flash
Text: fully differential multistage pipeline architecture with digital error correction to provide 12 , frequencies up to Nyquist and beyond. It thus represents an ideal solution for QUICK REFERENCE DATA , Analog Supply Voltage Positive Digital Supply Voltage Negative Supply Voltage Supply Current, Active , code. Analog Input Bandwidth The analog input frequency for which the measured input signal power , the input to the sample is converted and put on the digital output. Output Data Delay Time Output


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PDF nAD12110-18a 12-bit nAD12110-18a N-7075 TSMC 0.18 um CMOS vhdl coding for analog to digital converter adc vhdl 0.18-um CMOS technology characteristics cmos tsmc 0.18 TSMC 0.18 um CMOS silicon verilog code pipeline square root vlsi design physical verification tsmc 0.18 flash
tsmc cmos 0.13 um

Abstract: digital to analog converter vhdl coding vlsi design physical verification 12 bit DAC VHDL CODE N-7075 vhdl coding for analog to digital converter IFSR10 TSMC 0.13 um CMOS
Text: CMOS levels. Table 7 shows the digital input coding for mid and end codes for a full-scale current of , start-up times for the idle modes refer to electrical specifications in Table 2 and Table 3 DIGITAL , complementary segmented current source architecture to provide 10-bit dynamic performance for update rates up , at mid code input and the ideal mid output. Set-up time ( tSU ) Available time for input data to , is latched in, to the sample is converted and put on the analog output. Propagation Delay ( tPD


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PDF nDA10400-13a 10-bit nDA10400-13a N-7075 tsmc cmos 0.13 um digital to analog converter vhdl coding vlsi design physical verification 12 bit DAC VHDL CODE vhdl coding for analog to digital converter IFSR10 TSMC 0.13 um CMOS
tsmc cmos 0.13 um

Abstract: N-7075
Text: standard binary offset coding at CMOS levels. Table 7 shows the digital input coding for mid and end , Converter IP FEATURES · · · · · DIGITAL CONTROL OPM[2:0] CLK0 IOUT0 LATCH · Dual , excellent dynamic performance for output frequencies up to Nyquist and beyond. The high performance also , digital-to-analog converter silicon IP. It uses a complementary segmented current source architecture to provide 10-bit dynamic performance for update rates up to 400 MSPS. The core includes edge-triggered input


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PDF nDA10400x2-13a 10-bit nDA10400x2-13a N-7075 tsmc cmos 0.13 um
TSMC 0.18 um CMOS

Abstract: TSMC rf cmos 0.18 um IFSR15 N-7075 cmos tsmc 0.18 1/TSMC rf cmos 0.18 um
Text: time it takes from a digital input is latched in, to the sample is converted and put on the analog , MSPS Digital-to-Analog Converter IP Digital Inputs Operational Mode Control In addition to active , coding at CMOS levels. Table 8 shows the digital input coding for mid and end codes for a full-scale , for update rates up to 200 MSPS. The core includes edge-triggered input latches, an internal voltage , mid code input and the ideal mid output. The time it takes for the output to reach and remain


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PDF nDA10200x2-18a 10-bit nDA10200x2-18a N-7075 TSMC 0.18 um CMOS TSMC rf cmos 0.18 um IFSR15 cmos tsmc 0.18 1/TSMC rf cmos 0.18 um
2001 - GSM 900 simulink matlab

Abstract: verilog code for ofdm transmitter digital IIR Filter VHDL code fir filter coding for gui in matlab digital IIR Filter verilog code qpsk modulation VHDL CODE vhdl code for ofdm transmitter vhdl code for ofdm qpsk demapper VHDL CODE turbo codes qam system matlab code
Text: ), VHDL , or Verilog Using the power of digital logic, signals can be cleanly modulated to an , , high-throughput signal coding schemes, W processing algorithms. ireless and digital signal processing , Hardware Acceleration Signal Coding Altera provides a variety of signal coding functions for , triple-DES encryption. Using a PLD for encryption makes it easy to implement on-a-programmable-chip (SOPC , Figure 4. Signal Coding Block Diagram difficult to easily implement on any DSP processors. However


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PDF M-GB-SIGNAL-01 GSM 900 simulink matlab verilog code for ofdm transmitter digital IIR Filter VHDL code fir filter coding for gui in matlab digital IIR Filter verilog code qpsk modulation VHDL CODE vhdl code for ofdm transmitter vhdl code for ofdm qpsk demapper VHDL CODE turbo codes qam system matlab code
1998 - U2550

Abstract: u560100 ZMD U2510 U560244 Bosch Common Rail Sensor U2400 U560048 6v to 7.5v dc power supply circuit project U2100 u5601
Text: up to 16kbits, ROMs of up to 128kbits, functional blocks for test support, etc. The Analog , . Digital Libraries (equivalent to U2400) The ZMSC670 Cell Library is intended for circuit designs with , specific analog and digital cells. Support for full-custom designs and foundry services is available , the analog field. To ensure reliable designs with fast turnaround, ZMD offers a digital cell library as well as RAM/ROM and EEPROM macros. In addition to digital circuitry, ZMD provides a set of analog


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1999 - vhdl code for cordic algorithm

Abstract: vhdl code for cordic verilog code for cordic algorithm vhdl code for modulation vhdl code for complex multiplication and addition verilog code for cordic vhdl code for rotation cordic vhdl code for digital clock digital clock vhdl code cordic algorithm code in verilog
Text: automatically convert the fixed-point CORDIC algorithm to Verilog or VHDL . For the evaluation, a number of , 28 To get a resource-shared implementation in VHDL , a different C coding style is employed , A|RT Builder to automatically map the instantiated components in VHDL . For example, to import a , finite precision operations. A|RT Builder supports automatic conversion from ANSI C to VHDL or Verilog , , compression, coding , and other operations on digital signals. However, most hardware designers are using a


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2001 - VHDL code of lcd display

Abstract: vhdl code for lcd of xilinx vhdl code for lcd display XAPP149 handspring vhdl code for digital to analog converter analog to digital converter vhdl coding serial analog to digital converter vhdl code XAPP355 XAPP146
Text: source code will also be provided for download. To obtain the VHDL code described in this document, go to section VHDL Code Download, page 9 for instructions. Overview This application note presents , System interface. The VHDL code presented in XAPP355 is intended to be a "building block" for future , connected to analog input channel 0 of of the ADS7870. Thirty-eight points will be continuously plotted and , been configured for single ended operation, which means that the analog input signal can vary from 0V


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PDF XAPP149 XAPP149 VHDL code of lcd display vhdl code for lcd of xilinx vhdl code for lcd display handspring vhdl code for digital to analog converter analog to digital converter vhdl coding serial analog to digital converter vhdl code XAPP355 XAPP146
2001 - verilog code for DFT

Abstract: toshiba ASIC analog to digital converter verilog code target FPGA
Text: different from or in addition to FPGA implementations. Other special cells like DACs ( Digital to Analog Converter ), ADCs ( Analog to Digital Converter ) , oscillators, and PLLs (Phase-Lock Loop) also have fixed , Static Timing Analysis Design for Test Multiple FPGAs to ASIC 5 Synchronous Design Techniques , 3. For the manufacturing test process, Toshiba needs test patterns to insure the correct operation , objective of finishing the ASIC. It is conceivable that after a DFT (Design for Test) review, changes to


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2002 - adc controller vhdl code

Abstract: vhdl code for time division multiplexer serial analog to digital converter vhdl code vhdl code for digital clock output on CPLD vhdl code for parallel to serial converter XAPP355 vhdl program for parallel to serial converter adc vhdl handspring adc vhdl source code
Text: 12-bit, serial, 8-channel analog to digital converter . The ADS7870 ADC is ideal for portable and , Texas Instruments ADS7870 Analog to Digital Converter (ADC) in a Xilinx CoolRunnerTM XPLA3TM CPLD , the CoolRunner CPLD. All related source code is provided for download. To obtain the VHDL code described in this document, go to section VHDL Code Download, page 27 for instructions. Overview , ADS7870 interface for those who wish to understand the VHDL implementation of the CPLD ADC interface


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PDF XAPP355 ADS7870 XAPP355 adc controller vhdl code vhdl code for time division multiplexer serial analog to digital converter vhdl code vhdl code for digital clock output on CPLD vhdl code for parallel to serial converter vhdl program for parallel to serial converter adc vhdl handspring adc vhdl source code
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