The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC6993CS6-3#TRMPBF Linear Technology LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: SOT; Pins: 6; Temperature Range: 0°C to 70°C
LTC6993HS6-4#TRMPBF Linear Technology LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: SOT; Pins: 6; Temperature Range: -40°C to 125°C
LTC6993CDCB-4#TRPBF Linear Technology LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: DFN; Pins: 6; Temperature Range: 0°C to 70°C
LTC6993IDCB-2#TRMPBF Linear Technology LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C
LTC6993CS6-4#PBF Linear Technology LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: SOT; Pins: 6; Temperature Range: 0°C to 70°C
LTC6993IDCB-2#PBF Linear Technology LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C

vhdl code to generate sine wave Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2006 - verilog code to generate sine wave

Abstract: verilog code for sine wave generator using cordic vhdl code to generate sine wave CORDIC to generate sine wave fpga verilog code for CORDIC to generate sine wave vhdl code dds VHDL code for CORDIC to generate sine wave vhdl code for cordic algorithm vhdl code for cordic CORDIC to generate sine wave
Text: sine wave if the core is configured to generate a real or complex sinusoid. It carries a cosine , digitally generates a complex or real-valued sine wave . Due to the digital nature of the DDS functionality , . CORDIC-generated sine wave samples are approximations of a precise sine wave . In order to store the LUT precise sine wave values, the approximations sin' and cos' need to be truncated to discard bits that are not , wave if the core is configured to generate a complex sinusoid. If configured differently, the signal


Original
PDF
2008 - simulink 3 phase inverter

Abstract: vhdl code to generate sine wave FIR filter matlaB simulink design vhdl code for floating point adder vhdl code of floating point adder vhdl code for full subtractor vhdl code for qam inverter in matlab vhdl code for floating point subtractor modulation matlab code
Text: Blocks 6 Task 4: Add Simulink Blocks 6 Task 5: Specify Sine Wave Characteristics 7 Task 6: Define the Precision 8 Task 7: Simulate the Design 9 Task 8: Generate and Verify the VHDL Code 9 Target the Design , parameters of the sine wave source, which will provide the stimulus to the system. 1. Double-click the Sine , : Generate and Verify the VHDL Code In this task, you will proceed with the hardware implementation phase , design. The next and final steps are to synthesize the VHDL code and run the output through the FPGA


Original
PDF 1-800-LATTICE simulink 3 phase inverter vhdl code to generate sine wave FIR filter matlaB simulink design vhdl code for floating point adder vhdl code of floating point adder vhdl code for full subtractor vhdl code for qam inverter in matlab vhdl code for floating point subtractor modulation matlab code
2002 - fsk by simulink matlab

Abstract: VHDL code for CORDIC to generate sine wave VERILOG Digitally Controlled Oscillator vhdl code for cordic algorithm verilog code for cordic algorithm vhdl code to generate sine wave matlab code to generate sine wave using CORDIC verilog code for CORDIC to generate sine wave vhdl code for cordic matlab code for CORDIC to generate sine wave
Text: evaluation. The OpenCore Plus hardware evaluation feature allows you to generate time-limited programming , before you can generate programming files or EDIF, VHDL , or Verilog HDL gate-level netlist files for , deciding to purchase a license. However, you must purchase a license before you can generate programming , for the wizard to output. You can choose Verilog HDL, VHDL , and MATLAB models and testbenches, as , Click Next to view a summary of the files the wizard will generate . Click Finish when you are done


Original
PDF
2010 - AC350

Abstract: R501 0x40020000
Text: equation is used to generate the sine wave samples. YSineSample(x) = Offset + Amplitude * sin (2* pi* x/ns , second and 100 samples per cycle respectively. To have a high quality Sine wave pattern, it is , sine wave sample values. Continuously writing to the DAC0_BYTE0 register with the sine_LUT samples , application note describes how to generate analog waveform (Constant signal, Positive ramp, Negative ramp, Sine wave , and Square Wave ) using SmartFusion ACE DAC on SmartFusion Evaluation kit and SmartFusion


Original
PDF AC350 AC350 R501 0x40020000
2000 - vhdl code for cordic cosine and sine

Abstract: verilog code to generate sine wave vhdl code to generate sine wave verilog code for CORDIC to generate sine wave CORDIC to generate sine wave verilog code for cordic algorithm sine cosine qpsk modulation VHDL CODE VHDL code for CORDIC to generate sine wave vhdl code for cordic algorithm matlab code to generate sine wave using CORDIC
Text: generate a carrier or to modulate a signal onto a carrier. The Altera® digital signal processing (DSP , frequency and resolution of the output sine wave . In the ROM version, the phase accumulator output , both ROM and CORDIC architectures. ROM Architecture The ROM containing the sine /cosine wave can be , stores the sine or cosine values and outputs every clock cycle, operating at clock rates of 70 to 160 , s Family: APEXTM 20K, ACEXTM, FLEX® 10, FLEX 8000, and FLEX 6000 s s s s Ordering Code


Original
PDF
2005 - FIFO4K18

Abstract: AC240 fifo vhdl fifo
Text: /Fusion_sine_table.xls, is used to generate half-cycle of sine wave . This Sine Table requires 1024x8 memory. Creating , half of a cycle of a sine wave . If this table is used to initialize FIFO blocks, the contents of the FIFO should be read twice to generate a full cycle of periodic sine wave . The following is an example , ) of the read data alternatively at the end of each half-cycle to generate a full-cycle sine wave , transmits a full sine wave data to the external D/A. The Wave_Gen design in this example, enabled at the


Original
PDF AC240 FIFO4K18 AC240 fifo vhdl fifo
2005 - verilog code of sine rom

Abstract: sine wave output for fpga using verilog code vhdl code for 555 DS275 X9111 SPARTAN 6 verilog code for sine wave output using FPGA verilog code for sine wave using FPGA
Text: widths of 3 to 10 bits for Distributed ROM and 3 to 16 bits for Block ROM · Supports output Sine /Cosine widths of 4 to 32 bits · Supports negative Sine /Cosine outputs 2 · Symmetric Output option uses an , 2 Eq. 3 The values for the sine and cosine wave are stored in an internal ROM. Depending on , for both the Sine and Cosine output values. The valid range is 4 to 32. Theta Input Width: Specify , selection ­ either VHDL or Verilog { VHDL | VERILOG} ViewlogicLibraryAlias Pathname to Viewlogic


Original
PDF DS275 verilog code of sine rom sine wave output for fpga using verilog code vhdl code for 555 X9111 SPARTAN 6 verilog code for sine wave output using FPGA verilog code for sine wave using FPGA
2009 - verilog code for cordic algorithm

Abstract: CORDIC to generate sine wave fpga vhdl code for cordic cosine and sine vhdl code for cordic algorithm sin wave with test bench file in vhdl cordic algorithm code in verilog CORDIC altera cordic sine cosine generator vhdl QFSK matlab code to generate sine wave using CORDIC
Text: parameters for the NCO MegaCore function, refer to Chapter 3, Parameter Settings. 4. Click Step 2: Generate in IP Toolbench to generate your NCO MegaCore function variation. For information about the , Simulation NCO page (Figure 2­4). Figure 2­4. Set Up Simulation 3. Turn on Generate Simulation Model to , tool supports this feature, turn on Generate netlist. Generate the MegaCore Function To generate , Toolbench to generate your MegaCore function variation and supporting files. The generation phase may take


Original
PDF
2008 - FIFO4K18

Abstract: fifo vhdl Actel on sram Actel igloo ProASIC3
Text: of a sine wave . If this table is used to initialize FIFO blocks, the contents of the FIFO should be read twice to generate a full cycle of periodic sine wave . The following is an example of the Wave_Gen , alternatively at the end of each half-cycle to generate a full-cycle sine wave . library ieee; use , . The structure and functionality of Wave_Gen block depends entirely to the waveform type ( sine wave , FIFO. These memory blocks also include a dedicated FIFO controller to generate internal addresses and


Original
PDF AC215 FIFO4K18 fifo vhdl Actel on sram Actel igloo ProASIC3
2010 - verilog code for CORDIC to generate sine wave

Abstract: verilog code for cordic algorithm vhdl code for cordic verilog code for cordic verilog code to generate sine wave CORDIC to generate sine wave fpga vhdl code to generate sine wave vhdl code for rotation cordic vhdl code for FFT 32 point CORDIC to generate sine wave
Text: NCO MegaCore function, refer to Chapter 3, Parameter Settings. 4. Click Step 2: Generate in IP Toolbench to generate your NCO MegaCore function variation. For information about the generated files , Figure 2­4. Set Up Simulation 3. Turn on Generate Simulation Model to create an IP functional model , , turn on Generate netlist. Generate the MegaCore Function To generate your MegaCore function variation, perform the following steps: 1. Click Step 3: Generate in IP Toolbench to generate your MegaCore


Original
PDF
1998 - Gate level simulation without timing

Abstract: Gate level simulation ieee floating point vhdl simulation models vhdl coding vhdl code of floating point unit vhdl code for register signal path designer
Text: . About Testbenches A testbench is a separate set of VHDL or Verilog code that connects up to the inputs , Design Flow Designers have traditionally simulated the source code to check for syntax and functional , netlist. The functional simulation of the source code allows designers to check the general functionality , will additionally generate a VHDL or Verilog netlist with the routing delays annotated into a Standard , simulation or to miss critical board problems during simulation. Because VHDL and Verilog were both


Original
PDF
2011 - VERILOG Digitally Controlled Oscillator

Abstract: verilog code of sine rom matlab code to generate sine wave using CORDIC EP3C10F256 QFSK verilog code to generate sine wave matlab code for half adder CORDIC to generate sine wave fpga verilog code for digital modulation cyclone iii CORDIC altera sine and cos
Text: function, refer to Chapter 3, Parameter Settings. 4. Click Step 2: Generate in IP Toolbench to generate , NCO page (Figure 2­4). Figure 2­4. Set Up Simulation 3. Turn on Generate Simulation Model to , this feature, turn on Generate netlist. Generate the MegaCore Function To generate your MegaCore function variation, perform the following steps: 1. Click Step 3: Generate in IP Toolbench to generate your , synthesis. It will be added to your Quartus II project. ModelSim TCL Script that runs the VHDL or Verilog


Original
PDF
2002 - amplitude demodulation matlab code

Abstract: 4-bit AHDL adder subtractor vhdl code numeric controlled oscillator pipeline pulse amplitude modulation matlab code a6w 58 vhdl code for digit serial fir filter EP20K200EBC652-1X A4w sd matlab 14.1 APEX nios development board
Text: .56 Generate VHDL , Synthesize, Compile & Download the Design to the DSP Board .57 Specify Trigger , . Click OK. 6. Choose Save (File menu) to save the model. Add the Sine Wave Block Perform the following steps to add the Sine Wave block. 1. 2. Drag and drop a Sine Wave block into your model , .25 Add the Sine Wave Block , feature by supporting free hardware evaluation. This feature allows you to generate time-limited


Original
PDF \Exemplar\LeoSpec\OEM2002a 14\bin\win32 amplitude demodulation matlab code 4-bit AHDL adder subtractor vhdl code numeric controlled oscillator pipeline pulse amplitude modulation matlab code a6w 58 vhdl code for digit serial fir filter EP20K200EBC652-1X A4w sd matlab 14.1 APEX nios development board
2009 - real time simulink wireless

Abstract: quadrature amplitude modulation a simulink model EP2C35F672C6 vhdl projects abstract and coding vhdl code to generate sine wave EP2S60 EP2C35 AN442 simulink matlab PFC 1S25
Text: following steps to add the Sine Wave block: 1. In the Simulink Library Browser, click Simulink and Sources to view the blocks in the Sources library. 2. Drag and drop a Sine Wave block into your model. 3. Double-click the Sine Wave block in your model to display the Block Parameters dialog box (Figure 2­1). , Library Browser into your model. Position the block to the right of the Sine Wave block. If you are , Sine Wave block to the left side of the SinIn block by holding down the left mouse button and dragging


Original
PDF
1998 - xilinx vhdl code

Abstract: xilinx vhdl
Text: of the simulation models to the local directory. If you did not generate VHDL simulation models for , , this will resolve to C:\FNDTN\ vhdl \data\MTI After starting ModelSim, select File -> Directory and browse over to $MODELSIM. In ModelSim, select Library -> New. Type $XILINX/ vhdl /data/MTI/logiblox. If you , . In the Compile VHDL Source dialog window, set the Target Library to LogiBLOX. In the Directories window, change to $XILINX\ vhdl \src\logiblox. 10 Use the Compile to compile the VHDL files in the order


Original
PDF
2010 - vsim-3043

Abstract: vsim 3043 ModelSim QII53001-10 QII53001 220pack
Text: or VHDL designs that target an Altera FPGA. 1 In this chapter, ModelSim refers to ModelSim SE , simulation, generate gate-level timing simulation netlist files. For more information, refer to the , f For information about simulating VHDL designs using the GUI, refer to Performing a Functional , gate-level simulation, generate gate-level timing simulation netlist files. For more information, refer to , commands to perform a functional simulation for VHDL designs with one of the libraries (lib1) listed in


Original
PDF QII53001-10 vsim-3043 vsim 3043 ModelSim QII53001 220pack
1998 - xilinx vhdl code

Abstract: ROC Compiled Using Hierarchy in VHDL Design
Text: each of the simulation models to the local directory. If you did not generate VHDL simulation models , the default location, this will resolve to C:\FNDTN\ vhdl \data\MTI After starting ModelSim, select File -> Directory and browse over to $MODELSIM. In ModelSim, select Library -> New. Type $XILINX/ vhdl , Library to LogiBLOX. In the Directories window, change to $XILINX\ vhdl \src\logiblox. 10. Use the Compile to compile the VHDL files in the order they are shown: mvlutil.vhd mvlarith.vhd logiblox.vhd


Original
PDF
2005 - SPARTAN-3 motor

Abstract: XAPP900 spartan-3 starter 3 phase induction motor fpga sine pwm induction motor PWM motorController XC3S200 A2-19 XAPP448 FPGA motor driver
Text: divider has been inserted, modify the three wave buses to display the actual values in a sine fashion , differences on the waveforms. Wave Type Switching This design has the ability to generate three different , but failed due to an error (red "x"). As an example, highlight the top level VHDL file , is necessary to create the programming file bitstream. To create the bitstream: Highlight Generate Programming File, then right click, and select Run or Double left click on Generate Programming File to


Original
PDF XAPP900 240ns. XAPP448 SPARTAN-3 motor XAPP900 spartan-3 starter 3 phase induction motor fpga sine pwm induction motor PWM motorController XC3S200 A2-19 XAPP448 FPGA motor driver
1996 - EPM7160 Transition

Abstract: 6402 uart 4 bit updown counter vhdl code EPM7064L-84 EPM7192 Date Code Formats EPM7160L-84 ep330 epf8282alc84-4 EPF81500ARI240-3 EPF81500ARI240
Text: created with a LUT. This example describes how to generate a sine wave using an EAB. Transcendental , digital output can be driven to a digital-to-analog converter. A sine wave can be used for various DSP , performance prediction will be improved to generate more accurate results. In addition, the release will , . Example 1: Trancendental Functions & Waveform Generators The EAB can be used to generate waveforms that , EAB can be up to 8 bits wide, 1 EAB can simultaneously generate 8 waveforms. Multiple EABs can be


Original
PDF
Verification Using a Self-checking Test Bench

Abstract: new ieee programs in vhdl and verilog QII53001-7 QII53002-7 QII53003-7 QII53017-7
Text: automatically generate the clock wave , rather than drawing each clock triggering pulse. To generate a clock , . For timing simulations, you must first perform place-and-route and static timing analysis to generate , block and the routing delays. If you want to use third-party EDA simulation tools, you can generate a , to generate a VWF. Creating VWFs To create a VWF, perform the following steps: 1. 2. Click , offset and the duty cycle), or whether to generate the clock based on a specified clock. Figure 1­7


Original
PDF
2010 - system verilog

Abstract: Gate level simulation 220pack lpm compile STRATIX QII53023-10
Text: Simulation Library Compiler is used to compile Verilog HDL and VHDL simulation libraries for all Altera , ) Perform simulation of Verilog HDL or VHDL designs with Active-HDL software at various levels to verify , , you do not have to remember the commands to compile the libraries or load and simulate the VHDL , typically performed to verify the syntax of the code and to check the functionality of the design. f , VHDL designs, refer to Performing a Simulation of a VHDL Design with the Active-HDL Software in


Original
PDF QII53023-10 system verilog Gate level simulation 220pack lpm compile STRATIX
2000 - FSK modulate by matlab book

Abstract: adpll.mdl quadrature amplitude modulation a simulink model simulink 16QAM QAM verilog 16 QAM modulation matlab vhdl program for cordic cosine and sine CORDIC QAM modulation pulse amplitude modulation using 555 FSK matlab
Text: frequency of the output sine wave is derived from both the phase increment input to the accumulator and the , , digital phase locked loops (PLLs), and symbol recovery circuits. NCOs can be used to generate a carrier , table with interpolation to generate a precision sinosoid using limited-size onchip SRAM. ASSPs , sinusoid. For a given precision, the ROM containing the sine /cosine wave can be large or small. The ROM , to calculate trigonometric functions such as sine and cosine. CORDIC is based on the idea of complex


Original
PDF -UG-NCOCOMPILER-01 FSK modulate by matlab book adpll.mdl quadrature amplitude modulation a simulink model simulink 16QAM QAM verilog 16 QAM modulation matlab vhdl program for cordic cosine and sine CORDIC QAM modulation pulse amplitude modulation using 555 FSK matlab
2000 - isplsi architecture

Abstract: No abstract text available
Text: Devices · To generate the VHDL and/or Verilog timing models, check the VHDL and or Verilog netlist box. · , dialog box, the user can choose to generate a VHDL netlist, a Verilog netlist and an SDF file. 6 , netlist: 1. Select VHDL to generate the file. 2. Select Standard Delay Format to generate the , Model Generation: · To generate VHDL timing models, select Interfaces => VHDL Writer. · To generate , used to generate an EDIF netlist file that can be imported into ispDesignEXPERT software for place and


Original
PDF 1-800-LATTICE isplsi architecture
1998 - quadrature phase sine wave generator

Abstract: vhdl code to generate staircase wave vhdl code for FFT 4096 point vhdl code to generate sine wave vhdl code for accumulator Numerically Controlled Oscillator VHDL code for band pass Filter precision Sine Wave Generator amplitude demodulation using xilinx system generator analog to digital converter vhdl coding
Text: simultaneously generates digital "staircase" approximations to a sine wave and a cosine wave , the frequencies of , a consequence, the Fourier analysis is performed on a "staircase" approximation to a sine wave , resolution (3 to 10 bits) Simultaneous sine and cosine outputs available excellent for high speed I/Q , integrated phase value (or a truncated version of the same) is used to address the sine /cosine LUT, which outputs the amplitude corresponding to the cosine (In-phase) and sine (Quadrature) of the current phase


Original
PDF X8820r quadrature phase sine wave generator vhdl code to generate staircase wave vhdl code for FFT 4096 point vhdl code to generate sine wave vhdl code for accumulator Numerically Controlled Oscillator VHDL code for band pass Filter precision Sine Wave Generator amplitude demodulation using xilinx system generator analog to digital converter vhdl coding
1999 - vhdl code to generate sine wave

Abstract: Numerically Controlled Oscillator vhdl code for FFT 16 point vhdl code for FFT 4096 point X9025 quadrature phase sine wave generator vhdl code to generate staircase wave XILINX vhdl code NCO precision Sine Wave Generator matlab
Text: outputs (NCOIQ) module simultaneously generates digital "staircase" approximations to a sine wave and a , , the Fourier analysis is performed on a "staircase" approximation to a sine wave , which remains , truncated version of the same) is used to address the sine /cosine LUT, which outputs the amplitude corresponding to the cosine (In-phase) and sine (Quadrature) of the current phase value. Theory of Operation , recipe. VHDL instantiation code and a schematic symbol are created along with the netlist for the


Original
PDF XC4000E, vhdl code to generate sine wave Numerically Controlled Oscillator vhdl code for FFT 16 point vhdl code for FFT 4096 point X9025 quadrature phase sine wave generator vhdl code to generate staircase wave XILINX vhdl code NCO precision Sine Wave Generator matlab
Supplyframe Tracking Pixel