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Part Manufacturer Description Datasheet Download Buy Part
LT1103CY Linear Technology IC SWITCHING CONTROLLER, Switching Regulator or Controller
LTC6990HS6#PBF Linear Technology LTC6990 - TimerBlox: Voltage Controlled Silicon Oscillator; Package: SOT; Pins: 6; Temperature Range: -40°C to 125°C
LTC6990IDCB#PBF Linear Technology LTC6990 - TimerBlox: Voltage Controlled Silicon Oscillator; Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C
LTC6990IS6#PBF Linear Technology LTC6990 - TimerBlox: Voltage Controlled Silicon Oscillator; Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C
LTC6990CDCB#TRMPBF Linear Technology LTC6990 - TimerBlox: Voltage Controlled Silicon Oscillator; Package: DFN; Pins: 6; Temperature Range: 0°C to 70°C
LTC6990CS6#TRMPBF Linear Technology LTC6990 - TimerBlox: Voltage Controlled Silicon Oscillator; Package: SOT; Pins: 6; Temperature Range: 0°C to 70°C

vhdl code numeric controlled oscillator pipeline Datasheets Context Search

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2008 - simulink 3 phase inverter

Abstract: vhdl code to generate sine wave FIR filter matlaB simulink design vhdl code for floating point adder vhdl code of floating point adder vhdl code for full subtractor vhdl code for qam inverter in matlab vhdl code for floating point subtractor modulation matlab code
Text: Precision 8 Task 7: Simulate the Design 9 Task 8: Generate and Verify the VHDL Code 9 Target the Design , : Generate and Verify the VHDL Code In this task, you will proceed with the hardware implementation phase , design. The next and final steps are to synthesize the VHDL code and run the output through the FPGA , Lattice library blocks to build and test a Numerically Controlled Oscillator (NCO) within the Matlab , . Variables in commands, code syntax, and path names. Ctrl+L Press the two keys at the


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PDF 1-800-LATTICE simulink 3 phase inverter vhdl code to generate sine wave FIR filter matlaB simulink design vhdl code for floating point adder vhdl code of floating point adder vhdl code for full subtractor vhdl code for qam inverter in matlab vhdl code for floating point subtractor modulation matlab code
2002 - fsk by simulink matlab

Abstract: VHDL code for CORDIC to generate sine wave VERILOG Digitally Controlled Oscillator vhdl code for cordic algorithm verilog code for cordic algorithm vhdl code to generate sine wave matlab code to generate sine wave using CORDIC verilog code for CORDIC to generate sine wave vhdl code for cordic matlab code for CORDIC to generate sine wave
Text: property logic element numerically controlled oscillator programmable logic device phase shift keying , keying (QFSK) modulator example designs A numerically controlled oscillator (NCO) synthesizes a , .31 VHDL Simulation in ModelSim Simulators , Ordering Code IP-NCO Product ID(s) 0014 Vendor ID(s) 6AF8 (Standard) 6AF9 (Time-Limited) Introduction The Altera® NCO Compiler MegaCore function generates numerically controlled oscillators (NCOs


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2009 - verilog code for cordic algorithm

Abstract: CORDIC to generate sine wave fpga vhdl code for cordic cosine and sine vhdl code for cordic algorithm sin wave with test bench file in vhdl cordic algorithm code in verilog CORDIC altera cordic sine cosine generator vhdl QFSK matlab code to generate sine wave using CORDIC
Text: settings. A numerically controlled oscillator synthesizes a discrete-time, discrete-valued representation , Toolbench. (2) The prefix is added automatically. The VHDL code for each MegaCore instance is , numerically controlled oscillator (NCO) synthesizes a discrete-time, discrete-valued representation of a , . . . . . . . 3­7 Chapter 4. Functional Description Numerically Controlled Oscillators . . . . . , Information Item Version Release Date Description 9.1 November 2009 Ordering Code Product ID(s


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2010 - verilog code for CORDIC to generate sine wave

Abstract: verilog code for cordic algorithm vhdl code for cordic verilog code for cordic verilog code to generate sine wave CORDIC to generate sine wave fpga vhdl code to generate sine wave vhdl code for rotation cordic vhdl code for FFT 32 point CORDIC to generate sine wave
Text: MegaCore function implements a numerically controlled oscillator and supports the following features , testbenches for VHDL , Verilog HDL and MATLAB Includes dual-output oscillator and quaternary frequency , functionality of the NCO, based on your parameter settings. A numerically controlled oscillator synthesizes a , supplied automatically by IP Toolbench. (2) The prefix is added automatically. The VHDL code , Oscillators A numerically controlled oscillator (NCO) synthesizes a discrete-time, discrete-valued


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2011 - VERILOG Digitally Controlled Oscillator

Abstract: verilog code of sine rom matlab code to generate sine wave using CORDIC EP3C10F256 QFSK verilog code to generate sine wave matlab code for half adder CORDIC to generate sine wave fpga verilog code for digital modulation cyclone iii CORDIC altera sine and cos
Text: prefix is added automatically. The VHDL code for each MegaCore instance is generated , Controlled Oscillators A numerically controlled oscillator (NCO) synthesizes a discrete-time , . 3­7 Chapter 4. Functional Description Numerically Controlled Oscillators . . . . . . . . . . . , function generates numerically controlled oscillators (NCOs) customized for Altera devices. You can use the , display the functionality of the NCO, based on your parameter settings. A numerically controlled


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vhdl code for matrix multiplication

Abstract: VHDL code DCT vhdl code for inverse matrix vhdl code for transpose memory vhdl coding for pipeline matrix multiplication code in vhdl with testbench file verilog code for 8x8 matrix multiplication matrix multiplier Vhdl code idct vhdl code verilog code for matrix multiplication
Text: Inverse DCT compliant with IEEE 1180-1990 standard · Customizable RTL source code available · Customized , ) - Parameterizable number of pipeline stages in multipliers - Variable I/O scanning format , Formats EDIF netlist, XNF netlist, Constraints Files .ncf Verification VHDL testbench Instantiation VHDL , Verilog Templates Reference Designs & None Application Notes Additional Items C environment , Memory Word Size =14 · Internal Datapath Size =20 · One Pipeline Multiplier Stage · No MPEG2 Mismatch


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PDF I-10148 16x16 vhdl code for matrix multiplication VHDL code DCT vhdl code for inverse matrix vhdl code for transpose memory vhdl coding for pipeline matrix multiplication code in vhdl with testbench file verilog code for 8x8 matrix multiplication matrix multiplier Vhdl code idct vhdl code verilog code for matrix multiplication
1999 - VHDL code DCT

Abstract: vhdl code for multiplexer 8 to 1 using 2 to 1 vhdl code for inverse matrix verilog code for inverse matrix idct vhdl code vhdl code for transpose memory verilog code for 16*16 multiplier matrix multiplication code in vhdl with testbench file matrix multiplier Vhdl code vhdl code for matrix multiplication
Text: the synthesizable VHDL source code of the core. Parameters allow the user to specify some , source code available Customized testbench for pre- and post-synthesis verification supplied with the , coefficients width (10- 26 bits) - Parameterizable number of pipeline stages in multipliers - Variable I/O , Manual Design File Formats EDIF netlist, XNF netlist, Constraints Files .ncf Verification VHDL testbench Instantiation VHDL , Verilog Templates Reference Designs & None Application Notes Additional


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PDF 16x16 VHDL code DCT vhdl code for multiplexer 8 to 1 using 2 to 1 vhdl code for inverse matrix verilog code for inverse matrix idct vhdl code vhdl code for transpose memory verilog code for 16*16 multiplier matrix multiplication code in vhdl with testbench file matrix multiplier Vhdl code vhdl code for matrix multiplication
2002 - adc controller vhdl code

Abstract: vhdl code for time division multiplexer serial analog to digital converter vhdl code vhdl code for digital clock output on CPLD vhdl code for parallel to serial converter XAPP355 vhdl program for parallel to serial converter adc vhdl handspring adc vhdl source code
Text: ADC in a portable handheld application. This document provides an explanation of the VHDL code for the CoolRunner CPLD. All related source code is provided for download. To obtain the VHDL code described in this document, go to section VHDL Code Download, page 27 for instructions. Overview , R Usage Serial ADC Interface Using a CoolRunner CPLD The VHDL code distributed with this , section of the VHDL code can be edited to specify various aspects of the ADS7870 which include: ·


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PDF XAPP355 ADS7870 XAPP355 adc controller vhdl code vhdl code for time division multiplexer serial analog to digital converter vhdl code vhdl code for digital clock output on CPLD vhdl code for parallel to serial converter vhdl program for parallel to serial converter adc vhdl handspring adc vhdl source code
1999 - vhdl projects abstract and coding

Abstract: VHDL code for generate sound project of 8 bit microprocessor using vhdl I960RP 8 bit microprocessor using vhdl Modelling
Text: the design under test, or DUT. The top-level file is usually composed of structural VHDL code that , these would be the place to start. The codes can be stored in the VHDL code of the CPU model, or could , functions implemented directly in VHDL code . This was less efficient than a model that used a test language , two architectures. A main process embedded in the VHDL code drives the first itself. The test , Behavioral Modeling in VHDL Simulations The Benefits of Higher Levels of Abstraction in Complex


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p23a

Abstract: AMI Software
Text: characters representing description options. CODE no type specified TYPE (t) (one-digit number , table: INFORMATION TYPE CODE DESCRIPTION U INFORMATION TYPE CODE C Q X Holding , no strength specified crystal oscillator P DIRECTION (d) Programmable pull-up or , : Naming Scheme: Example: ODit1t2t3ss ODCSXE08 INFORMATION TYPE CODE DESCRIPTION C · , TTL levels are observed Qa crystal oscillator P Intel's PCI levels are observed B


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PDF AD00INT, p23a AMI Software
vhdl code for rsa

Abstract: vhdl code for DES algorithm vhdl code 32 bit risc code vhdl code for memory card ST22 ST22WJ64 interrupt controller vhdl code vhdl code for data memory
Text: control ­ Domain switching securely controlled by protected Context Stack ­ Native/Java, Code /Data , Code Validation Tools chain including the VHDL Emulator, must be used for both the hardware, software , AND NATIVE s 4-STAGE PIPELINE s 16 GENERAL PURPOSE 32-BIT REGISTERS, AND 10 SPECIAL REGISTERS s 4 , CLOCK FREQUENCY SENSORS MEMORY s HIGHLY RELIABLE CMOS EEPROM TECHNOLOGY ­ Error Correction Code for , Direct JavaCardTM byte code execution provides high performance advantage over processors that emulate


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PDF ST22WJ64 32-BIT 24-BIT 160d/PRZ vhdl code for rsa vhdl code for DES algorithm vhdl code 32 bit risc code vhdl code for memory card ST22 ST22WJ64 interrupt controller vhdl code vhdl code for data memory
1999 - vhdl projects abstract and coding

Abstract: SW04PCR040 I960RP ISA CODE VHDL only love vme bus specification vhdl
Text: the design under test, or DUT. The top-level file is usually composed of structural VHDL code that , these would be the place to start. The codes can be stored in the VHDL code of the CPU model, or could , functions implemented directly in VHDL code . This was less efficient than a model that used a test language , two architectures. A main process embedded in the VHDL code drives the first itself. The test , Behavioral Modeling in VHDL Simulations The Benefits of Higher Levels of Abstraction in Complex


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2001 - CRT2380

Abstract: vhdl code for 32bit data memory vhdl code for rsa 32 bit risc processor using vhdl vhdl code for DES algorithm ST22XJ64 UART using VHDL ICE POD vhdl code for memory card ST22
Text: control ­ Domain switching securely controlled by protected Context Stack ­ Native/Java, Code /Data , associated firmware. The complete Code Validation Tools chain including the VHDL Emulator, must be used , DUAL INSTRUCTION SET, JAVACARDTM AND NATIVE 4-STAGE PIPELINE 16 GENERAL PURPOSE 32-BIT REGISTERS , Code for single bit fail within a 32-bit word ­ 10 years data retention, 500,000 Erase/Write cycles , Memory and Peripheral accesses are controlled by a Memory Protection Unit that allows to implement


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PDF ST22XJ64 32-BIT ST22XJ64 24-BIT 160d/PRZ CRT2380 vhdl code for 32bit data memory vhdl code for rsa 32 bit risc processor using vhdl vhdl code for DES algorithm UART using VHDL ICE POD vhdl code for memory card ST22
vhdl code for DES algorithm

Abstract: vhdl code for rsa vhdl code for memory card vhdl program of smartcard vhdl code for Rom 1024 byte vhdl code for 4 bit ram ST22 ST22XJ64 flash memory controller vhdl code
Text: control ­ Domain switching securely controlled by protected Context Stack ­ Native/Java, Code /Data , Code Validation Tools chain including the VHDL Emulator, must be used for both the hardware, software , AND NATIVE s 4-STAGE PIPELINE s 16 GENERAL PURPOSE 32-BIT REGISTERS, AND 10 SPECIAL REGISTERS s 4 , CLOCK FREQUENCY SENSORS MEMORY s HIGHLY RELIABLE CMOS EEPROM TECHNOLOGY ­ Error Correction Code for , Direct JavaCardTM byte code execution provides high performance advantage over processors that emulate


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PDF ST22XJ64 32-BIT 24-BIT 160d/PRZ vhdl code for DES algorithm vhdl code for rsa vhdl code for memory card vhdl program of smartcard vhdl code for Rom 1024 byte vhdl code for 4 bit ram ST22 ST22XJ64 flash memory controller vhdl code
1999 - vhdl projects abstract and coding

Abstract: vhdl code CRC vme vhdl ISA CODE VHDL i960RP
Text: the design under test, or DUT. The top-level file is usually composed of structural VHDL code that , these would be the place to start. The codes can be stored in the VHDL code of the CPU model, or could , functions implemented directly in VHDL code . This was less efficient than a model that used a test language , two architectures. A main process embedded in the VHDL code drives the first itself. The test , Behavioral Modeling in VHDL Simulations The Benefits of Higher Levels of Abstraction in Complex


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1999 - ISA CODE VHDL

Abstract: vhdl code for simple microprocessor esperan vhdl projects abstract and coding vhdl code CRC 32 i960RP
Text: top-level file is usually composed of structural VHDL code that ties the various models together as , these would be the place to start. The codes can be stored in the VHDL code of the CPU model, or could , implemented directly in VHDL code . This was less efficient than a model that used a test language parser to , architectures. A main process embedded in the VHDL code drives the first itself. The test language-parsing , Behavioral Modeling in VHDL Simulations The Benefits of Higher Levels of Abstraction in Complex


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2001 - analog to digital converter vhdl coding

Abstract: XAPP355 vhdl code for time division multiplexer adc controller vhdl code vhdl code for parallel to serial converter vhdl coding for analog to digital converter adc controller vhdl code download handspring vhdl code 16 bit processor serial analog to digital converter vhdl code
Text: ADC in a portable handheld application. This document will provide an explanation of the VHDL code , SRAM Figure 1: High Level Block Diagram Usage The VHDL code distributed with this document is , VHDL code can be edited to specify various aspects of the ADS7870 which include: · Initialization , conversion results should be written Designers who do not wish to understand the VHDL code in detail can , . The VHDL code in this design allows the user to customize the register usage. CS must remain Low in


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PDF XAPP355 ADS7870 analog to digital converter vhdl coding XAPP355 vhdl code for time division multiplexer adc controller vhdl code vhdl code for parallel to serial converter vhdl coding for analog to digital converter adc controller vhdl code download handspring vhdl code 16 bit processor serial analog to digital converter vhdl code
1993 - vhdl structural code program for 2-bit magnitude

Abstract: vhdl code for bus invert coding circuit 4 BIT ALU design with vhdl code using structural vhdl code direct digital synthesizer vhdl code for a updown counter for FPGA ABEL-HDL Reference Manual 8 BIT ALU design with vhdl code using structural P22V10 vhdl code for D Flipflop synchronous 8 BIT ALU using vhdl
Text: code fragment also demonstrates how to include comments in VHDL source code . The double-hyphen , have a guaranteed power-up state. Therefore, when writing VHDL code , it is best not to use initial , predefined VHDL data types include: · numeric (integer or real) · boolean · character · , . Two encoding schemes are used by the VHDL Synthesizer for numeric types: · Numeric types and , VHDL Reference Manual 096-0400-003 March 1997 Synario Design Automation, a division of


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1998 - vhdl code for accumulator

Abstract: VHDL code for dac vhdl code to generate sine wave XILINX vhdl code NCO VHDL code for band pass Filter vhdl code for FFT 4096 point Numerically Controlled Oscillator vhdl code to generate staircase wave vhdl for 8 point fft in xilinx code for NCO
Text: Numerically Controlled Oscillator December 30, 1998 Product Specification phase_inc R , Functional Description The Numerically Controlled Oscillator (NCO) module generates a digital "staircase" , stores the phase increment value, Numerically Controlled Oscillator which is continually integrated , (in Hertz) of the sinusoid. In the context of a numerically controlled oscillator , the time interval , recipe. VHDL instantiation code and a schematic symbol are created along with the netlist for the


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PDF X8820r vhdl code for accumulator VHDL code for dac vhdl code to generate sine wave XILINX vhdl code NCO VHDL code for band pass Filter vhdl code for FFT 4096 point Numerically Controlled Oscillator vhdl code to generate staircase wave vhdl for 8 point fft in xilinx code for NCO
1998 - quadrature phase sine wave generator

Abstract: vhdl code to generate staircase wave vhdl code for FFT 4096 point vhdl code to generate sine wave vhdl code for accumulator Numerically Controlled Oscillator VHDL code for band pass Filter precision Sine Wave Generator amplitude demodulation using xilinx system generator analog to digital converter vhdl coding
Text: Dual Channel Numerically Controlled Oscillator December 30, 1998 Product Specification R , Numerically Controlled Oscillator with In-phase and Quadrature outputs Input phase increment resolution , Dual Channel Numerically Controlled Oscillator with in-phase and quadrature outputs (NCOIQ) module , the analog domain. Dual Channel Numerically Controlled Oscillator The module comprises an , . In the context of a numerically controlled oscillator , the time interval, , is determined by the


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PDF X8820r quadrature phase sine wave generator vhdl code to generate staircase wave vhdl code for FFT 4096 point vhdl code to generate sine wave vhdl code for accumulator Numerically Controlled Oscillator VHDL code for band pass Filter precision Sine Wave Generator amplitude demodulation using xilinx system generator analog to digital converter vhdl coding
1999 - vhdl code to generate sine wave

Abstract: Numerically Controlled Oscillator vhdl code for FFT 16 point vhdl code for FFT 4096 point X9025 quadrature phase sine wave generator vhdl code to generate staircase wave XILINX vhdl code NCO precision Sine Wave Generator matlab
Text: Dual Channel Numerically Controlled Oscillator V1.0.3 December 17, 1999 Product Specification , · · Fully parameterized Dual Channel Numerically Controlled Oscillator with In-phase and , Parameterization Window December 17, 1999 1 Dual Channel Numerically Controlled Oscillator V1.0.3 Functional Description The Dual Channel Numerically Controlled Oscillator with in-phase and quadrature , . In the context of a numerically controlled oscillator , the time interval, , is determined by the


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PDF XC4000E, vhdl code to generate sine wave Numerically Controlled Oscillator vhdl code for FFT 16 point vhdl code for FFT 4096 point X9025 quadrature phase sine wave generator vhdl code to generate staircase wave XILINX vhdl code NCO precision Sine Wave Generator matlab
2002 - multiplier accumulator MAC code VHDL

Abstract: multiplier accumulator MAC code verilog verilog code for 16 bit multiplier addition accumulator MAC code verilog 8 bit unsigned multiplier using vhdl code VHDL code of DCT by MAC ALTMULT_ACCUM vhdl code for complex addition VHDL code DCT vhdl code for accumulator
Text: as shift registers. Figures 1 and 2 show sample Verilog and VHDL code , respectively, for , input, output, or pipeline registers. f Associated with this application note are sample code , input, output, and pipeline registers along with the simple multiplier. Figure 1. Verilog HDL Code for , DSP Blocks in the LeonardoSpectrum Software Figure 2. VHDL Code for Inferring lpm_mult (Unsigned 8 , show sample Verilog and VHDL code , respectively, for inferring the altmult_accum megafunction in the


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PDF an194 2002a multiplier accumulator MAC code VHDL multiplier accumulator MAC code verilog verilog code for 16 bit multiplier addition accumulator MAC code verilog 8 bit unsigned multiplier using vhdl code VHDL code of DCT by MAC ALTMULT_ACCUM vhdl code for complex addition VHDL code DCT vhdl code for accumulator
1999 - XILINX vhdl code NCO

Abstract: low pass Filter VHDL code vhdl code for accumulator VHDL code for dac vhdl code to generate staircase wave 3 phase generator sine amplitude demodulation using xilinx system generator vhdl code to generate sine wave vhdl for 8 point fft in xilinx VHDL code for band pass Filter
Text: Numerically Controlled Oscillator V1.0.3 December 17, 1999 Product Specification R , Numerically Controlled Oscillator (NCO) module generates a digital "staircase" approximation to a sine (or , Digital-to-Analog Converter (DAC) for use in the analog domain. Numerically Controlled Oscillator V1.0.3 The , . In the context of a numerically controlled oscillator , the time interval, , is determined by the , parameterized VHDL recipe. VHDL instantiation code and a schematic symbol are created along with the netlist


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PDF X9025 XC4000E, XILINX vhdl code NCO low pass Filter VHDL code vhdl code for accumulator VHDL code for dac vhdl code to generate staircase wave 3 phase generator sine amplitude demodulation using xilinx system generator vhdl code to generate sine wave vhdl for 8 point fft in xilinx VHDL code for band pass Filter
2002 - vhdl code for accumulator

Abstract: 8 bit unsigned multiplier using vhdl code 8 bit multiplier using vhdl code multiplier accumulator MAC code VHDL multiplier accumulator MAC code verilog vhdl code for 8 bit shift register addition accumulator MAC code verilog verilog code for 16 bit multiplier vhdl coding for pipeline VHDL code of DCT by MAC
Text: code in these text files use the input, output, and pipeline registers along with the simple , : Design Guidelines for Using DSP Blocks in the Synplify Software Figure 2. VHDL Code for Inferring , VHDL code , respectively, for inferring the altmult_accum megafunction in the Synplify software. These , 193: Design Guidelines for Using DSP Blocks in the Synplify Software Figure 5. VHDL Code for , Verilog and VHDL code , respectively, for inferring altmult_add. These samples do not use any of the


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PDF an193 vhdl code for accumulator 8 bit unsigned multiplier using vhdl code 8 bit multiplier using vhdl code multiplier accumulator MAC code VHDL multiplier accumulator MAC code verilog vhdl code for 8 bit shift register addition accumulator MAC code verilog verilog code for 16 bit multiplier vhdl coding for pipeline VHDL code of DCT by MAC
2010 - booth multiplier code in vhdl

Abstract: vhdl code for Booth multiplier verilog code pipeline square root 4-bit AHDL adder subtractor 7,4 bit hamming decoder by vhdl multiplier accumulator MAC code VHDL algorithm vhdl code for 4 bit updown counter 3 bit booth multiplier using verilog code low pass fir Filter VHDL code vhdl code for a updown counter
Text: ; endmodule VHDL Component Declaration The VHDL component declaration is located in the VHDL Design File (.vhd) LPM_PACK.vhd in the \libraries\ vhdl \lpm directory , -1 downto 0); OVERFLOW : out std_logic); end component; VHDL LIBRARY_USE Declaration The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration. LIBRARY lpm; USE , . LPM_HINT String No Allows you to specify Altera-specific parameters in VHDL design files (.vhd).


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PDF UG-01063-2 booth multiplier code in vhdl vhdl code for Booth multiplier verilog code pipeline square root 4-bit AHDL adder subtractor 7,4 bit hamming decoder by vhdl multiplier accumulator MAC code VHDL algorithm vhdl code for 4 bit updown counter 3 bit booth multiplier using verilog code low pass fir Filter VHDL code vhdl code for a updown counter
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