2000  vhdl code 16 bit LFSR
Abstract: vhdl code 8 bit LFSR vhdl code 4 bit LFSR vhdl code 10 bit LFSR vhdl code 16 bit LFSR with VHDL simulation output verilog code 8 bit LFSR verilog code 16 bit LFSR verilog code 32 bit LFSR verilog code 5 bit LFSR pseudo random generator
Text: input bits  24bit pseudo random generator with polynomial (1C20008)16 and seed (557074)16 2 , pseudo random generator , implemented as a linear feedback shift register (LFSR). The LFSR value v is , pseudo random generator and a set of comparators that compare the pseudo random value against the , Customizable VHDL source code available, allowing generation of different netlist versions · Customized , a quantizer at the channel output)  Parallel programming data bus width  Pseudo Random

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I10148
vhdl code 16 bit LFSR
vhdl code 8 bit LFSR
vhdl code 4 bit LFSR
vhdl code 10 bit LFSR
vhdl code 16 bit LFSR with VHDL simulation output
verilog code 8 bit LFSR
verilog code 16 bit LFSR
verilog code 32 bit LFSR
verilog code 5 bit LFSR
pseudo random generator

Not Available
Abstract: No abstract text available
Text: PRNG1 Cryptographically Secure Pseudo Random Number Generator IP Core www.ipcores.com , PRNG1 Cryptographically Secure Pseudo Random Number Generator IP Core www.ipcores.com Pin , Cryptographically Secure Pseudo Random Number Generator IP Core export administration regulations. See the IP , Cryptographically Secure Pseudo Random Number Generator IP Core Deliverables HDL Source Licenses Netlist , fully functional and synthesizable Verilog or VHDL for Actel programmable devices PRNG1 core is

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SP80090.
SP80090
256bit

2000  pn sequence generator
Abstract: vhdl code 16 bit LFSR verilog code 16 bit LFSR verilog code 8 bit LFSR vhdl code for pseudo random sequence generator vhdl code for 32 bit pn sequence generator vhdl code 8 bit LFSR verilog code for pseudo random sequence generator in qpsk modulation VHDL CODE vhdl code for 9 bit parity generator
Text: being transmitted is spread across a wide radio spectrum using a pseudo random binary sequence unique to each user. Every data bit of a user signal is multiplied by many bits of a pseudo random binary sequence . This sequence is created by a PN generator and often referred to as a PNCode. The PNCodes , schemes. The PN Generator HDL code therefore implements two LFSRs, one for the "I" channel and one for , Generators A Pseudorandom Noise (PN) sequence / code is a binary sequence that exhibits randomness

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XAPP211
16bit
SRL16
pn sequence generator
vhdl code 16 bit LFSR
verilog code 16 bit LFSR
verilog code 8 bit LFSR
vhdl code for pseudo random sequence generator
vhdl code for 32 bit pn sequence generator
vhdl code 8 bit LFSR
verilog code for pseudo random sequence generator in
qpsk modulation VHDL CODE
vhdl code for 9 bit parity generator

2000  vhdl code for 32 bit pn sequence generator
Abstract: vhdl code 8 bit LFSR vhdl code 16 bit LFSR vhdl code for pseudo random sequence generator vhdl code for 7 bit pseudo random sequence generator vhdl code for pn sequence generator qpsk modulation VHDL CODE 4 bit pn sequence generator vhdl code for pn sequence generator using lfsr vhdl code 12 bit LFSR
Text: Verilog and VHDL code examples have been written for the PN Generator module. The PN Generator provides , being transmitted is spread across a wide radio spectrum using a pseudo random binary sequence unique to each user. Every data bit of a user signal is multiplied by many bits of a pseudo random binary sequence . This sequence is created by a PN generator and often referred to as a PNCode. The PNCodes , msequences (S), for a given length of shift register is defined by: S (L  1) ÷ N Gold Code Generator

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XAPP211
16bit
SRL16
vhdl code for 32 bit pn sequence generator
vhdl code 8 bit LFSR
vhdl code 16 bit LFSR
vhdl code for pseudo random sequence generator
vhdl code for 7 bit pseudo random sequence generator
vhdl code for pn sequence generator
qpsk modulation VHDL CODE
4 bit pn sequence generator
vhdl code for pn sequence generator using lfsr
vhdl code 12 bit LFSR

simulation for prbs generator in matlab
Abstract: block diagram prbs generator in matlab vhdl code for pseudo random sequence generator in vhdl code for 16 prbs generator vhdl code for pseudo random sequence generator prbs pattern generator using vhdl pulse shaping FILTER implementation xilinx fifo vhdl xilinx vhdl code for 7 bit pseudo random sequence generator rAised cosine FILTER
Text: 16bit pseudo random binary sequence (PRBS) generator which is initialized at beginning of a Data , 2 for MW_ ATSC Modulator Core emission mask. Core Modifications Source code uses VHDL generics , Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL synthesizable source code , NGC implementation file MindWay S.r.l. Constraints Files Centro Direzionale , Xilinx ISE User Constrains File VHDL Test Bench and Test Vectors Instantiation Templates VHDL

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2000  verilog code 16 bit LFSR
Abstract: verilog code 8 bit LFSR vhdl code for 7 bit pseudo random sequence generator vhdl code 12 bit LFSR verilog code 32 bit LFSR vhdl code for pseudo random sequence generator in verilog code 5 bit LFSR verilog code for pseudo random sequence generator in vhdl code for 32 bit pn sequence generator vhdl code for pseudo random sequence generator
Text: being transmitted is spread across a wide radio spectrum using a pseudo random binary sequence unique to each user. Every data bit of a user signal is multiplied by many bits of a pseudo random binary sequence . This sequence is created by a PN generator and often referred to as a PNCode. The PNCodes , Using the SRL Macro HDL Code R Verilog and VHDL code examples have been written for the PN , Generator HDL code therefore implements two LFSRs, one for the "I" channel and one for the "Q" channel. In

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XAPP211
16bit
SRL16
verilog code 16 bit LFSR
verilog code 8 bit LFSR
vhdl code for 7 bit pseudo random sequence generator
vhdl code 12 bit LFSR
verilog code 32 bit LFSR
vhdl code for pseudo random sequence generator in
verilog code 5 bit LFSR
verilog code for pseudo random sequence generator in
vhdl code for 32 bit pn sequence generator
vhdl code for pseudo random sequence generator

vhdl code for ofdm
Abstract: vhdl code for ofdm transmitter OFDM Matlab code ofdm code in vhdl OFDM QPSK simulation OFDM matlab program CODES VHDL PROGRAM for ofdm vhdl code for 8 point ifft in xilinx simulation for prbs generator in matlab vhdl code for block interleaver
Text: block inverts a sync byte every eight sync byte received.The polynomial for the pseudo random binary sequence (PRBS) generator is: 1 + x14 + x15. The sync byte of the first packet is bitwise inverted from 47HEX to B8HEX, and the PRBS generator is loaded with the seed sequence "100101010000000". During the , the mother code are G1=171OCT for X output and G2=133 OCT for Y output. The two bit stream, X and Y , insertion. Core Modifications Source code uses VHDL generics in order to customize MW_DVBT/H Modulator

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vhdl code for ofdm
Abstract: ofdm matlab simulation block prbs generator using vhdl vhdl code for 16 prbs generator vhdl code for pseudo random sequence generator vhdl code for block interleaver ofdm code in vhdl DVBT modulator vhdl code for ofdm transmitter vhdl code for interleaver
Text: for the pseudo random binary sequence (PRBS) generator is: 1 + x14 + x15. The sync byte of the first packet is bitwise inverted from 47HEX to B8HEX, and the PRBS generator is loaded with the seed sequence , for a range of puntured convolutional codes, based on a mother convolutional code of rate 1/2 with 64 , polynomials of the mother code are G1=171OCT for X output and G2=133 OCT for Y output. The two bit stream, X , symbols by guard interval insertion. Core Modifications Source code uses VHDL generics in order to

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2005  vhdl code 16 bit LFSR
Abstract: verilog code 16 bit LFSR vhdl code for 32 bit pn sequence generator VHDL 32bit pn sequence generator vhdl code for shift register using d flipflop SRL16 vhdl code for pn sequence generator fpga cdma by vhdl examples vhdl code for rs232 receiver using fpga vhdl code 16 bit LFSR with VHDL simulation output
Text: . This document provides generic VHDL and Verilog submodules and reference code examples for , in the proper data. This requires predictable timing for the load command. VHDL Inference Code , design. Templates for the SHIFT_REGISTER_16_C module are provided in VHDL and Verilog code as an , special type of PN sequence is a Gold code generator , which can be created from SRL16based LFSRs. · , Primitive Initialization in VHDL and Verilog Code A shift register can be initialized in VHDL or Verilog

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SRL16)
XAPP465
SRL16
16bit
vhdl code 16 bit LFSR
verilog code 16 bit LFSR
vhdl code for 32 bit pn sequence generator
VHDL 32bit pn sequence generator
vhdl code for shift register using d flipflop
vhdl code for pn sequence generator
fpga cdma by vhdl examples
vhdl code for rs232 receiver using fpga
vhdl code 16 bit LFSR with VHDL simulation output

2000  vhdl code scrambler
Abstract: scrambling design of scrambler and descrambler verilog code for implementation of des error correction code in vhdl vhdl code Linear block code vhdl code CRC 32 crc 16 verilog text scrambling vhdl code for pseudo random sequence generator
Text: Generator (SRG) generates the scrambling sequence for the input data stream. The generator composed of a , transmission · Customizable VHDL source code available, allowing generation of different netlist versions · , generator  Reset value of the scrambling sequence generator Applications Core Specifics1 Supported , from byte 1 to 5 inclusive  Scrambling sequence generator with: feedback polynomial = x31+x28 , PBCLK_IN N_PBRST Scrambling Sequence Shift Register Generator Scrambling Sequence HEC

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I10148
vhdl code scrambler
scrambling
design of scrambler and descrambler
verilog code for implementation of des
error correction code in vhdl
vhdl code Linear block code
vhdl code CRC 32
crc 16 verilog
text scrambling
vhdl code for pseudo random sequence generator

2000  design of scrambler and descrambler
Abstract: vhdl code scrambler verilog code for implementation of des error correction code in vhdl vhdl code for scrambler descrambler vhdl code for phase shift Descrambler crc 16 verilog cell phone vhdl code for pseudo random sequence generator
Text: Generator The Descrambling Sequence SRG generates the descrambling sequence for the received input data , transmission · Customizable VHDL source code available, allowing generation of different netlist versions · , sequence generator  Reset value of the descrambling sequence generator Applications Core , ATM cell header from byte 1 to 5 inclusive  Descrambling sequence generator with: feedback , CORE IBUFG IBUF PBCLK_IN N_PBRST Descrambling Sequence Shift Register Generator

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I10148
53bit
design of scrambler and descrambler
vhdl code scrambler
verilog code for implementation of des
error correction code in vhdl
vhdl code for scrambler descrambler
vhdl code for phase shift
Descrambler
crc 16 verilog
cell phone
vhdl code for pseudo random sequence generator

1994  sol 20 Package XILINX
Abstract: XC2064 XC3090 XC4005 XC5210 verilog code for spi4.2 to fifo
Text: . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Random Testcase Sample Code . . . . . . . , in the CORE Generator GUI. For additional assistance installing the IP Update, contact , Generator system, do the following: 1. Start the CORE Generator system. For help starting and using , Options  For Design Entry, select either VHDL or Verilog.  For Vendor, select Synplicity or , timing. The simulation models provided are either in VHDL or Verilog, depending on the CORE Generator

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UG231
XC2064,
XC3090,
XC4005,
XC5210
sol 20 Package XILINX
XC2064
XC3090
XC4005
verilog code for spi4.2 to fifo

1999  vhdl code CRC 32
Abstract: vhdl code for pseudo random sequence generator in "network interface cards" vhdl code for ethernet mac spartan 3
Text: backoff. A maximal length pseudo random sequence generator is seeded and is used to generate the integer , padding. RANDOM_SEED[9:0] Input Seed value for random number generator used to compute backoff LOAD_RANDOM_SEED Input Goes high for a period more than one clock in order to load RANDOM_SEED into backoff random , perform special modifications for additional charge. However source code is available for each core for , detection Extensive statistics information on transmit frames for RMON and MIBs Media Independent Interface

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4000EX
4028EX2
V1504,
V2004,
V3004
4028EX
16bit
vhdl code CRC 32
vhdl code for pseudo random sequence generator in
"network interface cards"
vhdl code for ethernet mac spartan 3

1998  VHDL CODE FOR 16 bit LFSR in PRBS
Abstract: vhdl code for 8 bit barrel shifter vhdl code 8 bit LFSR vhdl code for 9 bit parity generator vhdl code for 8 bit parity generator vhdl code for 8 bit common bus vhdl code for 16 prbs generator prbs using lfsr vhdl code for pseudo random sequence generator in vhdl code for a 9 bit parity generator
Text: . The full VHDL source code for the PLDs in this application note is listed in Appendixes B and C. This , Data Out Use HOTLink for 9 and 10Bit Data Appendix B. Scrambler VHDL Source Code  , ; 13 Use HOTLink for 9 and 10Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8bit data , documented in this application note. Schematics and VHDL code are included in this document. Serial

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10Bit
8B/10B
8B/10B.
VHDL CODE FOR 16 bit LFSR in PRBS
vhdl code for 8 bit barrel shifter
vhdl code 8 bit LFSR
vhdl code for 9 bit parity generator
vhdl code for 8 bit parity generator
vhdl code for 8 bit common bus
vhdl code for 16 prbs generator
prbs using lfsr
vhdl code for pseudo random sequence generator in
vhdl code for a 9 bit parity generator

1999  vhdl code scrambler
Abstract: prbs generator using vhdl vhdl code for pseudo random sequence generator vhdl code for 7 bit pseudo random sequence generator vhdl code for 4 bit barrel shifter vhdl code for 16 bit Pseudorandom Streams Generation Using HOTLink vhdl code 10 bit LFSR prbs pattern generator using vhdl VHDL CODE FOR 16 bit LFSR in PRBS
Text: . The full VHDL source code for the PLDs in this application note is listed in Appendices B and C. This , Data Out Use HOTLink for 9 and 10Bit Data Appendix B. Scrambler VHDL Source Code  , ; 13 Use HOTLink for 9 and 10Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8bit data , documented in this application note. Schematics and VHDL code are included in this document. Serial

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10Bit
8B/10B
8B/10B.
vhdl code scrambler
prbs generator using vhdl
vhdl code for pseudo random sequence generator
vhdl code for 7 bit pseudo random sequence generator
vhdl code for 4 bit barrel shifter
vhdl code for 16 bit Pseudorandom Streams Generation
Using HOTLink
vhdl code 10 bit LFSR
prbs pattern generator using vhdl
VHDL CODE FOR 16 bit LFSR in PRBS

2000  vhdl code for ethernet mac spartan 3
Abstract: vhdl code for 8bit calculator vhdl code CRC CRC32 vhdl code for pseudo random sequence generator "network interface cards"
Text: pseudo random sequence generator is seeded and is used to generate the integer. January 10, 2000 , Input TRUE enables short frame padding. RANDOM_SEED[9:0] Input Seed value for random number generator used to compute backoff LOAD_RANDOM_SEED Input Goes high for a period more than one clock in order to load RANDOM_SEED into backoff random number generator . Host Interface TXMITTER_ENB Input , perform special modifications for additional charge. However source code is available for each core for

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4000EX
4028EX2
4000X,
4028EX
vhdl code for ethernet mac spartan 3
vhdl code for 8bit calculator
vhdl code CRC
CRC32
vhdl code for pseudo random sequence generator
"network interface cards"

2000  verilog code 16 bit LFSR
Abstract: vhdl code 16 bit LFSR verilog code 8 bit LFSR vhdl code 8 bit LFSR simple LFSR 8 shift register by using D flipflop verilog hdl code for parity generator vhdl code Pseudorandom Streams Generator SRL16 VHDL 32bit pn sequence generator
Text: work with current versions of Express, Exemplar, and Synplify. For both VHDL and Verilog code , the , pseudorandom noise (PN) code generator (XAPP211) and Gold code generators (XAPP217) commonly used in Code , time; the longer the LFSR, however, the longer the sequence of random numbers before pattern , detail. LFSR 1 Length N PN Code Out LFSR 2 Length N X220_01_010101 Figure 1: Gold Code Generator , maximal length sequence for a shift register of length N is referred to as an msequence, and is defined

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XAPP220
XAPP211)
XAPP217)
SRL16
41stage,
41stage
SRL16s.
verilog code 16 bit LFSR
vhdl code 16 bit LFSR
verilog code 8 bit LFSR
vhdl code 8 bit LFSR
simple LFSR
8 shift register by using D flipflop
verilog hdl code for parity generator
vhdl code Pseudorandom Streams Generator
SRL16
VHDL 32bit pn sequence generator

2001  vhdl code for 16 prbs generator
Abstract: vhdl code for 9 bit parity generator free verilog code of prbs pattern generator vhdl code for 8 bit parity generator verilog code for pseudo random sequence generator in vhdl code for a 9 bit parity generator sonet testbench Transistor Substitution Data Book 1993 CRC16 GR499CORE
Text: Frame Personal Computer Performance Monitor Pseudo Random Bit Sequence Remote Defect Indication , Generator transmits codes to the Cbit parity FEAC channel via the TXFRMR. The idle code is used to disable , . Software generates a pseudo random payload bit pattern with a length of 216to1. The result is fed back , . rndata Input Line receive negative data for dual rail interface lcv Input Line code , countries. Altera Corporation acknowledges the trademarks of other organizations for their respective

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2000  turbo codes matlab simulation program
Abstract: Turbo code Decoder posteriori TURBO Encoder/Decoder source coding turbo encoder circuit sova 5 to 32 decoder using 3 to 8 decoder vhdl code turbo decoder turbo codes matlab code vhdl code for bit interleaver InterleaverDeinterleaver
Text: pseudo random interleaver into encoder 2. The encoded bit streams can be punctured to save bandwidth , random independent errors. For channels with memory, such as fading channels, this method is not , acknowledges the trademarks of other organizations for their respective products or services mentioned in this , agreement to the contrary, Altera assumes no liability for Altera applications assistance, customer , process in which such semiconductor devices might be or are used. Altera products are not authorized for

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UGTURBO01
turbo codes matlab simulation program
Turbo code Decoder posteriori
TURBO Encoder/Decoder source coding
turbo encoder circuit
sova
5 to 32 decoder using 3 to 8 decoder vhdl code
turbo decoder
turbo codes matlab code
vhdl code for bit interleaver
InterleaverDeinterleaver

2002  vhdl code CRC
Abstract: vhdl code CRC 32 vhdl code for 9 bit parity generator CRC8 and crc16 CRC32 for FDDI vhdl code for 8bit parity generator binary cyclic code program in vhdl vhdl code for parity generator 8bit input crc16 ccitt vhdl code CRC32
Text: application generates VHDL code specifically for use in the SXA, ProASIC, and ProASICPLUS families. The RTL VHDL code generated is simply designed to take advantage of the SXA silicon features. This is , v4.0 Cyclic Redundancy Code Generator Macro Fe a t ur es Fu n ct i o n al D e sc r i p t i on The highlights of the Cyclic Redundancy Codes (CRC) Generator are as follow: Many designers , User defined polynomial · A Win32 console application that generates VHDL code · Performance

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16bit
32bit
CRC10
vhdl code CRC
vhdl code CRC 32
vhdl code for 9 bit parity generator
CRC8 and crc16
CRC32 for FDDI
vhdl code for 8bit parity generator
binary cyclic code program in vhdl
vhdl code for parity generator 8bit input
crc16 ccitt
vhdl code CRC32

2002  BPSK modulation VHDL CODE
Abstract: vhdl code for bpsk modulation 16 bit qpsk VHDL CODE hardware implementation of bpsk bpsk simulink matlab QPSK using xilinx qpsk simulink matlab system generator matlab ise qpsk modulation VHDL CODE Signaltonoise ratio matlab
Text: ., August 2001. 2. P. Chu and R. Jones, "Design Techniques of FPGABased Random Number Generator ," , Specification Features LogiCORETM Facts · Designed for VirtexTMII and VirtexII ProTM using structural VHDL · Probability density function (PDF) deviates less than 0.2 percent from the Gaussian PDF for x < 4.8 and is obtained from a closedform expression Core Specifics Supported Device , theorem as described in [1] · Period of generated noise sequence is ~ 2190 = 1.57×1057 samples ·

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DS210
BPSK modulation VHDL CODE
vhdl code for bpsk modulation
16 bit qpsk VHDL CODE
hardware implementation of bpsk
bpsk simulink matlab
QPSK using xilinx
qpsk simulink matlab
system generator matlab ise
qpsk modulation VHDL CODE
Signaltonoise ratio matlab

2000  vhdl code CRC
Abstract: vhdl code for 8 bit parity generator 54SXA CRC8 and crc16 binary cyclic code program in vhdl vhdl code CRC 32 CRC8 vhdl code serial CRC8 CCITT16 CRC10
Text: application generates VHDL code specifically for use in the 54SXA family. The RTL VHDL code generated is , v2.0 Cyclic Redundancy Code Generator Macro Fe a t ur es Fu n ct i o n al D e sc r i p t i on The highlights of the Cyclic Redundancy Codes (CRC) Generator are as follow: Many designers use the CRC as an alternative to parity and checksum calculation for checking (and sometimes , · User defined polynomial · A Win32 console application that generates VHDL code · Performance

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16bit
32bit
CRC10
vhdl code CRC
vhdl code for 8 bit parity generator
54SXA
CRC8 and crc16
binary cyclic code program in vhdl
vhdl code CRC 32
CRC8
vhdl code serial CRC8
CCITT16

2009  simple 32 bit LFSR using verilog
Abstract: verilog hdl code for traffic light control verilog code 16 bit LFSR cyclic redundancy check verilog source 25.263 EP1SGX40GF1020C5 verilog code 8 bit LFSR in scrambler CRC32 CRC16 8B10B
Text: functional simulation models for use in Alterasupported VHDL and Verilog HDL simulators Support for , ; the MegaWizard PlugIn Manager supports VHDL and Verilog HDL. For this example, select Verilog HDL , industrystandard VHDL and Verilog HDL simulators. c You may use these models only for simulation and not for , for products or services. UG07051.10 Contents Chapter 1. About This MegaCore Function , ) File Generation ( For the Verilog HDL Testbench) . . . . . . . . . . . . . . . . 58 Testbench TimeOut

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2010  vhdl code for traffic light control
Abstract: vhdl code for crc16 using lfsr verilog code 8 bit LFSR in scrambler verilog code 16 bit LFSR SerialLite vhdl code 16 bit LFSR with VHDL simulation output verilog code for traffic light control vhdl code CRC verilog code 8 bit LFSR 0705111
Text: series Lane order reversal IP functional simulation models for use in Alterasupported VHDL , . 4. Select the output file type for your design; the MegaWizard PlugIn Manager supports VHDL , requires cyclic redundancy code (CRC) checking, turn on the Enable CRC option for your chosen packet type , allows for fast functional simulation of IP using industrystandard VHDL and Verilog HDL simulators. c , for products or services. UG07051.11 Contents Chapter 1. About This MegaCore Function

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2001  vhdl code for nand flash memory
Abstract: 8192Kx8 NAND flash memory K9F4008W0A XAPP354 xilinx mp3 vhdl decoder NAND flash differences XAPP338 XCR3032XLVQ44 samsung date code
Text: Flash is a random access device appropriate for code storage applications. NAND technology organizes , lowest power CPLD available and the ideal target device for memory interface applications. The code for , ready for the next operation. When RY/BY# is low, an internal program, erase, or random read operation , to read the manufacturer code and device code . CPLD Design For more information on the ABEL , "HDL Code " on page 14 for more information). The CPLD design decodes system address commands to

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XAPP354
com/products/nvd/techdocs/22363
area/flash00/artic04
vhdl code for nand flash memory
8192Kx8
NAND flash memory
K9F4008W0A
XAPP354
xilinx mp3 vhdl decoder
NAND flash differences
XAPP338
XCR3032XLVQ44
samsung date code
