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Part Manufacturer Description Datasheet Download Buy Part
LTC1093CSW#PBF Linear Technology LTC1093 - 1, 2, 6 and 8 Channel, 10-Bit Serial I/O Data Acquisition Systems; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC1093CSW#TRPBF Linear Technology LTC1093 - 1, 2, 6 and 8 Channel, 10-Bit Serial I/O Data Acquisition Systems; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC1093CSW Linear Technology LTC1093 - 1, 2, 6 and 8 Channel, 10-Bit Serial I/O Data Acquisition Systems; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC1093CSW#TR Linear Technology LTC1093 - 1, 2, 6 and 8 Channel, 10-Bit Serial I/O Data Acquisition Systems; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC1093CN Linear Technology LTC1093 - 1, 2, 6 and 8 Channel, 10-Bit Serial I/O Data Acquisition Systems; Package: PDIP; Pins: 16; Temperature Range: 0°C to 70°C
LTC1091CN8 Linear Technology LTC1091 - 1, 2, 6 and 8 Channel, 10-Bit Serial I/O Data Acquisition Systems; Package: PDIP; Pins: 8; Temperature Range: 0°C to 70°C

vhdl code for binary data serial transmitter Datasheets Context Search

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2002 - cyclic redundancy check verilog source

Abstract: vhdl code manchester encoder vhdl code for manchester decoder verilog code for uart communication vhdl code for clock and data recovery vhdl manchester manchester code manchester verilog decoder manchester vhdl code for uart communication
Text: data cell, and a logic "0" is represented by a low level. Manchester code represents binary values by , . A UART is a serial communication circuit which uses NRZ code . To sample at mid-bit of the data cell , as reference for clock recovery, center sampling mdi Input Serial manchester data input , for the transmitter and receiver to distinguish between a command and data . Since the 3-bit wide , Verilog) Code Download Manchester Encoder-Decoder for Xilinx CPLDs VHDL (or Verilog) source code


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PDF XAPP339 XC9572, XCR3064XL, XC2C64 XAPP339 cyclic redundancy check verilog source vhdl code manchester encoder vhdl code for manchester decoder verilog code for uart communication vhdl code for clock and data recovery vhdl manchester manchester code manchester verilog decoder manchester vhdl code for uart communication
2000 - vhdl code manchester encoder

Abstract: manchester verilog decoder manchester code verilog line code manchester vhdl manchester vhdl code for nrz Manchester code vhdl code for binary data serial transmitter vhdl code for manchester decoder vhdl code for clock and data recovery
Text: _01_032700 Figure 1: Binary Values for NRZ and Manchester Codes Relative Advantages of NRZ/ Manchester Code , 1-800-255-7778 5 Manchester Encoder-Decoder for Xilinx CPLDs VHDL (or Verilog) Code Download R VHDL (or Verilog) source code and test benches are available for this design. THE DESIGN IS PROVIDED , Encoder-Decoder for Xilinx CPLDs Summary This application note provides a functional description of VHDL and Verilog source code for a Manchester Encoder Decoder. The reasons to use Manchester code are


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PDF XAPP339 XC9572 XCR3064XL XAPP339 vhdl code manchester encoder manchester verilog decoder manchester code verilog line code manchester vhdl manchester vhdl code for nrz Manchester code vhdl code for binary data serial transmitter vhdl code for manchester decoder vhdl code for clock and data recovery
2001 - vhdl code manchester encoder

Abstract: vhdl code for manchester decoder vhdl code for clock and data recovery manchester encoder manchester verilog decoder manchester code verilog vhdl manchester vhdl code for nrz vhdl manchester encoder manchester encoder xilinx
Text: _01_032700 Figure 1: Binary Values for NRZ and Manchester Codes Relative Advantages of NRZ/ Manchester Code , www.xilinx.com 1-800-255-7778 5 Manchester Encoder-Decoder for Xilinx CPLDs VHDL (or Verilog) Code Download R VHDL (or Verilog) source code and test benches are available for this design. THE DESIGN , Encoder-Decoder for Xilinx CPLDs Summary This application note provides a functional description of VHDL and Verilog source code for a Manchester Encoder Decoder. The reasons to use Manchester code are


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PDF XAPP339 XC9572 XCR3064XL XAPP339 vhdl code manchester encoder vhdl code for manchester decoder vhdl code for clock and data recovery manchester encoder manchester verilog decoder manchester code verilog vhdl manchester vhdl code for nrz vhdl manchester encoder manchester encoder xilinx
1998 - lms algorithm using verilog code

Abstract: lms algorithm using vhdl code ATM machine working circuit diagram using vhdl verilog code for lms adaptive equalizer for audio verilog code for lms adaptive equalizer digital IIR Filter VHDL code 8086 microprocessor based project verilog DTMF decoder qpsk demodulation VHDL CODE verilog code for fir filter using DA
Text: Data Communication (Telecom and Datacom) Digital Signal Processing (DSP) For additional details on , directly for an authorization code ; the AMPP partner will generate this code based on your MAX+PLUS II PC , File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL instantiation templates Megafunction , II software. The MAX+PLUS II software for PCs uses an embedded license system, based on the serial , offer pre-synthesized and pre-verified solutions for standard serial and parallel buses. Using AMPP


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1999 - 16650 uart

Abstract: uart 16650 timing vhdl code for fifo and transmitter D16950 test bench verilog code for uart 16550 uart 16750 baud rate "flow control" verilog code for uart communication in fpga verilog code for 8 bit shift register baud rate generator vhdl block diagram UART using VHDL
Text: communication bits (start, stop, and parity) to or from the serial data In UART mode receiver and transmitter , for INT buff. Parallel data output Driver disable output Transmitter ready output Receiver ready , Asynchronous Receiver/ Transmitter (UART) functionally identical to the OX16C950. The D16950 allows serial , and increase system efficiency by automatically controlling serial data flow through the RTS output , synchronize by external clock connected to RI ( for receiver and transmitter ) or to DSR ( only for receiver


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PDF D16950 D16950 OX16C950. 16650 uart uart 16650 timing vhdl code for fifo and transmitter test bench verilog code for uart 16550 uart 16750 baud rate "flow control" verilog code for uart communication in fpga verilog code for 8 bit shift register baud rate generator vhdl block diagram UART using VHDL
1999 - 16750 UART texas instruments

Abstract: vhdl code for fifo and transmitter uart 16750 verilog code for 8 bit fifo register uart 16750 baud rate verilog code for baud rate generator parallel to serial conversion verilog vhdl code for 8 bit parity generator vhdl code for 8 bit shift register vhdl code for binary data serial transmitter
Text: Asynchronous Receiver/ Transmitter (UART) functionally identical to the TL16C750. The D16750 allows serial , 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions , efficiency by automatically controlling serial data flow through the RTS output and the CTS input signals , receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data Independently controlled transmit, receive, line status, and data set


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PDF D16750 D16750 TL16C750. 16750 UART texas instruments vhdl code for fifo and transmitter uart 16750 verilog code for 8 bit fifo register uart 16750 baud rate verilog code for baud rate generator parallel to serial conversion verilog vhdl code for 8 bit parity generator vhdl code for 8 bit shift register vhdl code for binary data serial transmitter
1999 - design IP Uarts using verilog HDL

Abstract: uart vhdl code fpga verilog hdl code for parity generator verilog code for 8 bit fifo register asynchronous fifo design in verilog D16754 uart 16750 baud rate FLEX10KE D16750 APEX20KE
Text: serial data In UART mode receiver and transmitter are double buffered to eliminate a need for , VHDL , Verilog source code called HDL Source serial-interface Single Design license for , Asynchronous Receiver/ Transmitter (UART) functionally identical to the TL16C750. The D16750 allows serial , 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions , efficiency by automatically controlling serial data flow through the RTS output and the CTS input signals


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PDF D16750 D16750 TL16C750. design IP Uarts using verilog HDL uart vhdl code fpga verilog hdl code for parity generator verilog code for 8 bit fifo register asynchronous fifo design in verilog D16754 uart 16750 baud rate FLEX10KE APEX20KE
1999 - verilog hdl code for parity generator

Abstract: vhdl code for asynchronous fifo test bench verilog code for uart 16550 verilog code for baud rate generator verilog code for UART baud rate generator D16550 FLEX10KE vhdl code for Digital DLL uart vhdl code fpga APEX20KE
Text: Asynchronous Receiver/ Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial , 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions , Copyright 1999-2007 DCD ­ Digital Core Design. All Rights Reserved. Serial Data communications , serial data The DLL, DLM and THR registers are reset to all zeros In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU


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PDF D16550 D16550 TL16C550A. verilog hdl code for parity generator vhdl code for asynchronous fifo test bench verilog code for uart 16550 verilog code for baud rate generator verilog code for UART baud rate generator FLEX10KE vhdl code for Digital DLL uart vhdl code fpga APEX20KE
1999 - test bench verilog code for uart 16550

Abstract: verilog code for UART baud rate generator test bench code for uart 16550 verilog code for baud rate generator address generator logic vhdl code vhdl code for 4 bit even parity generator vhdl code for uart communication vhdl code for fifo and transmitter vhdl code for binary data serial transmitter baud rate generator vhdl
Text: bits (start, stop, and parity) to or from the serial data In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data , Asynchronous Receiver/ Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial , 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions , Copyright 1999-2009 DCD ­ Digital Core Design. All Rights Reserved. Serial Data communications


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PDF D16550 D16550 TL16C550A. D16752 D16754 D16950 D16X50 test bench verilog code for uart 16550 verilog code for UART baud rate generator test bench code for uart 16550 verilog code for baud rate generator address generator logic vhdl code vhdl code for 4 bit even parity generator vhdl code for uart communication vhdl code for fifo and transmitter vhdl code for binary data serial transmitter baud rate generator vhdl
1999 - test bench verilog code for uart 16550

Abstract: test bench code for uart 16550 verilog code for uart communication in fpga baud rate generator vhdl verilog hdl code for parity generator vhdl code for uart communication D16550 verilog code for uart communication vhdl code for fifo and transmitter uart vhdl code fpga
Text: , stop, and parity) to or from the serial data In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data , to 12 months. Single Design license for Source VHDL , Verilog source code called HDL , Asynchronous Receiver/ Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial , 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions


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PDF D16550 D16550 TL16C550A. test bench verilog code for uart 16550 test bench code for uart 16550 verilog code for uart communication in fpga baud rate generator vhdl verilog hdl code for parity generator vhdl code for uart communication verilog code for uart communication vhdl code for fifo and transmitter uart vhdl code fpga
1999 - verilog code 16 bit processor

Abstract: uart vhdl code fpga verilog hdl code for parity generator verilog code for 8 bit shift register D16450 verilog code for ring counter parallel to serial conversion verilog D16750 D16550 APEX20KC
Text: parity) to or from the serial data In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data Independently , time of use is limited to 12 months. Single Design license for VHDL , Verilog source code , producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use , programmable characteristics: serial-interface DELIVERABLES Source code : VHDL Source Code or/and


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PDF D16450 D16450 TL16C450. verilog code 16 bit processor uart vhdl code fpga verilog hdl code for parity generator verilog code for 8 bit shift register verilog code for ring counter parallel to serial conversion verilog D16750 D16550 APEX20KC
1998 - VHDL CODE FOR 16 bit LFSR in PRBS

Abstract: vhdl code for 8 bit barrel shifter vhdl code 8 bit LFSR vhdl code for 9 bit parity generator vhdl code for 8 bit parity generator vhdl code for 8 bit common bus vhdl code for 16 prbs generator prbs using lfsr vhdl code for pseudo random sequence generator in vhdl code for a 9 bit parity generator
Text: character or characters. By sending this Sync code , and searching for it in the serial data stream, the , bits. Because of its numerous advantages for serial data transmission, the 8B/10B code has been , Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8-bit data


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PDF 10-Bit 8B/10B 8B/10B. VHDL CODE FOR 16 bit LFSR in PRBS vhdl code for 8 bit barrel shifter vhdl code 8 bit LFSR vhdl code for 9 bit parity generator vhdl code for 8 bit parity generator vhdl code for 8 bit common bus vhdl code for 16 prbs generator prbs using lfsr vhdl code for pseudo random sequence generator in vhdl code for a 9 bit parity generator
1999 - vhdl code scrambler

Abstract: prbs generator using vhdl vhdl code for pseudo random sequence generator vhdl code for 7 bit pseudo random sequence generator vhdl code for 4 bit barrel shifter vhdl code for 16 bit Pseudorandom Streams Generation Using HOTLink vhdl code 10 bit LFSR prbs pattern generator using vhdl VHDL CODE FOR 16 bit LFSR in PRBS
Text: character or characters. By sending this Sync code , and searching for it in the serial data stream, the , bits. Because of its numerous advantages for serial data transmission, the 8B/10B code has been , Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8-bit data


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PDF 10-Bit 8B/10B 8B/10B. vhdl code scrambler prbs generator using vhdl vhdl code for pseudo random sequence generator vhdl code for 7 bit pseudo random sequence generator vhdl code for 4 bit barrel shifter vhdl code for 16 bit Pseudorandom Streams Generation Using HOTLink vhdl code 10 bit LFSR prbs pattern generator using vhdl VHDL CODE FOR 16 bit LFSR in PRBS
1999 - verilog code for UART baud rate generator

Abstract: vhdl code for uart communication test bench verilog code for uart 16550 test bench code for uart 16550 vhdl code for fifo and transmitter verilog hdl code for parity generator verilog code for uart communication VHDL description for an 8-bit even/odd parity vhdl code for 8-bit parity generator verilog code for uart communication in fpga
Text: communication bits (start, stop, and parity) to or from the serial data In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial , Asynchronous Receiver/ Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial , 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are , . APPLICATIONS Serial Data communications applications Modem interface KEY FEATURES Software


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PDF D16550 TL16C550A. verilog code for UART baud rate generator vhdl code for uart communication test bench verilog code for uart 16550 test bench code for uart 16550 vhdl code for fifo and transmitter verilog hdl code for parity generator verilog code for uart communication VHDL description for an 8-bit even/odd parity vhdl code for 8-bit parity generator verilog code for uart communication in fpga
2001 - XAPP029

Abstract: verilog rtl code of Crossbar Switch adc controller vhdl code XAPP172 Insight Spartan-II demo board 12-bit ADC interface vhdl code for FPGA vhdl code for pn sequence generator XAPP014 verilog code for cdma transmitter ADC DAC Verilog 2 bit Implementation
Text: . XAPP029 Serial Code Conversion Between BCD and Binary Binary-to-BCD and BCD-to-binary conversions are performed between serial binary values and parallel BCD values. XAPP030 Megabit FIFO in Two Chips: One LCA , FIFOs using the Block SelectRAM+ memory in the Spartan-II FPGAs. Verilog and VHDL code is available for , The design strategies for loadable and non-loadable binary counters are significantly different. This , the XC3000 series of FPGA devices. This information supplements the data sheets, and is provided for


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PDF Q4-01 XAPP004 XAPP005 XC3000 Desi49 XC18V00, XC9500XL, XC9500XV, XAPP501 XC9500, XAPP029 verilog rtl code of Crossbar Switch adc controller vhdl code XAPP172 Insight Spartan-II demo board 12-bit ADC interface vhdl code for FPGA vhdl code for pn sequence generator XAPP014 verilog code for cdma transmitter ADC DAC Verilog 2 bit Implementation
2000 - 32-Bit Parallel-IN Serial-OUT Shift Register

Abstract: 32-Bit sipo Shift Register vhdl code for interleaver vhdl code for block interleaver vhdl code for sipo vhdl code for asynchronous piso 32-Bit Parallel-IN parallel-OUT Shift Register design for block interleaver deinterleaver SRL16 Convolutional
Text: shifted out through a PISO shift register for transmission. At the receiver, the incoming data stream is , interleavers (block or convolutional) are popular techniques for protecting data from noise. Interleavers are , the transmitter (TX) and one de-interleaver in the receiver (RX). Consider a data stream, D_IN , are reserialized by a parallel-in, serial-out (PISO) register, and the serial output data flow, D_OUT , transmitter to reconstruct the data stream. In TX and RX circuits, a counter provides the correct timing and


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PDF XAPP222 DS022, DS003, DS001, XAPP210, XAPP130, 32-Bit Parallel-IN Serial-OUT Shift Register 32-Bit sipo Shift Register vhdl code for interleaver vhdl code for block interleaver vhdl code for sipo vhdl code for asynchronous piso 32-Bit Parallel-IN parallel-OUT Shift Register design for block interleaver deinterleaver SRL16 Convolutional
1998 - OPCODE SHEET FOR 8051 MICROCONTROLLER

Abstract: vhdl code for 16 BIT BINARY DIVIDER program for 8051 16bit square root IEEE754 testbench 4 bit binary multiplier Vhdl code single port ram testbench vhdl 8 BIT ALU design with vhdl code verilog code for four bit binary divider verilog code for TCON 8051 16bit division
Text: , data sheet, instruction set details Design File Formats EDIF netlist, ngo, VHDL , Verilog RTL source , memory. Extra DPP ( Data Page Pointer) register is used for the segments swapping. The DR8051 RISC , ) module includes the Serial Configuration register (SCON), the serial receiver, and the transmitter , write enable Internal data memory read User SFR write enable User SFR read Serial receiver output Serial transmitter output The DR8051 microcontroller has also been verified using a DCD testing board


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PDF DR8051 OPCODE SHEET FOR 8051 MICROCONTROLLER vhdl code for 16 BIT BINARY DIVIDER program for 8051 16bit square root IEEE754 testbench 4 bit binary multiplier Vhdl code single port ram testbench vhdl 8 BIT ALU design with vhdl code verilog code for four bit binary divider verilog code for TCON 8051 16bit division
2002 - vhdl code for rs232 receiver

Abstract: xilinx uart verilog code interface of rs232 to UART in VHDL vhdl code for uart communication vhdl code for serial transmitter vhdl code 16 bit microprocessor uart verilog code verilog code for serial transmitter verilog code for 8 bit shift register parallel to serial conversion vhdl
Text: This application note provides a functional description of VHDL and Verilog source code for a UART , Transmitter (UART) is the most widely used serial data communication circuit ever. UARTs allow full duplex communication over serial communication links as RS232. The reference VHDL and Verilog code implements a UART , on the receiver and then the transmitter . The frame format for data transmitted/received by a UART , discussed. To obtain the VHDL (or Verilog) source code described in this document, go to section VHDL (or


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PDF XAPP341 XC95144, XCR3128XL, XC2C128 RS232. XAPP341 XCR3128 XCR3128XL vhdl code for rs232 receiver xilinx uart verilog code interface of rs232 to UART in VHDL vhdl code for uart communication vhdl code for serial transmitter vhdl code 16 bit microprocessor uart verilog code verilog code for serial transmitter verilog code for 8 bit shift register parallel to serial conversion vhdl
2000 - vhdl code for rs232 receiver

Abstract: verilog code for uart communication vhdl code for uart communication xilinx uart verilog code uart verilog code verilog code for serial transmitter interface of rs232 to UART in VHDL 16 bit register vhdl vhdl code for serial transmitter UART using VHDL
Text: This application note provides a functional description of VHDL and Verilog source code for a UART , Transmitter (UART) is the most widely used serial data communication circuit ever. UARTs allow full duplex communication over serial communication links as RS232. The reference VHDL and Verilog code implements a UART , the receiver and then the transmitter . The frame format for data transmitted/received by a UART is , discussed. To obtain the VHDL (or Verilog) source code described in this document, go to section " VHDL (or


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PDF XAPP341 XC95144 XCR3128XL RS232. XAPP341 XCR3128 vhdl code for rs232 receiver verilog code for uart communication vhdl code for uart communication xilinx uart verilog code uart verilog code verilog code for serial transmitter interface of rs232 to UART in VHDL 16 bit register vhdl vhdl code for serial transmitter UART using VHDL
2000 - xilinx uart verilog code

Abstract: vhdl code for rs232 receiver vhdl code for uart communication vhdl code for shift register vhdl code for serial transmitter 16 bit register vhdl vhdl code for rs232 interface uart verilog code vhdl code for 8 bit shift register UART using VHDL
Text: This application note provides a functional description of VHDL and Verilog source code for a UART , Transmitter (UART) is the most widely used serial data communication circuit ever. UARTs allow full duplex communication over serial communication links as RS232. The reference VHDL and Verilog code implements a UART , the receiver and then the transmitter . The frame format for data transmitted/received by a UART is , ] Internal Receives data from tbr[7:0] and shifts to sdo clkdiv[3:0] VHDL (or Verilog) Code


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PDF XAPP341 XC95144 XCR3128 RS232. XAPP341 xilinx uart verilog code vhdl code for rs232 receiver vhdl code for uart communication vhdl code for shift register vhdl code for serial transmitter 16 bit register vhdl vhdl code for rs232 interface uart verilog code vhdl code for 8 bit shift register UART using VHDL
baud rate generator vhdl

Abstract: testbench of a transmitter in verilog C16550 buffer register vhdl 16 byte register VERILOG
Text: Support Support provided by CAST, Inc. Applications The C16550 core is used in serial data , Control Register INTERNAL DATA BUS MRESETn DIN[7:0] TXDATA MUX Transmitter FIFO , provides data formatting and control to a serial communication channel. This register provides , and receive serial data , supporting asynchronous operation. Interrupt Enable Register (IER) The , Different FIFOs size (separately for Transmitter and Receiver) · Removal of internal baud rate generator


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PDF C16550 6550A 16-byte baud rate generator vhdl testbench of a transmitter in verilog buffer register vhdl 16 byte register VERILOG
1999 - LIN Verilog source code

Abstract: LIN VHDL source code
Text: is a serial communication protocol designed primarity for use in automotive application. Compared to , their respective owners. Source code : VHDL Source Code VERILOG Source Code VHDL & VERILOG test , , store the divisor in the 15-bit binary format. Receiver Control & Shift Register ­ is responsible for , Design. All Rights Reserved. Provides necessery function for data reception, frame timming and error checking. Data Buffer ­ stores the receive or transmit data . Transmitter Control & Shift Register ­


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1996 - 8251 intel microcontroller architecture

Abstract: 8251 usart vhdl source code for 8086 microprocessor verilog coding for asynchronous decade counter verilog code for 8254 timer verilog code for median filter 8251 uart vhdl verilog code for iir filter SERVICE MANUAL oki 32 lcd tv VHDL CODE FOR HDLC controller
Text: asynchronous receiver/ transmitter Universal synchronous/asynchronous receiver/ transmitter Universal serial bus Universal test and operations physical layer interface for ATM data path interface Virtual , >.tdf), VHDL , Verilog HDL, or AHDL file Symbol File (.sym) for use in MAX+PLUS II , translates all PCI access information for the target device to a 486-style internal bus. Address and data , VHDL - or Verilog HDL-based design files that are optimized for the Altera FLEX 10K device family


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1998 - verilog code for 32 BIT ALU multiplication

Abstract: 8052 microcontroller architecture of 8052 vhdl source code for i2c memory read and write vhdl code for watchdog timer 32 BIT ALU design with vhdl code I2C master controller VHDL code
Text: data pointers (DPTR0 & DPTR1) for faster data transfers De-multiplexed Address/ Data Bus to allow easy , external data memory. Extra DPP ( Data Page Pointer) register is used for the segments swapping. It has the , Receiver & Transmitter (UART) module includes the Serial Configuration register (SCON0) and the serial , instructions. UART1 Universal Asynchronous Receiver & Transmitter module includes the Serial Configuration register (SCON1) and the serial receiver and transmitter buffer (SBUF1) registers. The module functions in


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PDF DR8052EX verilog code for 32 BIT ALU multiplication 8052 microcontroller architecture of 8052 vhdl source code for i2c memory read and write vhdl code for watchdog timer 32 BIT ALU design with vhdl code I2C master controller VHDL code
C16550

Abstract: XC4000XL buffer register vhdl
Text: · · · Applications The C16550 core is used in serial data communications and modem , communications interface (UART) megafunction provides data formatting and control to a serial communication , error checking, the megafunction can transmit and receive serial data , supporting asynchronous , priority) Priority 2 Receiver data ready or receiver character timeout Priority 3 Transmitter holding , Respective Manufacturer Input Different FIFOs size (separately for Transmitter and Receiver) Removal


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PDF c16550 6550A 16-byte XC4000XL buffer register vhdl
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