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LTC3444EDD#PBF Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD#TRPBF Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD#TR Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC6993CS6-3#TRMPBF Linear Technology LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: SOT; Pins: 6; Temperature Range: 0°C to 70°C
LTC6993HS6-4#TRMPBF Linear Technology LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: SOT; Pins: 6; Temperature Range: -40°C to 125°C

vhdl code for 16 prbs generator Datasheets Context Search

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simulation for prbs generator in matlab

Abstract:
Text: 16 -bit pseudo random binary sequence ( PRBS ) generator which is initialized at beginning of a Data Field. The PRBS polynomial generator is: G( 16 ) = X16 + X13 + X12 + X11 + X7 + X6 + X3 + X + 1. The sync byte of the incoming packet marks the beginning of Data Field, and the PRBS generator is loaded with , 2 for MW_ ATSC Modulator Core emission mask. Core Modifications Source code uses VHDL generics , , including the additional features for 16 -VSB. It accepts a single, SMPTE 310 or DVB-ASI, MPEG-2 formatted


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2009 - vhdl code for 8 bit barrel shifter

Abstract:
Text: specific PRBS pattern used in this application note for both the generator and the checker is based on the polynomial x15 + 1. The VHDL and Verilog code for both the generator and the checker can be found in the , binary sequence ( PRBS ) generator works at full speed on CLK_DT and can generate a PRBS 15 pattern. The , and works in parallel, while the PRBS generator is serial. The 10-bit output of the DRU is processed , Controllable via ChipScope Pro Analyzer Each of the four channels is equipped with: · A PRBS generator


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PDF XAPP875 vhdl code for 8 bit barrel shifter verilog code for barrel shifter vhdl code for 16 prbs generator vhdl code for 4 bit barrel shifter vhdl code for loop filter of digital PLL ML523 8 bit barrel shifter vhdl code vhdl code for phase frequency detector verilog code of parallel prbs pattern generator prbs pattern generator using vhdl
2009 - verilog code for barrel shifter

Abstract:
Text: the generator and the checker is based on the polynomial x15 + 1. The VHDL and Verilog code for both , CLK_DT PRBS Generator Ideal Deserializer HF_CLK (3.11 GHz) Simulation Only NI-DRU (Unit , pseudorandom binary sequence ( PRBS ) generator works at full speed on CLK_DT and can generate a PRBS 15 pattern , checker is synthesizable and works in parallel, while the PRBS generator is serial. The 10-bit output of , equipped with: · A PRBS generator continuously sending a PRBS 15 pattern. The user can force each of


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PDF XAPP875 verilog code for barrel shifter vhdl code for 8 bit barrel shifter vhdl code for 4 bit barrel shifter vhdl code Pseudorandom Streams Generator XAPP875 vhdl code for 16 prbs generator vhdl code for loop filter of digital PLL vhdl code for clock and data recovery prbs pattern generator using vhdl prbs generator using vhdl
vhdl code for ofdm

Abstract:
Text: for the pseudo random binary sequence ( PRBS ) generator is: 1 + x14 + x15. The sync byte of the first packet is bit-wise inverted from 47HEX to B8HEX, and the PRBS generator is loaded with the seed sequence "100101010000000". During the MPEG-2 sync bytes of the subsequent seven trasport packets the PRBS generator , for a range of puntured convolutional codes, based on a mother convolutional code of rate 1/2 with 64 , polynomials of the mother code are G1=171OCT for X output and G2=133 OCT for Y output. The two bit stream, X


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vhdl code for ofdm

Abstract:
Text: sequence ( PRBS ) generator is: 1 + x14 + x15. The sync byte of the first packet is bit-wise inverted from 47HEX to B8HEX, and the PRBS generator is loaded with the seed sequence "100101010000000". During the MPEG-2 sync bytes of the subsequent seven trasport packets the PRBS generator continues, but its , the mother code are G1=171OCT for X output and G2=133 OCT for Y output. The two bit stream, X and Y , specified by clause 4.3.5 of ETSI EN 300 744 V1.5.1 (2004-11) for QPSK, 16 -QAM or 64-QAM. It outputs I/Q


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2011 - vhdl code for 16 prbs generator

Abstract:
Text: , 2011 www.xilinx.com 6 Reference Design Table 4: Attribute Sets for PRBS Pattern Generator , Application Note: Xilinx FPGAs An Attribute-Programmable PRBS Generator and Checker XAPP884 , application note describes a PRBS generator /checker circuit where the generator polynomial, the parallelism , users who want to know how to use the PRBS generator and checker. The final section, PRBS Sequences , or checks it is indicated by the term LFSR. Table 1: PRBS Generator /Checker Attributes Attribute


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PDF XAPP884 vhdl code for 16 prbs generator verilog code of prbs pattern generator VHDL CODE FOR 16 bit LFSR in PRBS verilog code 16 bit LFSR in PRBS prbs generator using vhdl prbs pattern generator using vhdl XAPP884 verilog prbs generator prbs using lfsr DESIGN AND IMPLEMENTATION OF PRBS GENERATOR
2008 - vhdl code for loop filter of digital PLL

Abstract:
Text: Verilog Code Structure CDR Code (Verilog) ChipScope Pro Tool Project Files (Verilog) Testbenches for the CDR (Verilog) VHDL Code Structure CDR Code ( VHDL ) ChipScope Pro Tool Project Files ( VHDL ) Testbenches for the CDR ( VHDL ) X868_08_121707 Figure 8: Reference Design Analysis Directory Code , speedsel_0 DCO 0 prbs0 PRBS Generator 0 CDR 0 rec_clk2m0 (K18) dt_out0 (AF19) CDR 1 rec_clk2m1 (AH15) dt_out1 (AG15) Common REFCLK: CLK_N (J16)/CLK_P (J17) DCO 1 PRBS Generator 1


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PDF XAPP868 vhdl code for loop filter of digital PLL vhdl code for All Digital PLL vhdl code for phase frequency detector vhdl code for 16 prbs generator prbs generator using vhdl vhdl code for DCO E1 pdh vhdl vhdl code for loop filter of digital PLL spartan vhdl code for phase frequency detector for FPGA XAPP868
2001 - vhdl code for 16 prbs generator

Abstract:
Text: LCV LE LIU LOS M23 Mbps NRZ OOF PC PMON PRBS RDI RTL RX SONET SPE STS-1 TX VHDL , received as 16 -bit sequences, each consisting of eight 1's, a 0, six code bits, and a trailing 0. If a , Generator transmits codes to the C-bit parity FEAC channel via the TXFRMR. The idle code is used to disable , detection is software programmable. Software searches for the PRBS pattern from the in-coming payload bits , encoded dual data rail. The Midbus allows for connection to a SONET framer. A 16 -bit synchronous


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1998 - VHDL CODE FOR 16 bit LFSR in PRBS

Abstract:
Text: . The full VHDL source code for the PLDs in this application note is listed in Appendixes B and C. This , Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8-bit data , documented in this application note. Schematics and VHDL code are included in this document. Serial


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PDF 10-Bit 8B/10B 8B/10B. VHDL CODE FOR 16 bit LFSR in PRBS vhdl code for 8 bit barrel shifter vhdl code 8 bit LFSR vhdl code for 9 bit parity generator vhdl code for 8 bit parity generator vhdl code for 8 bit common bus vhdl code for 16 prbs generator prbs using lfsr vhdl code for pseudo random sequence generator in vhdl code to implement 8bit lfsr using maximum length sequence
1999 - vhdl code scrambler

Abstract:
Text: . The full VHDL source code for the PLDs in this application note is listed in Appendices B and C. This , Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8-bit data , documented in this application note. Schematics and VHDL code are included in this document. Serial


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PDF 10-Bit 8B/10B 8B/10B. vhdl code scrambler prbs generator using vhdl vhdl code for pseudo random sequence generator vhdl code for 7 bit pseudo random sequence generator vhdl code for 4 bit barrel shifter vhdl code for 16 bit Pseudorandom Streams Generation Using HOTLink vhdl code 8 bit LFSR vhdl code for nrz prbs pattern generator using vhdl
2002 - block diagram code hamming using vhdl

Abstract:
Text: "010101" configures the encoder for the (32,26) × ( 16 ,15) code . Table 3: Constituent Codes Supported by , example, with the (8,4) × (8,4) code , the user would provide valid data_in and assert data_en High for 16 , 802.16a standards · Optimized for Virtex®-II and Virtex-II Pro FPGAs, using structural VHDL and , process is illustrated in Figure 2 for an (8,4) × (8,4) product code , where the Dij represent input data , : Product Code Block for the (8,4)-by-(8,4) Case The core supports both extended Hamming and parity only


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PDF 16-Compatible DS211 block diagram code hamming using vhdl hamming test bench vhdl code hamming window vhdl code hamming hamming code FPGA vhdl code for 8 bit parity generator block diagram code hamming hamming code in vhdl vhdl code for 4 bit even parity generator TPC encoder design using xilinx
2009 - iodelay

Abstract:
Text: stay close to the half-full condition. As the FIFO empties, the flag for hitting 6/ 16 is asserted, and , The FIFO marks of 3/ 16 and 13/ 16 are used in case the frequency drifts and for ensuring that the , Jittered Clock DCM CLKIN CLKFX REFCLK BUFG MUX FILL-LEVEL PRBS Generator DCM FIFO , oscillator. A PRBS generator is driven by the multiplied CLKFX output and writes into a standard FIFO. The , from the FIFO is then checked by a PRBS checker with the same polynomial as the generator . Once both


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PDF XAPP872 iodelay vhdl code for 16 BIT BINARY DIVIDER vhdl code for frequency divider iodelay Virtex 5 prbs generator using vhdl vhdl code for FFT 32 point vhdl code for 16 prbs generator knx usb ML505 XAPP872
1998 - vhdl HDB3

Abstract:
Text: FPGA provides a PRBS generator , loopback capabilities, logic for alarm LEDs, and several timing , 3.9.5 VHDL CODE . 26 3.10 ALARMS , Display is controlled by the microprocessor. The ACTEL A1460A FPGA provides a PRBS data generator , 00H Select B8ZS line code for receiver Write XBAS Configuration Register 44H 3XH Select B8ZS, enable for ESF in transmitter (bits defined by `X' determine the FDL data rate & Zero Code


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PDF PM4344 TQUAD/PM6344 PMC-980328 PM4344/PM6344 PMC-951013 vhdl HDB3 PQFP208 footprint alarm clock design of digital VHDL digital alarm clock vhdl code 74XXX139 vhdl code for 16 bit Pseudorandom Streams Generation MLL41 vhdl code Pseudorandom Streams Generator 74hc04bl vhdl code for 16 prbs generator
2010 - verilog code of parallel prbs pattern generator

Abstract:
Text: . The code you can reuse in the reference design is the PRBS generator , PRBS checker, and, most , , pseudo-random binary sequence ( PRBS ) generator and checker, and a frequency checker. All the necessary design , TX PRBS Generator ANY PHY IP Block PRBS Checker RX Avalon Master PRBS Generator and Checker A 64-bit PRB23 data generator and check modules are used for loopback testing. Top-Level , (DUT) is the PHY IP. A clock generator was created in the testbench for the PHY IP’s clock


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PDF AN-634-1 verilog code of parallel prbs pattern generator
1999 - verilog hdl code for encoder

Abstract:
Text: binary sequence ( PRBS ) generator whose output is XORed with the clear data stream on the transmitter side , packets remain 0x47. During the inverted sync byte interval (SYNC 1), the PRBS generator is loaded with a seed value of "100101010000000". After the seed is loaded, the PRBS generator runs continuously through , . Randomizer Disable Control: When asserted high, the output of the PRBS generator is not XORed with the data , packet, and low for 16 bytes. The Outer Coder block uses it to qualify on which clock cycles input data


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2000 - vhdl code for 16 prbs generator

Abstract:
Text: randomizer is a pseudo random binary sequence ( PRBS ) generator whose output is XORed with the clear data , generator is loaded with a seed value of "100101010000000". After the seed is loaded, the PRBS generator , . Randomizer Disable Control: When asserted high, the output of the PRBS generator is not XORed with the data , . In DVB, this signal is high for the first 188 bytes of the packet, and low for 16 bytes. The Outer , Experience For the source code version, users should be familiar with Verilog HDL entry, synthesis


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2003 - FSP250-60GTA

Abstract:
Text: placing orders for products or services. Printed on recycled paper ii Altera Corporation , information. For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to www.altera.com/mysupport. For , exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also , the revision history for Chapter 1. Chapter(s) Date / Version 1 Altera Corporation July 2003


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PDF P25-09565-00 D-85757 10-Gigabit FSP250-60GTA fsp250-60gta power supply schematic power supply fsp250-60gta fsp250-60 FSP250 manual FSP250-60gta manual vhdl code for 16 prbs generator FSP250 fsp250-60gt SMC91C11xFD
2001 - free verilog code of prbs pattern generator

Abstract:
Text: LCV LE LIU LOS M23 Mbps NRZ OOF PC PMON PRBS RDI RTL RX SONET SPE STS-1 TX VHDL , programmable. Software searches for the PRBS pattern from the in-coming unframed bit stream. When the number , Midbus allows for connection to a SONET framer. A 16 -bit synchronous microprocessor interface (AIRbus , Input Line code violation for single rail signal Receive T3 Mapper Interface Signals rxsclk , placing orders for products or services. All rights reserved. ii Altera Corporation About this


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1991 - digital FIR Filter verilog HDL code

Abstract:
Text: Instantiation Template for an 8-Bit Adder . 4-12 Using the CORE Generator VHDL Design Flow , ,"Getting Started"-Provides information for setting up your environment and installing the CORE Generator , resources for using the CORE Generator System. · · · · · CORE Generator Guide - 3.1i v CORE Generator Guide Additional Resources For additional information, go to http , 3.1i vii CORE Generator Guide See the Development System Reference Guide for more information


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PDF XC2064, XC3090, XC4005, XC5210, XC-DS501 digital FIR Filter verilog HDL code generator pdt 908 vhdl code direct digital synthesizer vhdl code for character display
2001 - xilinx vhdl code

Abstract:
Text: , page 19 for instructions. When using a Xilinx CORE Generator macro in the VHDL design, there are , Simulating a Xilinx 3.1i CORE Generator VHDL Design This section describes the input/output files for a , in the CORE Generator tree. XilinxCoreLib/*_comp.vhd VHDL component declaration files for each CORE , to compile the CORE Generator libraries. 1. Creating the library named "xilinxcorelib". For VHDL , www.xilinx.com 1-800-255-7778 11 R Simulating a Xilinx 3.1i CORE Generator VHDL Design end for


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PDF XAPP409 com/pub/applications/xapp/XAPP409 xilinx vhdl code single port ram testbench vhdl Using Hierarchy in VHDL Design EE core testbench vhdl ram 16 x 4 vhdl code for 1 bit error generator vhdl coding XAPP409 xilinx vhdl
2005 - RAM32X2S

Abstract:
Text: defines all the other control parameters for the CORE Generator system. memory_initialization_radix= 16 , Verilog Codes Distributed RAM structures can be initialized in VHDL or Verilog code for both synthesis , read function. Each 16 x 1-bit RAM is cascadable for deeper and/or wider memory applications, with a , distributed RAMs for the Spartan-3 architecture. Similarly, CORE Generator creates Asynchronous and , , including the Xilinx CORE Generator software or VHDL or Verilog. Xilinx CORE Generator System The Xilinx


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PDF XAPP464 com/bvdocs/publications/ds099-2 RAM32X2S RAM64X1S XAPP464 vhdl code for 8 bit ram "Single-Port RAM" RAM16X1D RAMX Spartan 3E VHDL code SRL16
2011 - XC7VH580T-HCG1155-2

Abstract:
Text: generator . Transmit differential pairs for each of the n GTZ transceivers used. Receive differential pairs , v LogiCORE IP ChipScope Pro IBERT for 7 Series GTZ Transceivers (v2.0) DS878 December 18, 2012 , ChipScope™ Pro Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTZ transceivers is designed for evaluating and monitoring the GTZ transceivers. This core includes pattern generators and , User Guide Documentation Design Files Vivado™: RTL Example Design Verilog/ VHDL Test


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PDF DS878 XC7VH580T-HCG1155-2
1998 - vhdl code for 4 bit even parity generator

Abstract:
Text: The LTC Bit Stream Generator retrieves 5 x 16 time code data bits from the register bank which are , Longitudinal Time Code Generator September 25, 2000 Product Specification AllianceCORETM , under terms of the SignOnce IP License SMPTE/EBU Longitudinal Time Code time code generator Lock on external (video) reference PAL/NTSC support 27 Mhz clock input for internal timing Five 16 -bit double buffered registers for time code data and sync word Versatile synchronization Core Specifics See


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PDF B-4430 16-bit 12M-1995 vhdl code for 4 bit even parity generator vhdl code for 9 bit parity generator vhdl code for frame synchronization biphase mark encoder biphase mark vhdl vhdl code for 8 bit parity generator vhdl code for 8 bit ODD parity generator vhdl 8 bit parity generator code address generator logic vhdl code audio file in vhdl code
1999 - electronic power generator using transistor

Abstract:
Text: ( VHDL Instantiation Template) . 4-12 Sample .VHO file for an , CORE Generator VHDL Flow .4-28 Synthesis , manual describes the Xilinx CORE Generator System, a tool used for parameterizing cores optimized for , the Development System Reference Guide for more information. CORE Generator 2.1i User Guide ix , CORE Generator System can generate for the designer. COREs are organized by type into folders that


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PDF XC2064, XC3090, XC4005, XC-DS501, electronic power generator using transistor Behavioral verilog model new ieee programs in vhdl and verilog ieee vhdl projects free how example make fir filter in spartan 3 vhdl XC4005 spartan 3 fir filter synopsys Platform Architect DataSheet virtex user guide 1999 XC2064
1999 - electronic power generator using transistor

Abstract:
Text: ( VHDL Instantiation Template) . 4-12 Sample .VHO file for an , 4-16 Preparing for Verilog Behavioral Simulation . 4-16 CORE Generator , CORE Generator VHDL Flow .4-28 Synthesis , . Prepare for Simulation . 4-30 VHDL Model , manual describes the Xilinx CORE Generator System, a tool used for parameterizing cores optimized for


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PDF XC2064, XC3090, XC4005, XC-DS501, electronic power generator using transistor how example make fir filter in spartan 3 vhdl XC4000 XC3090 XC2064 virtex user guide 1999 verilog code for fir filter new ieee programs in vhdl and verilog MODELS 248, 249 XC4005
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