The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LM119J/883 Linear Technology IC COMPARATOR, Comparator
LT1017CJ8 Linear Technology IC MICRPWR COMPARATOR DUAL 8CDIP
LT685MJ883 Linear Technology IC COMPARATOR, 3000 uV OFFSET-MAX, CDIP16, 0.300 INCH, HERMETIC SEALED, CERDIP-16, Comparator
RH1011J8 Linear Technology IC COMPARATOR, 3000 uV OFFSET-MAX, CDIP8, CERAMIC, DIP-8, Comparator
LTC1540CIMS8#PBF Linear Technology IC COMPARATOR, 16000 uV OFFSET-MAX, 70000 ns RESPONSE TIME, PDSO8, PLASTIC, MSOP-8, Comparator
LTC1531CSW Linear Technology IC COMPARATOR, PDSO28, 0.300 INCH, PLASTIC, SOP-28, Comparator

verilog module of byte comparator Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1997 - 16 byte register VERILOG

Abstract: vhdl codings for fast page mode dram controller pci master verilog code AN21BUF2 QL2009 AN21 80C300 vhdl code dma controller verilog code of 8 bit comparator design of dma controller using vhdl
Text: /receive capability · 32- byte burst size for efficient use of 80C300 internal FIFO · Automatic , shown in Figure 10. Details of the DMA register implementation may be found in the Verilog source file , TARTO is a Verilog module that checks for the Master Abort condition. DevSelTO is asserted if DEVSEL , and pinout capabilities of the QL2009 device are key to providing the necessary interface , accommodate the stringent system timing requirements of the 33 MHz PCI bus. All required PCI Configuration


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PDF QAN15 QL2009 80C300 16 byte register VERILOG vhdl codings for fast page mode dram controller pci master verilog code AN21BUF2 AN21 vhdl code dma controller verilog code of 8 bit comparator design of dma controller using vhdl
1996 - verilog code of 8 bit comparator

Abstract: vhdl code for 4 channel dma controller pci master verilog code pin vga CRT pinout pci schematics 80C300 digital clock verilog code design of dma controller using vhdl 8 shift register by using D flip-flop 16 byte register VERILOG
Text: registers · Simultaneous transmit/receive capability · 32- byte burst size for efficient use of , Verilog source code. Figure 4 indicates the external signals of the FPGA, connecting to the PCI Bus and , synthesized from Verilog . Also on this page are the Target Time-out module (TARTO) and Latency Counter , Notes TARTO is a Verilog module that checks for the Master Abort condition. DevSelTO is asserted if , logic and pinout capabilities of the QL24x32B device are key to providing the necessary interface


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PDF QAN15 QL24x32B t0C300 verilog code of 8 bit comparator vhdl code for 4 channel dma controller pci master verilog code pin vga CRT pinout pci schematics 80C300 digital clock verilog code design of dma controller using vhdl 8 shift register by using D flip-flop 16 byte register VERILOG
2007 - verilog code for 4-bit alu with test bench

Abstract: No abstract text available
Text: to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of , result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress , System-on-ChipTM, and WarpTM are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Any Source Code (software and/or


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2003 - FSP250-60GTA

Abstract: fsp250-60gta power supply schematic power supply fsp250-60gta fsp250-60 FSP250 manual FSP250-60gta manual vhdl code for 16 prbs generator FSP250 fsp250-60gt SMC91C11xFD
Text: trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their , applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to , liability arising out of the application or use of any information, product, or service described herein , the latest version of device specifications before relying on any published information and before


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PDF P25-09565-00 D-85757 10-Gigabit FSP250-60GTA fsp250-60gta power supply schematic power supply fsp250-60gta fsp250-60 FSP250 manual FSP250-60gta manual vhdl code for 16 prbs generator FSP250 fsp250-60gt SMC91C11xFD
2009 - full adder circuit using nor gates

Abstract: free transistor equivalent book Verilog code for 2s complement of a number verilog code for four bit binary divider 16 bit carry select adder verilog code hex to 7 segment decoder BASYS+3
Text: mux24b defined by the Verilog program in Listing 6.3 could be used in place of the mux24 module in the , Digilent FPGA Boards ─ Block Diagram / Verilog Examples Table of Contents Introduction – Digital , ) to design digital systems. The most widely used HDLs are VHDL and Verilog . Both of these hardware , top-level designs. Sometimes it will be easier to design a digital module by writing a Verilog program , module in higher-level designs. We will illustrate this process in many of our examples. Just like any


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DataFlash

Abstract: AT26DFXXX AT25DF041A AT26DF321 AT26DF161A AT25DF041A application AT26DF081A BE32 top26x
Text: erase received Opcode(02) Byte Program received Page 4 of 17 Atmel Corporation ­ DataFlash Verilog , 17 Atmel Corporation ­ DataFlash Verilog Model 02/05/2007 4. Signals and Events of AT26DFxxx.v module : AT26DFxxx model will receive opcode, data from the SI line. Some of the tasks in this , intimates start of Sequential Byte Programming. current_address signal stores the 24 bit address. data_in , Page 2 of 17 Atmel Corporation ­ DataFlash Verilog Model 02/05/2007 WEL signal holds the


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PDF AT26DFxxx AT25DF041A, AT26DF081A, AT26DF161A, AT26DF321. AT26DFx at26x AT26DF321 DataFlash AT25DF041A AT26DF161A AT25DF041A application AT26DF081A BE32 top26x
1998 - verilog code for adc

Abstract: verilog code of 8 bit comparator ADC Verilog Implementation ADC DAC Verilog 2 bit Implementation verilog code of 16 bit comparator adc verilog analog to digital converter verilog verilog code of 4 bit comparator verilog code of 3 bit comparator verilog code for serial multiplier
Text: ADC output register. Virtex FPGA Vcco Comparator Verilog adc module DACout RP OBUF_F , signal feeds the positive input of the comparator (see Figure 1). The voltage range of the DAC output is , set, which drives the reference voltage to midrange. Depending on the output of the comparator , the , circuit. AgtR Input Analog greater than Reference. This is the output of external comparator , /second ShiftIn Shift Shift DAC The ADC can be implemented in a single Verilog module that


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PDF XAPP155 10-bit CLK90( CLK180( CLK270( verilog code for adc verilog code of 8 bit comparator ADC Verilog Implementation ADC DAC Verilog 2 bit Implementation verilog code of 16 bit comparator adc verilog analog to digital converter verilog verilog code of 4 bit comparator verilog code of 3 bit comparator verilog code for serial multiplier
1996 - dram verilog model

Abstract: MC68HC11RM F645D verilog code to generate square wave MPA1000 Verilog code of state machine for 16-byte SRAM 7908 motorola pal spi verilog code 16 bit CISC CPU motorola bubble memory controller
Text: synthesis, place and route, and Verilog post simulation. of the top glue68k module , designated with the , of the stimulus module and the waveform capabilities of the Verilog simulator. Once the design was , generation of the Verilog RTL source code. The DRAM design used a hierarchical module development , diagram of the Verilog stimulus module used for logic simulation and includes the 25MHz clock module for , following is a subset of Verilog simulation module stimulus.v, that was used for the test bench and


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PDF 68ock, MPA1000 DL201 dram verilog model MC68HC11RM F645D verilog code to generate square wave Verilog code of state machine for 16-byte SRAM 7908 motorola pal spi verilog code 16 bit CISC CPU motorola bubble memory controller
1998 - DW01 pinout

Abstract: vhdl code for full subtractor full subtractor implementation using 4*1 multiplexer 16 bit carry select adder verilog code
Text: List of Figures Comparator Logic Levels . Counter Module Count . . Counter Logic Levels . . . , trademarks of Synopsys, Inc. UNIX is a registered trademark of X/Open Company Limited. Verilog is a registered trademark of Open Verilog International. Viewlogic is a registered trademark and MOTIVE is a , . . . . . Comparator Module Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . Multiplexer Diagram Verilog module mux4_1 (c, d, e, f, s, mux_out); input c, d, e, f; input [1:0] s


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2001 - verilog code for Modified Booth algorithm

Abstract: 8 bit booth multiplier vhdl code Booth algorithm using verilog booth multiplier code in vhdl structural vhdl code for ripple counter vhdl code for Booth multiplier 8 bit carry select adder verilog code verilog code for 16 bit carry select adder
Text: trademarks of Synopsys, Inc. UNIX is a registered trademark of X/Open Company Limited. Verilog is a registered trademark of Open Verilog International. Viewlogic is a registered trademark and MOTIVE is a , Comparator Module Count . . . . . . . . . . . . Comparator Logic Levels . . . . . . . . . . . . . Area and , . Multiplexer Diagram Verilog module mux4_1 (c, d, e, f, s, mux_out); input c, d, e, f; input [1:0] s; output , multiplexer. Verilog module mux11 (s, a, b, c, d, e, f, g, h, i, j, k, mux_out); input [3:0] s; input a, b, c


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1998 - vhdl coding for pipeline

Abstract: verilog code of 2 bit comparator verilog code for 4 bit ripple COUNTER RAM32X32 structural vhdl code for ripple counter
Text: .109 .109 .110 vii List of Figures Comparator Logic Levels . . . . . . . Area and Module , trademarks of Synopsys, Inc. UNIX is a registered trademark of X/Open Company Limited. Verilog is a registered trademark of Open Verilog International. Viewlogic is a registered trademark and MOTIVE is a , /54SXA Subtractor Logic Level . . . . . . . . . . Comparator Module Count . . . . . . . . . . . . . . . . , . Multiplexer Diagram Verilog module mux4_1 (c, d, e, f, s, mux_out); input c, d, e, f; input [1:0] s


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1995 - verilog code of 8 bit comparator

Abstract: verilog code of 16 bit comparator verilog code of 2 bit comparator verilog code for timer HP700 verilog code finite state machine uPD 1719 G
Text: The following is an example of I/O buffer instantiation in Verilog : module top(clear,clock,enable , contains practical Verilog HDL applications to provide you with a solid understanding of techniques , switches: Minus Switches Table 2-1 indicates the names and definitions of Verilog minus switches , and definitions of Verilog plus switches: Table 2-2. Plus Switches Name Definition +libext+ , . //Instantiate the top module of your design in the test module


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PDF 1995Actel verilog code of 8 bit comparator verilog code of 16 bit comparator verilog code of 2 bit comparator verilog code for timer HP700 verilog code finite state machine uPD 1719 G
2001 - sample verilog code for memory read

Abstract: verilog code arm processor NetportExpress verilog code for bfm ARM verilog code COYB Pentium II Xeon 20/ZYNQ-7000 BFM
Text: ® 80200 Verilog Bus Functional Model (BFM) What is Provided 3.0 What is Provided The BFM module , named coybfm, has ports that match the inputs and outputs of the actual 80200 component. This module , important for byte writes, where the position of the valid byte within the word depends on the two LSBs of , gets whatever is on the bus - the byte position within the word depends on the two LSBs of the address. In the case of a 32- byte read, w0-w7 are filled in line-fill order. When the bottom eight bits


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2010 - verilog code for correlator

Abstract: vhdl code for complex multiplication and addition vhdl code for accumulator vhdl code CRC vhdl code of carry save multiplier vhdl code for lvds driver verilog code for implementation of rom vhdl code for multiplexer 32 BIT BINARY vhdl code for sr flipflop advanced synthesis cookbook
Text: Template-Sample Verilog HDL instantiation of the module in the megafunction wrapper file. of the Verilog HDL and VHDL examples in this document correspond with , . Verilog HDL module declaration file that can be used when instantiating the megafunction as a black box , instantiation of the subdesign in the megafunction wrapper file. _bb.v Black box Verilog HDL Module Declaration-Hollow-body module declaration that can be used in Verilog HDL designs to specify


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PDF QII51007-10 verilog code for correlator vhdl code for complex multiplication and addition vhdl code for accumulator vhdl code CRC vhdl code of carry save multiplier vhdl code for lvds driver verilog code for implementation of rom vhdl code for multiplexer 32 BIT BINARY vhdl code for sr flipflop advanced synthesis cookbook
2001 - testbench vhdl ram 16 x 4

Abstract: ram memory testbench vhdl code testbench verilog ram 16 x 4 ram memory testbench vhdl sample vhdl code for memory write mem_rd_ altera pci pci verilog code PCI32 MEMWR64
Text: Verilog HDL application design. Figure 1 shows the block diagram of Altera PCI testbench. Refer to the , . source Contains Verilog HDL source files of the testbench modules and reference designs for Altera PCI , section of the VHDL behavioral model wrapper file or parameter section of the Verilog HDL behavioral , . Figure 5 shows the USER COMMANDS section of the master transactor model source code in VHDL and Verilog , address_lines and mem_hit_range parameters of the target transactor model source code in VHDL and Verilog HDL


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1994 - 5AC312

Abstract: LIN VHDL source code vhdl code for carry select adder 8 bit carry select adder verilog codes 3 bit carry select adder verilog codes carry save adder verilog program verilog code for fixed point adder PQFP132 PLCC84 PLCC28
Text: . Avoid using an interface statement on the module declaration line of lower-level ABEL-HDL modules that , ABEL-HDL module due to re-ordering of pin names in the schematic netlister. Accessing FLEXlogic , simulate your design functionally using a Verilog or a VHDL model of your design. The Equation simulator , with either the device or a module in your design. You can write Verilog test fixtures for schematic , features of the FLEXlogic FPGA architectures. These features include the SRAM and Hardware Comparator


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1998 - DW01A

Abstract: DW01 FFF10000 MXT3010 MXT3010EP-A ess11 F29E gdr5 rsa Verilog
Text: . //////////////////////////////////////////////////////////////// 34. // Lump a Small Amount of Delay on the Outputs of this Module 35 , independently and not within the context of the Verilog code above. The resulting gate level circuit matched the , ; ////////////////////////////////////////////////////////////////////////////// ; // Subroutine: P1_GET_HALFWORD ; // ; // Issues a pair of Byte DMA Read[s], increments the source and , ; ////////////////////////////////////////////////////////////////////////////// ; // Subroutine: P2_GET_HALFWORD ; // ; // Issues a pair of Byte DMA Read[s], increments the source and , of the comparator that was designed for the MXT3010B/C, which did not correctly model the signed


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PDF MXT3010EP-A AS3010 MXT3010EP MXT3010EP-A DW01A DW01 FFF10000 MXT3010 ess11 F29E gdr5 rsa Verilog
1995 - HP700

Abstract: verilog code for 8 bit carry look ahead adder carry save adder verilog program catalogue book
Text: Inference Flip-Flop Inference The sequential module in the Actel architecture consists of a , of a flip-flop with synchronous enable. Figure 3-8 illustrates this example: module mux_ff (clk, d , of America Part Number: 5029076-0 Release: October 1995 No part of this document may be copied or reproduced in any form or by any means without prior written consent of Actel Corporation. Actel makes no warranties with respect to this documentation and disclaims any implied warranties of merchantability or


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1999 - vhdl code for 4 channel dma controller

Abstract: verilog code of 8 bit comparator vhdl code dma controller latgn pci to pci bridge verilog code verilog code 8 bit LFSR asynchronous fifo vhdl vhdl code for DMA design of dma controller using vhdl dell core i3
Text: schematic that represents your Verilog or VHDL file(s). Of course, you may also use a Verilog or VHDL file , . Step-by-step Project Setup Regardless of whether you intend on designing with schematics, VHDL, Verilog , or , appropriate section of the Verilog (.V) file is shown here. // * beginning of user-modifiable , . From the Turbo Writer menu, click on File > Open. Then choose VHDL or VERILOG from the `List Files of , designing your top-level block in Verilog or VHDL, you will be using a .SC file to specify the pinout of


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PDF QL5032 1152-bits vhdl code for 4 channel dma controller verilog code of 8 bit comparator vhdl code dma controller latgn pci to pci bridge verilog code verilog code 8 bit LFSR asynchronous fifo vhdl vhdl code for DMA design of dma controller using vhdl dell core i3
2010 - decoder.vhd

Abstract: LC4256ZE MC68340 vhdl code for 8-bit parity generator 180lt128 RAS20 4 bit microprocessor using vhdl
Text: the upper column address on the DRAM address lines to select the upper byte of the 16-bit data lines , column address on the DRAM address lines to select the lower byte of the 16-bit data lines on the DRAM , data on the upper 8-bit data bus. The lower byte on the data bus will be ignored. In case of Odd , is implemented in Verilog and VHDL. When using this design with another version of software or , within the page can then be made without the time penalty of additional precharge cycles. Although it


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PDF RD1014 MC68340, 1-800-LATTICE decoder.vhd LC4256ZE MC68340 vhdl code for 8-bit parity generator 180lt128 RAS20 4 bit microprocessor using vhdl
1998 - verilog code for MII phy interface

Abstract: MII PHY verilog code for phy interface crc verilog code 16 bit ethernet mac verilog testbench vhdl code for phy interface 2V500FG456-4
Text: multiple licensees' products Verilog RTL source code available Applications The PE-MACMII module is a , Description The PE-MACMII module consists of five sub-blocks. These sub-blocks are the transmit and receive , Input Transmit Packet Start-of-Frame. Marks the first byte of transmit frame on TPD[7:0] TPEF Input , ; Marks the first byte of a receive frame on RPD[7:0] RPEF Output Receive Packet End-of-Frame; Marks the last byte of a receive frame on RPD[7:0] PCRF Output Pass Current Receive Frame; Indicates


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PDF 10Base-T 100Base-TX 100Base-FX 100Base-T4 16-bit verilog code for MII phy interface MII PHY verilog code for phy interface crc verilog code 16 bit ethernet mac verilog testbench vhdl code for phy interface 2V500FG456-4
2003 - XAPP463

Abstract: written RAMB16 vhdl code for bcd to seven segment display XC3S500E Seven Segment LED Display vhdl code for 4 bit even parity generator XC3S200 INIT01 Application Circuit xc3s200 XC3S50
Text: has a number of attributes that control its behavior as shown in Table 5 for VHDL and Verilog . The , describes the features and capabilities of block SelectRAM and illustrates how to specify the various options using the Xilinx CORE GeneratorTM system or via VHDL or Verilog instantiation. Various , -3E devices, feature multiple block RAM memories, organized in columns. The total amount of block RAM memory depends on the size of the Spartan-3 Generation FPGA. Table 1 shows the available block RAM for Spartan


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PDF XAPP463 256x72 XC3S1000L, XC3S1500L, XC3S4000L) XC3S100E, XC3S250E, XC3S500E, XC3S1200E, XC3S1600E) XAPP463 written RAMB16 vhdl code for bcd to seven segment display XC3S500E Seven Segment LED Display vhdl code for 4 bit even parity generator XC3S200 INIT01 Application Circuit xc3s200 XC3S50
1991 - verilog hdl code for parity generator

Abstract: verilog code for half adder using behavioral modeling verilog code mealy for vending machine drinks vending machine circuit vending machine hdl SR flip flop using discrete gates verilog disadvantages vending machine xilinx schematic verilog hdl code for encoder system verilog
Text: principal design entity in the Verilog language is a module . A module consists of the module name, its , of a module are illustrated in the following figure. Verilog Reference Guide 3-1 Verilog , efficient implementation. · Chapter 9, " Verilog Syntax," contains syntax descriptions of the Verilog , Figure 1-1 Foundation Express Design Process Foundation Express supports a majority of the Verilog constructs. For exceptions, see the "Unsupported Verilog Language Constructs" section of the " Verilog


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PDF XC2064, XC3090, XC4005, XC5210, XC-DS501 verilog hdl code for parity generator verilog code for half adder using behavioral modeling verilog code mealy for vending machine drinks vending machine circuit vending machine hdl SR flip flop using discrete gates verilog disadvantages vending machine xilinx schematic verilog hdl code for encoder system verilog
2000 - verilog code of 4 bit magnitude comparator

Abstract: verilog code of 8 bit comparator Verilog code for 2s complement of a number Verilog code subtractor 8 bit full adder VHDL verilog code for half subtractor vhdl code for 8-bit signed adder verilog code of 16 bit comparator 32 bit carry adder vhdl code 8bit comparator vhdl code
Text: example is of a signed magnitude comparator module mag_comp_sign (a, b, a_gtet_b); input [7:0]a; input , discusses the optimum implementation for coding the arithmetic functions of a fullfeatured arithmetic module , ease. The two languages differ in signed arithmetic support. In the case of synthesizable Verilog , differently. In Verilog , only values of XAPP215 (v1.0) June 28, 2000 www.xilinx.com 1-800-255-7778 5 , incorrect. The designer must manually handle the exceptions of dealing with signed numbers in verilog


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PDF XAPP215 verilog code of 4 bit magnitude comparator verilog code of 8 bit comparator Verilog code for 2s complement of a number Verilog code subtractor 8 bit full adder VHDL verilog code for half subtractor vhdl code for 8-bit signed adder verilog code of 16 bit comparator 32 bit carry adder vhdl code 8bit comparator vhdl code
2000 - 9536XL

Abstract: verilog code for johnson decoder verilog code for johnson counter encoder8*3 verilog hdl code for multiplexer 4 to 1 verilog code for 4 bit ripple COUNTER vhdl code for 4 bit ripple COUNTER verilog code for four bit binary divider verilog code of 4 bit comparator verilog code for multiplexer 16 to 1
Text: Summary This Application Note covers the basics of how to use Verilog as applied to Complex , of code. Four Bit address Decoder module adddec (Address, AddDec_0to3, AddDec_4to7, AddDec , if( (A = B) && (A = C) ). // 6 Bit Equality Comparator module comparator (A1,B1,A2,B2,A3,B3, Y1 , makes use of parameter. Parameters are constants allowing a module to be customized at compile time , decoded in the next state logic, whether they form part of the state machine or not. In Verilog a


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PDF XAPP143 9536XL verilog code for johnson decoder verilog code for johnson counter encoder8*3 verilog hdl code for multiplexer 4 to 1 verilog code for 4 bit ripple COUNTER vhdl code for 4 bit ripple COUNTER verilog code for four bit binary divider verilog code of 4 bit comparator verilog code for multiplexer 16 to 1
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