The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC3444EDD#TRPBF Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD#PBF Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD#TR Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC2851CMS#TRPBF Linear Technology IC LINE TRANSCEIVER, PDSO8, LEAD FREE, PLASTIC, MSOP-8, Line Driver or Receiver
LTC1064-7MJ#TR Linear Technology IC SWITCHED CAPACITOR FILTER, BESSEL, LOWPASS, CDIP14, LEAD FREE, CERDIP-14, Active Filter

verilog code for scale free cordic Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2005 - verilog code for cordic algorithm

Abstract: verilog code for cordic cordic algorithm code in verilog cordic cordic algorithm in matlab code for cordic cordic design for fixed angle rotation AN 263 CORDIC Reference Design altera CORDIC ip cordic design for fixed angle of rotation
Text: Verilog HDL source code , precompiled simulation files for the ModelSim simulator, and a testbench for , compensate for the processing gain. However, Altera supply source code for a gain compensation block with the encrypted source code for the CORDIC reference design,. This block is synthesizable and is , of up to 32 bits for x, y and z. Iterations The accuracy of the CORDIC algorithm improves with , files and Verilog HDL parameters to configure the hardware CORDIC , gain compensation blocks, and


Original
PDF
2006 - verilog code to generate sine wave

Abstract: verilog code for sine wave generator using cordic vhdl code to generate sine wave CORDIC to generate sine wave fpga verilog code for CORDIC to generate sine wave vhdl code dds VHDL code for CORDIC to generate sine wave vhdl code for cordic algorithm vhdl code for cordic CORDIC to generate sine wave
Text: / RTAX (ax). lang verilog or vhdl Identifies hardware description language for the RTL code and , the CORDIC iteration, the x and y coordinates for a given angle represent the cosine and sine of that angle, respectively. See the CoreCORDIC CORDIC RTL Generator datasheet for more information. Figure , bit resolution at the phase quantizer output, the CORDIC DDS architecture is virtually free of this , (F:\Actelprj, for example), and an HDL type ( Verilog or VHDL). · Select the targeted FPGA family


Original
PDF
1999 - vhdl code for cordic algorithm

Abstract: vhdl code for cordic verilog code for cordic algorithm vhdl code for modulation vhdl code for complex multiplication and addition verilog code for cordic vhdl code for rotation cordic vhdl code for digital clock digital clock vhdl code cordic algorithm code in verilog
Text: automatically convert the fixed-point CORDIC algorithm to Verilog or VHDL. For the evaluation, a number of , available for code development, compilation, and debugging. In addition, the simulation speed using C or C , . What WYWIWYG really means is that if you code in behavioral C, the output VHDL or Verilog will be behavioral. If you code in RTL C, you get RTL VHDL or Verilog . It is a supported subset of C that is , simulate in C, you write a behavioral model in C for the CORE Generator module. The behavioral code


Original
PDF
2003 - verilog code for cordic algorithm

Abstract: cordic algorithm code in verilog FIR filter design using cordic algorithm CORDIC adaptive algorithm dpd verilog code for dpd verilog code for cordic altera CORDIC ip verilog code for cordic algorithm for wireless matlab code for half adder
Text: simulation Verilog HDL source code for Nios processor, co-ordinate rotation digital computer ( CORDIC , HDL solution. Altera supplies the reference design as Verilog HDL source code . The reference design , The reference design implements an Altera CORDIC reference design, for the cartesian-to-polar and , For the cycle to work, an input signal is fed into the CORDIC block to signify the start of a CORDIC , ensures that the INVALID_FLAG is always read for all but the first WINDOW_VALID cycles of a CORDIC frame


Original
PDF AN-314-1 verilog code for cordic algorithm cordic algorithm code in verilog FIR filter design using cordic algorithm CORDIC adaptive algorithm dpd verilog code for dpd verilog code for cordic altera CORDIC ip verilog code for cordic algorithm for wireless matlab code for half adder
2002 - fsk by simulink matlab

Abstract: VHDL code for CORDIC to generate sine wave VERILOG Digitally Controlled Oscillator vhdl code for cordic algorithm verilog code for cordic algorithm vhdl code to generate sine wave matlab code to generate sine wave using CORDIC verilog code for CORDIC to generate sine wave vhdl code for cordic matlab code for CORDIC to generate sine wave
Text: Evaluation The OpenCore feature lets you test-drive Altera MegaCore functions for free using the Quartus II , the core for free using the OpenCore or OpenCore Plus feature. Refer to AN 176: OpenCore Plus , . matlab Contains the MATLAB libraries for simulation. verilog Contains the Verilog HDL libraries for , before you can generate programming files or EDIF, VHDL, or Verilog HDL gate-level netlist files for , files or EDIF, VHDL, or Verilog HDL gate-level netlist files for simulation in third-party EDA tools


Original
PDF
2010 - verilog code for CORDIC to generate sine wave

Abstract: verilog code for cordic algorithm vhdl code for cordic verilog code for cordic verilog code to generate sine wave CORDIC to generate sine wave fpga vhdl code to generate sine wave vhdl code for rotation cordic vhdl code for FFT 32 point CORDIC to generate sine wave
Text: testbenches for VHDL, Verilog HDL and MATLAB Includes dual-output oscillator and quaternary frequency , _tb.vhd A VHDL or Verilog HDL testbench file for the MegaCore function variation. The VHDL , EDIF netlist file (.edf) or a Verilog Quartus Mapping (VQM) file (.vqm) for input to the Quartus II , resolution. (2) The maximum value is 24 for small and large ROM algorithms; 32 for CORDIC and , information about the CORDIC algorithm, refer to A Survey of CORDIC Algorithms for FPGAs by Andraka, Ray


Original
PDF
2008 - verilog code for cordic

Abstract: verilog code for logarithm intel 80387sx CORDIC divider math coprocessor FPGA sinus intel 80c186 verilog code for implementation of rom CORDIC in xilinx 80387
Text: Post-synthesis EDIF netlist (RTL source code also available) Set of constants required by the CORDIC unit for , , including support for arithmetic, logarithmic, exponential, and trigonometric mathematical operations. It is upward object-code compatible with the 8087math coprocessor and will execute code written for the 80387DX , Implements ANSI/IEEE Stan- dard 754-1985 for binary floating point arithmetic C80187 Math , - The C80187 core implements a math coprocessor that can serve as a replacement for the IntelTM 80C187


Original
PDF C80187 80-bit 80387DX 80387SX C80187 80C187. C80186XL 80C186 verilog code for cordic verilog code for logarithm intel 80387sx CORDIC divider math coprocessor FPGA sinus intel 80c186 verilog code for implementation of rom CORDIC in xilinx 80387
2009 - verilog code for cordic algorithm

Abstract: CORDIC to generate sine wave fpga vhdl code for cordic cosine and sine vhdl code for cordic algorithm sin wave with test bench file in vhdl cordic algorithm code in verilog CORDIC altera cordic sine cosine generator vhdl QFSK matlab code to generate sine wave using CORDIC
Text: Toolbench interface IP functional simulation models for use in Altera-supported VHDL and Verilog HDL , Generates simulation files and architecture-specific testbenches for VHDL, Verilog HDL and MATLAB , top-level output file type for your design; the wizard supports VHDL and Verilog HDL. © November 2009 , Verilog HDL model produced by the Quartus II software. c Use the simulation models only for , simulation model. _bb.v Verilog HDL black-box file for the MegaCore function variation


Original
PDF
2011 - VERILOG Digitally Controlled Oscillator

Abstract: verilog code of sine rom matlab code to generate sine wave using CORDIC EP3C10F256 QFSK verilog code to generate sine wave matlab code for half adder CORDIC to generate sine wave fpga verilog code for digital modulation cyclone iii CORDIC altera sine and cos
Text: models for use in Altera-supported VHDL and Verilog HDL simulators © May 2011 Altera Corporation , Generates simulation files and architecture-specific testbenches for VHDL, Verilog HDL and MATLAB Includes , the top-level output file type for your design; the wizard supports VHDL and Verilog HDL. © May , software. A VHDL or Verilog HDL testbench file for the MegaCore function variation. The VHDL file is , defines the IP functional simulation model. Verilog HDL black-box file for the MegaCore function variation


Original
PDF
2000 - vhdl code for cordic cosine and sine

Abstract: verilog code to generate sine wave vhdl code to generate sine wave verilog code for CORDIC to generate sine wave CORDIC to generate sine wave verilog code for cordic algorithm sine cosine qpsk modulation VHDL CODE VHDL code for CORDIC to generate sine wave vhdl code for cordic algorithm matlab code to generate sine wave using CORDIC
Text: MHz. For applications requiring high-precision waveforms, a CORDIC architecture is more , values are created by the CORDIC algorithm, are most effective for applications that require lower frequency and higher precision. CORDIC implementations use a very small ROM block and one clock cycle for , and drop into your system design Verilog HDL models used for simulation in other EDA tools , s Family: APEXTM 20K, ACEXTM, FLEX® 10, FLEX 8000, and FLEX 6000 s s s s Ordering Code


Original
PDF
1999 - vhdl code for cordic algorithm

Abstract: verilog code for cordic verilog code for logarithm verilog code for cordic algorithm cordic algorithm code in verilog vhdl code for cordic verilog code for cordic algorithm sine cosine vhdl code for cordic cosine and sine verilog code of sine rom vhdl cordic code
Text: ) Fully configurable Source code : VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation , VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist , DCORDIC CORDIC processor ver 1.16 The DCORDIC uses the CORDIC algorithm to compute , , arcus tangent functions for hyperbolic and trigonometric systems. Logarithm, square root and exponent


Original
PDF 24-bit IEEE-754 vhdl code for cordic algorithm verilog code for cordic verilog code for logarithm verilog code for cordic algorithm cordic algorithm code in verilog vhdl code for cordic verilog code for cordic algorithm sine cosine vhdl code for cordic cosine and sine verilog code of sine rom vhdl cordic code
2000 - CORDIC vhdl altera

Abstract: CORDIC QAM modulation 16 QAM modulation matlab vhdl cordic CORDIC "vhdl" cordic nco verilog QAM matlab cosine qam by simulink matlab
Text: 8000 FLEX 6000 - EAB ROM ROM ESB - EAB ESB Coordinate rotation digital computer CORDIC - , ROM CORDIC ROM sine/cosine ROM ROM 90 ROM sine cosine 90 ROM sine cosine 2 ROM CORDIC CORDIC sine cosine CORDIC NCO sine cosine CORDIC x y cosine sine , CORDIC ROM CORDIC sine cosine CORDIC ROM 1 ROMNCO 1NCO , Accumulator precision Angular precision Magnitude precision CORDIC architecture ROM


Original
PDF 20KACEXTM 10KFLEX 20KACEXTM 10KFLEX 20KFLEX CORDIC vhdl altera CORDIC QAM modulation 16 QAM modulation matlab vhdl cordic CORDIC "vhdl" cordic nco verilog QAM matlab cosine qam by simulink matlab
2008 - source code verilog for qr decomposition

Abstract: verilog code for 4 bit multiplier testbench matlab code for mimo ofdm verilog code for mimo ofdm vhdl code for cordic algorithm RLS matlab verilog code for inverse matrix cordic vhdl code for rotation cordic vhdl code for cordic
Text: model, VHDL constants and CORDIC Verilog HDL parameters to text files for use in RTL simulation and , cntl.wrfile.ip Testbench writes Verilog HDL parameters ( for selected model configuration of CORDIC ) to the , computer ( CORDIC ) algorithm reference design ModelSim VHDL self-checking testbench Sample data sets for , Writes input data, output data, VHDL constants, and Verilog HDL constants to text files for RTL , Altera's CORDIC reference design to perform the Givens rotations. f Altera Corporation For more


Original
PDF
2000 - FSK modulate by matlab book

Abstract: adpll.mdl quadrature amplitude modulation a simulink model simulink 16QAM QAM verilog 16 QAM modulation matlab vhdl program for cordic cosine and sine CORDIC QAM modulation pulse amplitude modulation using 555 FSK matlab
Text: CORDIC implementations. 3 2 Specifications s s s s s s s Optimized for multiple device , generated Verilog HDL models, bit-accurate to MATLAB files Reference designs provided for a digital , Frequency For applications that require high precision and low frequency, a CORDIC implementation, in , approximate the cartesian coordinate values for the input angle. At the end of the CORDIC iteration, the x , 3. CORDIC Rotation for Sine & Cosine Calculcation y dø dy sin ø ø cos ø x dx An


Original
PDF -UG-NCOCOMPILER-01 FSK modulate by matlab book adpll.mdl quadrature amplitude modulation a simulink model simulink 16QAM QAM verilog 16 QAM modulation matlab vhdl program for cordic cosine and sine CORDIC QAM modulation pulse amplitude modulation using 555 FSK matlab
1999 - 8051 16bit addition, subtraction

Abstract: verilog code for floating point division verilog code for single precision floating point multiplication vhdl code for cordic cosine and sine verilog code for floating point multiplication vhdl code for cordic program for 8051 16bit square root vhdl code for cordic multiplication test bench for 16 bit shifter verilog code for cordic
Text: to 12 months. Single Design license for VHDL, Verilog source code called HDL Source int , code : VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL , Floating Point Mathematics Unit ver 1.30 OVERVIEW DFPMU uses the specialized CORDIC and , : Precision lack PE KEY FEATURES Direct replacement for C float software functions such as: +, -, *, /,=, !=,>=, <=, <, > C interface supplied for all popular compilers: GNU C/C+, 8051 compilers No


Original
PDF IEEE-754 16-bit 32-bit 32-bit 8051 16bit addition, subtraction verilog code for floating point division verilog code for single precision floating point multiplication vhdl code for cordic cosine and sine verilog code for floating point multiplication vhdl code for cordic program for 8051 16bit square root vhdl code for cordic multiplication test bench for 16 bit shifter verilog code for cordic
2012 - Not Available

Abstract: No abstract text available
Text: obligation to compensate and scale for the magnitude outputs gain introduced by the CORDIC algorithm. Refer , Simulation support for the CORDIC IP core is provided for Aldec Active-HDL ( Verilog and VHDL) simulator , Facts Table 1-1 through Table 1-7 give quick facts about the CORDIC IP core for LatticeECPâ , , respectively. Table 1-1. CORDIC IP Core for LatticeECP Devices Quick Facts CORDIC IP Configuration Rotate , Introduction Table 1-2. CORDIC IP Core for LatticeECP2 Devices Quick Facts CORDIC IP Configuration Rotate


Original
PDF IPUG81 MULT18X18 LFXP2-30E-7F484C D-2009 12L-1
2007 - wireless power transfer matlab simulink

Abstract: wcdma simulink vhdl code for cordic Crest factor reduction CORDIC vhdl altera verilog code for histogram simulink model verilog code for cdma simulation FIR filter matlaB design code cdma simulink
Text: one-half of this value. Scale Compensation factor Scaling for peak window calculation. CORDIC phase bit width The size of the calculation for phase in CORDIC . CORDIC XY precision The increase in the , a mix of Verilog HDL ( CORDIC ) and VHDL (everything else). Synthesize the Design To synthesize , /./ cordic /source/ verilog " vlog +incdir+$cordicdir -y $cordicdir +libext+.v "Cordic_subsystem.v" 13 , interpolated baseband to determine which delayed baseband symbols to modify Good for ACLR; not so good for


Original
PDF
1999 - verilog code for floating point multiplication

Abstract: vhdl code for cordic cosine and sine vhdl code for 8 bit floating point processor verilog code for double precision floating point multiplication verilog code for cordic verilog code for single precision floating point multiplication 8051 16bit addition, subtraction verilog code for single precision floating point addition CORDIC altera IEEE 754
Text: . Single Design license for VHDL, Verilog source code called HDL Source Encrypted, or plain text , Source Code or/and VERILOG Source Code or/and Encrypted Netlist or/and plain text EDIF netlist , 's DP8051, but can also operate with any other 8-, 16- and 32-bit processor. Drivers for all popular 8051 C compilers are delivered together with the DFPMU-DP package. DFPMU-DP uses the specialized CORDIC and , DCD ­ Digital Core Design. All Rights Reserved. KEY FEATURES Direct replacement for C double


Original
PDF
2006 - cordic sine cosine generator vhdl

Abstract: vhdl code for cordic algorithm cordic vhdl code for cordic vhdl code for rotation cordic vhdl code for vector cordic verilog code for cordic verilog code for cordic algorithm cordic algorithm code in verilog vhdl code for cordic cosine and sine
Text: Rotation DIgital Computer ( CORDIC ) Rotator Function for Actel FPGAs · · · Sine and Cosine , .0 1 CoreCORDIC CORDIC RTL Generator coordinates, for general vector rotation, and also to , CORDIC modes. Magnitude r Phase x CORDIC Engine y The gain can be compensated for , data for CoreCORDIC, implemented in various Actel devices with the CORDIC engine bit resolution set to , hardware processor for every CORDIC iteration. An example of the parallel CORDIC architecture configured


Original
PDF
1999 - verilog code for floating point multiplication

Abstract: vhdl code for cordic cosine and sine verilog code for floating point division VHDL code for floating point addition vhdl code for cordic vhdl code for cordic multiplication program for 8051 16bit square root 8051 16bit addition, subtraction verilog code for single precision floating point multiplication CORDIC sine cosine float altera
Text: for VHDL, Verilog source code called HDL Source code : VHDL Source Code or/and VERILOG Source Code or/and Encrypted Netlist or/and plain text EDIF netlist VHDL & VERILOG test bench environment , . Drivers for all popular 8051 C compilers are delivered together with the DFPMU package. DFPMU uses the specialized CORDIC and standard algorithms to compute math functions. It supports addition, subtraction , control KEY FEATURES Direct replacement for C float software functions such as: +, -, *, /,=, !=,>=


Original
PDF DP8051, 32-bit verilog code for floating point multiplication vhdl code for cordic cosine and sine verilog code for floating point division VHDL code for floating point addition vhdl code for cordic vhdl code for cordic multiplication program for 8051 16bit square root 8051 16bit addition, subtraction verilog code for single precision floating point multiplication CORDIC sine cosine float altera
2011 - vhdl code for rotation cordic

Abstract: DS858 LogiCORE IP CORDIC CORDIC divider cordic design for fixed angle rotation CORDIC in xilinx CORDIC v5.0 XC7K325T CORDIC v4.0 cordic algorithm code in verilog
Text: CORDIC core provides the option of automatically compensating for the CORDIC scale factor. The CORDIC , CORDIC scale factor, Zn. The compensation scaling module compensates for the effect of CORDIC magnitude , is provided to compensate for the CORDIC scale factor Zi. For this functional configuration, the , Optional amplitude compensation scaling module to compensate for the output amplitude scale factor of the , configurations are available for the CORDIC core: · · A fully parallel configuration with single-cycle data


Original
PDF DS858 ZynqTM-7000, vhdl code for rotation cordic LogiCORE IP CORDIC CORDIC divider cordic design for fixed angle rotation CORDIC in xilinx CORDIC v5.0 XC7K325T CORDIC v4.0 cordic algorithm code in verilog
FSK ask psk by simulink matlab

Abstract: digital modulation carrier ASK,PSK and FSK FSK ask psk by matlab FSK matlab cordic algorithm code in verilog verilog code for cordic algorithm verilog code for cordic verilog coding for CORDIC ALGORITHM EP2C35F672C6 FSK modulate by matlab book
Text: The CORDIC algorithm for this mode is derived from the general rotation transform: xfin = xincos - , Andraka, "A survey of cordic algorithms for FPGA based computers," International Symposium on Field , technology extends the use of the system for a wide range of applications. Application Scope SDR , , wideband code division multiple access (W-CDMA), general packet radio services (GPRS), etc. SDR has , Designers can use FPGAs efficiently for digital signal processing (DSP) and other computationally intensive


Original
PDF
2007 - tcl script ModelSim

Abstract: P802 vhdl cyclic prefix vhdl "channel estimation"
Text: Ranging Modules for WiMAX set cordic_srcdir "D:/work/ cordic /source/ verilog " # set to one if , proj_topdir "D:/work/WiMax/wimax_ofdma" set cordic_srcdir "D:/work/ cordic /source/ verilog " 5. To ensure , cordic_srcdir "D:/work/ cordic /source/ verilog " 2. To ensure that the ModelSim simulator is run in command , Integrating Uplink Desubchannelization & Ranging Modules for WiMAX Application Note 457 , of a worldwide interoperability for microwave access (WiMAX) compliant basestations. All of Altera


Original
PDF
2006 - matlaB

Abstract: nco v7.0 CORDIC altera
Text: Simulation Targeting VCS With Parsing Error 2 The Valid Signal is Incorrect for Serial CORDIC Architectures f 1 2 For the most up-to-date errata for this release, refer to the errata sheet on the , the NCO Compiler. The Valid Signal is Incorrect for Serial CORDIC Architectures When the CORDIC , and documentation issues for the Altera® NCO Compiler, v7.0. Errata are functional defects or errors , simulation using the NCO Compiler generated Verilog HDL testbench targeting the NativeLink VCS simulation


Original
PDF
2006 - CORDIC

Abstract: nco verilog
Text: Simulation Targeting VCS With Parsing Error 2 The Valid Signal is Incorrect for Serial CORDIC Architectures f 1 2 For the most up-to-date errata for this release, refer to the errata sheet on the , the NCO Compiler. The Valid Signal is Incorrect for Serial CORDIC Architectures When the CORDIC , and documentation issues for the Altera® NCO Compiler, v6.1. Errata are functional defects or errors , simulation using the NCO Compiler generated Verilog HDL testbench targeting the NativeLink VCS simulation


Original
PDF
Supplyframe Tracking Pixel