The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC1264-7CN Linear Technology LTC1264-7 - Linear Phase, Group Delay Equalized, 8th Order Lowpass Filter; Package: PDIP; Pins: 14; Temperature Range: 0°C to 70°C
LTC1264-7CSW Linear Technology LTC1264-7 - Linear Phase, Group Delay Equalized, 8th Order Lowpass Filter; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC1264-7CSW#TRPBF Linear Technology LTC1264-7 - Linear Phase, Group Delay Equalized, 8th Order Lowpass Filter; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC1264-7CSW#TR Linear Technology LTC1264-7 - Linear Phase, Group Delay Equalized, 8th Order Lowpass Filter; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC1264-7CN#PBF Linear Technology LTC1264-7 - Linear Phase, Group Delay Equalized, 8th Order Lowpass Filter; Package: PDIP; Pins: 14; Temperature Range: 0°C to 70°C
LTC1264-7CSW#PBF Linear Technology LTC1264-7 - Linear Phase, Group Delay Equalized, 8th Order Lowpass Filter; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C

verilog code for lms adaptive equalizer Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1998 - lms algorithm using verilog code

Abstract:
Text: Verilog HDL files are available from most partners, a source code license is usually more expensive than a , directly for an authorization code ; the AMPP partner will generate this code based on your MAX+PLUS II PC , File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL instantiation templates Megafunction , printing date, but megafunction specifications and availability are subject to change. For the most current , Data Communication (Telecom and Datacom) Digital Signal Processing (DSP) For additional details on


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2002 - LMS adaptive filter model for FPGA vhdl

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Text: based on the assumption of damping factor of 0.71 MUCMAEQ Input 2 Equalizer m select for , for DD LMS mode 00: 1/8192 01: 1/4096 10: 1/2048 11: 1/1024 RXSYNC Output 1 Output , value for ideal signal, static programming signal 0: 1/2 1: ¾ LCKWINBLL Input 1 BLL lock , state to initial state in which the equalizer is put into CMA mode. The CLL acquisition starts after the initial period. AFCCLL Input 1 Use or not use AFC for frequency offset estimate


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PDF CS3810 74MHz) DS3810 LMS adaptive filter model for FPGA vhdl verilog code for lms adaptive equalizer verilog code for TCM decoder 12-bit ADC interface vhdl code for FPGA qam demodulator LMS adaptive filter model for FPGA vhdl code REED SOLOMON demodulator fpga 32 QAM vhdl coding for error correction and detection
2002 - 16 QAM modulation verilog code

Abstract:
Text: factor of 0.71 MUCMAEQ Input 2 Equalizer m select for CMA mode 00: 1/1024 01: 1/512 10: 1/256 11: 1/128 MUDDEQ Input 2 Equalizer m select for DD LMS mode 00: 1/8192 01: 1/4096 , CS3810 TM 32 QAM Demodulator Virtual Components for the Converging World The CS3810 32 , optimized solution for wireless data networks. Combined with the CS3710 32 QAM modulator core data transmission speeds of up to 155Mbps can be achieved at low error rates. The CS3810 is suited for applications


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PDF CS3810 CS3810 CS3710 155Mbps CS5200 DS3810 16 QAM modulation verilog code 4 QAM modulator demodulator circuitry verilog code for lms adaptive equalizer verilog code for TCM decoder VHDL Coding for Pulse Width Modulation vhdl coding for error correction and detection LMS adaptive filter model for FPGA vhdl CS-3810
2001 - GSM 900 simulink matlab

Abstract:
Text: Adaptive Equalizer (PLSM-HC-EQUALIZER) HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury , ® Signal Processing IP Megafunctions Signal Processing Solutions for System-on-a , for Existing Designs portfolio-including MegaCore® and Altera Megafunction Signal processing IP , code while enjoying the PLD You can download signal processing IP functions benefits of hardware , functions have Figure 2. Hardware Acceleration for DSP Processor Systems a user-friendly


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PDF M-GB-SIGNAL-01 GSM 900 simulink matlab verilog code for ofdm transmitter fir filter coding for gui in matlab digital IIR Filter VHDL code digital IIR Filter verilog code vhdl code for ofdm transmitter qpsk modulation VHDL CODE vhdl code for ofdm qpsk demapper VHDL CODE verilog code for iir filter
2009 - Video sync splitter lm

Abstract:
Text: ® Adaptive Cable Equalizer LMH0384 Adaptive Cable Equalizer Cable Length Indicator Features 30 CLI , extended reach adaptive cable equalizer 3.3 230 143 to 2970 Ind SD384EVK NEW! LMH0344GR/SQ 3G/HD/SD adaptive cable equalizer 3.3 280 143 to 2970 Ind SD344EVK Array-25/LLP-16 LMH0044SQ HD/SD adaptive cable equalizer 3.3 208 143 to 1485 Ext SD044EVK LLP-16 LMH0034MA HD/SD adaptive cable equalizer 3.3 208 143 to 1485 Ext SD034EVK


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2008 - HDMI verilog code

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Text: for 3 Gbps SDI (3G-SDI) data transmissions, including adaptive equalizer , reclocker, cable driver , Adaptive Equalizer LMH1981 Sync Separator LVDS Rx Data (5-bit) SD Clock LVDS Input Clocks , SDI In Reclocked Loop Through SMBus LMH0344 3G-SDI Adaptive Equalizer LMH0341 3G , both level-A and level-B 3G SDI formats Source code provided in synthesizable HDL ( Verilog , VHDL , ! LMH0344SQ 3G/HD/SD Adaptive Cable Equalizer 3.3 280 143-2970 Ind SD344EVK LMH0044SQ


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2010 - HDMI verilog code Altera

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Text: Altera's high-speed mezzanine connector (HSMC). National provides FPGA source code for SMPTE protocol , /VSYNC Analog Ref-In SMBus LMH0341 3G-SDI Deserializer LMH0344 Adaptive Equalizer , Reclocked Loop Through LMH0344 Adaptive Equalizer H/VSYNC Analog Ref-In LMH1981 Sync Separator , 3G/HD/SD extended reach adaptive cable equalizer 3.3 230 143 to 2970 Ind SD384EVK NEW! LMH0344GR/SQ 3G/HD/SD adaptive cable equalizer 3.3 280 143 to 2970 Ind


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PDF LMP7704 ADC121S101 HDMI verilog code Altera sdi to hdmi converter ic HDMI to SDI converter chip LMH0034MA pmbus verilog hdmi to SDI IC DS92LV1021A SD131EVK 3G-SDI serializer IEEE1588
2007 - HDMI verilog code

Abstract:
Text: OTP ROM Adaptive Equalizer Has dithering feature for bit width reduction to improve image , customers through all phases (IP) cores can be used for a variety of digital video and of development , at a maximum of 2.30 Gbps for all currently existing HD (high definition) monitor standards. The , resolution. Refer to the chart on the Timing Models (.lib) reverse side for resolutions, refresh rates , ) Soft Macro The DSP-based design provides superior performance RTL Code that exceeds the


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2009 - HDMI to SDI converter chip

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Text: 20 mm2 Configurable 3G SDI PowerWise® Adaptive Cable Equalizer LMH0384 ­ Adaptive Cable , adaptive cable equalizer 3.3 230 143 to 2970 Ind SD384EVK NEW! LMH0344GR/SQ 3G/HD/SD adaptive cable equalizer 3.3 280 143 to 2970 Ind SD344EVK microArray-25. LLP-16 LMH0044SQ HD/SD adaptive cable equalizer 3.3 208 143 to 1485 Ext SD044EVK LLP-16 LMH0034MA HD/SD adaptive cable equalizer 3.3 208 143 to 1485 Ext SD034EVK SOIC


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2010 - HDMI to SDI converter chip

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Text: Through Clocks* Parallel SMBus SDI In LMH0344 3G-SDI Adaptive Equalizer LMH0341 3G , adaptive cable equalizer 3.3 280 143 to 2970 Ind SD344EVK microArray-25. LLP-16 LMH0044SQ HD/SD adaptive cable equalizer 3.3 208 143 to 1485 Ext SD044EVK LLP-16 LMH0034MA HD/SD adaptive cable equalizer 3.3 208 143 to 1485 Ext SD034EVK SOIC-16 LMH0074SQ SD adaptive cable equalizer with cable detect 3.3 208 143 to 540 Ind SD074EVK


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PDF LMP7704 ADC121S101 HDMI to SDI converter chip sdi to hdmi converter ic vhdl code for spartan 6 audio SDI to HDMI converter chip HDMI verilog code free vhdl code for pll LMH0034MA CAT-5 Sdi IC xilinx video broadcast pmbus verilog
1997 - free vHDL code of median filter

Abstract:
Text: in MAX+PLUS II GDFs Include File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL , for Communications Sample rates ranging from 2 kHz to over 75 MHz Fully parameterized adaptive , megafunction descriptions and partner profiles for each AMPP partner. The information in this catalog is current as of the print date, but megafunction specifications and availability are subject to change. For , applicable standards compliance, and a table with fitting and performance specifications. See page 11 for


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1997 - verilog code for 2D linear convolution

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Text: File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL instantiation templates Megafunction , trademark laws. Altera Corporation acknowledges the trademarks of other organizations for their respective , . Verilog and Cadence are registered trademarks of Cadence Design Systems, Inc. SCVL, SCVL-S, MOR , for a particular purpose, or non-infringement of any patent, copyright, or their intellectual property rights. In the absence of written agreement to the contrary, Altera assumes no liability for Altera


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PDF M-CAT-AMPP-02 EPF10K10, EPF10K20, EPF10K30, EPF10K40, EPF10K50, EPF10K70, EPF10K100, EPF8282, EPF82828A, verilog code for 2D linear convolution verilog code for GPS correlator vhdl code numeric controlled oscillator pipeline rx UART AHDL design verilog code car parking free verilog code of median filter verilog code for 2D linear convolution filtering verilog code for median filter LED Dot Matrix vhdl code 16 QAM modulation verilog code
2006 - mystiphy110

Abstract:
Text: Reference Design Design Models HDL simulation models Verilog Test Bench Stamp Models TranSwitch provides intellectual property (IP) cores for Fast Ethernet (10/100) and Gigabit Ethernet (GigE) PHY applications, plus engineering services to customize these cores for specific applications. TranSwitch has designed over a dozen specific cores for 10/100 Ethernet PHY devices and most customers can license a hard , approach provides superior performance that exceeds the IEEE 802.3 requirements for cable length and


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PDF MystiPHY110 MystiPHY110 Mystiphy TranSwitch
2010 - CTXIL671

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Text: Configurable 3G SDI Adaptive Cable Equalizer Features · SMPTE-standard compliant ° Supports SMPTE 424M (3G , (HSMC). National provides FPGA source code for SMPTE protocol processing with the purchase of a , Comprehensive reference for hardware design and FGPA IP development · Included HDL ( Verilog , VHDL source , Clock Generators Clocks Coax LMH0344 3G-SDI Adaptive Cable Equalizer Coax LMH0344 3G-SDI Adaptive Cable Equalizer Coax LMH0302 3G-SDI Cable Driver Coax LMH0302 3G-SDI Cable Driver


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PDF 16-channel CTXIL671 Video sync splitter lm lmh0387 xilinx Mini DisplayPort cable hd-SDI splitter HDMI verilog code SOT23-5 i2c based pwm generator hdmi SDI HDMI to SDI converter chip ml605 bom
2006 - VHDL code for polyphase decimation filter using D

Abstract:
Text: Analog LPF -j2nft e NCO RF Oscillator T/2-spaced Feed Forward Adaptive Equalizer , interest. Since the adaptive equalizer in Figure 1 normally operates on an input that is sampled at twice , Forward fsym Adaptive Equalizer Timing Recovery CLK Oscillator Errors Coarse Carrier , enter the adaptive equalizer block at 2*fsym, then the resampler block must decimate (digitally lower , (IF) and then sampled at a particular (constant) frequency for all supported signals. The sample rate


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PDF XAPP936 xapp936 VHDL code for polyphase decimation filter using D verilog code for decimation filter VHDL code for polyphase decimation filter 16 QAM modulation verilog code 16 QAM modulation matlab vhdl code for qam qpsk modulation VHDL CODE verilog code for decimator SDR baseband modulation demodulation DSP48
fuzzy logic motor code

Abstract:
Text: implement the design control rules. When writing the program, we chose the Verilog HDL language for , the complementary code and fixed-point methods are available, users unfamiliar with Verilog HDL , , using the Nios II embedded processor for the design we wrote our code with the familiar C language , software to write Verilog HDL code (motor angle count module, D/A control module) corresponding to the , peripheral circuit is designed in Verilog HDL. We used the Nios II processor for the control rules, which


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2004 - verilog code for apb

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Text: the verification deliverables for : · directed test Verilog testbench · integration test , language used for the design implementation is the Verilog HDL. The following design tools are used: · , intended. Adaptive Voltage Scaling (AVS) Support for controlling the multi-level power supply to a , controlled. It monitors the system delay for the adaptive voltage scaling control. HPM Glossary-2 See , Change First release for r0p0 Proprietary Notice Product features and specifications described in


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PDF 9297-APC1-D101 verilog code for apb 9297-APC1-D101 verilog code voltage regulator SY751-DC-06002 APC1 Release Notes SY751-DA-03001 SY751-DC-06002 timing diagram of AMBA apb protocol SY751-MN-22001 LN+9297 SY751-DC-08001
2010 - verilog code for interpolation filter

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Text: modulation bandwidth Provides 20-30dB ACP correction capability Adaptive transmit equalizer and AQM , Self-checking test bench with programs to generate golden output Verilog source code is provided to enable , that are ready-to-use right out of the box. For wireless applications, a full suite of tested , Demonstration Designs Test and Interoperability Reports for PMA, PCS and Generic I/O Silicon , Low-Cost Digital SERDES ·Ideal for low-cost chip-to-chip and small form-factor backplane applications Up


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PDF JESD204a LatticeMico32 1-800-LATTICE I0197B LatticeMico32, verilog code for interpolation filter verilog code for decimation filter gsm simulink VITA-57 fmc ECP3-150 Lattice ECP3 ofdm predistortion SFP CPRI EVALUATION BOARD ECP3-35 ECP3-95
2006 - verilog code for interrupt controller amba based

Abstract:
Text: components required for implementing the AVS power management system. Performance code HPM clock HPM , deliverables for : · directed test Verilog testbench · integration test Verilog testbench. Table 2-6 , Design tools The hardware description language used for the design implementation is the Verilog HDL , . Adaptive Voltage Scaling (AVS) Support for controlling the multi-level power supply to a subsystem to reduce voltage to the minimum level for the required performance. This is achieved by using adaptive


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PDF 10349-APC2-D101 verilog code for interrupt controller amba based AN 10349 APC2 emu verilog code for ALU implementation verilog code for apb verilog code voltage regulator
2000 - quantizer verilog code

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Text: .727a. It specifies the requirements for the conversion of a 64 kbit/s pulse code modulation (PCM) channel to and from a 40, 32, 24 and 16 kbit/s channel, using an Adaptive Differential Pulse Code , signal for transmission. Inverse Adaptive Quantizer The Inverse Adaptive Quantizer block produces a , .727a ITU standards · 8 channel duplex encoding and decoding · Online configurable for different compression rates, µ-law and A-law for each encoding or decoding channel · A generic parameter in VHDL RTL


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1999 - quantizer verilog code

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Text: requirements for the conversion of a 64 kbit/s pulse code modulation (PCM) channel to and from a 40, 32, 24 and 16 kbit/s channel, using an Adaptive Differential Pulse Code Modulation (ADPCM) transcoding technique , Testbench, Test Vectors Instantiation Templates VHDL, Verilog Reference Designs & Application Notes None , .726a, and G.727, G.727a ITU standards · 8 channel duplex encoding and decoding · Online configurable for different compression rates, µ-law and A-law for each encoding or decoding channel · A generic parameter in


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PDF V150-6 quantizer verilog code G.723 codec 8 channel xilinx vhdl codes G.723. c code 2 bit address decoder coding using verilog hdl 8 bit parallel multiplier vhdl code encoder verilog coding verilog hdl code for modulation vhdl code for digital clock input id
SIIGX52006-1

Abstract:
Text: MegaWizard Plug-In Manager provides a wizard that allows you to specify options for the ALT2GXB_RECONFIG , the device family. Your desired type of output file format ( Verilog , VHDL, or AHDL). Your desired file name. For the design to compile successfully, you must enable the dynamic reconfiguration , . Check off the reconfig controller features that you would like to activate; for example, Analog , Settings) Table 5­1 describes the available options on page 3 of the MegaWizard Plug-In Manager for


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PDF SIIGX52006-1 RECONFIG
1996 - 10BASET4

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Text: this ap plication. The high precision currents needed for the transmit DAC and equalizer are derived , 100BASET4 Ethernet Network Repeater using the Cypress CY7C971 PHY and CY7C388P for the core logic. The , Standard MAC Parameters, Physical Layer, Medium At tachment Units and Repeater for 100 Mb/s Opera tion," , required to interface to the twistedpair media such as transmit filtering, adaptive equalization, and D , transformer for electrical isolation from onchip. A quad 2:1 transformer for electrical isola the medium


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PDF 100BASE 100BASET4 CY7C971 CY7C388P 100Mb/s 100BASET4 100BASET4, 10BASET4 transformer ethernet mux Led driver 100W schematic symbol of transformer 10BASE power supply driver led 100w schematic RJ45 modular jack
verilog code for cdma transmitter

Abstract:
Text: implementation. The Walsh generator Verilog code also illustrates several key points for reliable design. In the , if the clock ran at 20MHz, it would still take 2.5 days for the cycle to repeat. A 31bit PN code , reader into a Verilog expert. Walsh Code Generator The Walsh Code generator is usually described in , observation is made, the Walsh matrix may seem a daunting module to generate with Verilog code and fit in a CPLD. The listing of the Verilog code is included here as a sample only. module walsh( clk, resetn


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PDF 9152MHz CY37256 com/an918 MAX2361: AN918, APP918, Appnote918, verilog code for cdma transmitter verilog code for matrix inversion 15-bit* pn sequence digital mixer verilog code code for pn generator in digital PN generator circuit 4 bit pn sequence generator verilog code cdma pn sequence generator verilog code digital radio verilog code
fpga vhdl code for crc-32

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Text: Language VHDL / Verilog Source Code or Encrypted VHDL / Verilog Sources Code for Altera FPGAs , Delivery Language BIN Encrypted VHDL / Verilog Sources Code for Altera FPGAs and Structured ASICs. VHDL Synthesizable generic VHDL source code for Altera FPGA and Structured ASICs or ASIC implementations VLOG Synthesizable generic Verilog source code for Altera FPGA and Structured ASICs or ASIC , based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus


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PDF 10000Mbps) 10GbEth 100MbEth 10MbEth fpga vhdl code for crc-32 vhdl code for mac interface vhdl code CRC vhdl code switch layer 2 block code error management, verilog source code vhdl code CRC 32 VHDL MAC CHIP CODE 1000BASE-KX ethernet mac verilog testbench 10GBASE-KX4
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