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Part Manufacturer Description Datasheet Download Buy Part
LTC3444EDD#PBF Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD#TRPBF Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD#TR Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC6401CUD-8 Linear Technology LTC6401-8 - 2.2GHz Low Noise, Low Distortion Differential ADC Driver for DC-140MHz; Package: QFN; Pins: 16; Temperature Range: 0°C to 70°C
LTC6401CUD-20#TRPBF Linear Technology LTC6401-20 - 1.3GHz Low Noise, Low Distortion Differential ADC Driver for 140MHz IF; Package: QFN; Pins: 16; Temperature Range: 0°C to 70°C

verilog code for adc Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1998 - verilog code for adc

Abstract: verilog code of 8 bit comparator ADC Verilog Implementation ADC DAC Verilog 2 bit Implementation verilog code of 16 bit comparator adc verilog analog to digital converter verilog verilog code of 4 bit comparator verilog code of 3 bit comparator verilog code for serial multiplier
Text: optional. It may not be necessary if wire lengths are short. See "Appendix B - ADC Top Level Verilog Code - File ADCtop.v" on page 8 which shows an example of top-level Verilog code for the ADC 2.00 , to the Verilog code located in "Appendix A - ADC Verilog Implementation" on page 5 and and the , 1.1) 7 Virtex Analog to Digital Converter Appendix B - ADC Top Level Verilog Code - File , . This process continues for each bit of the DAC input. The DAC is one bit wider than the ADC output


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PDF XAPP155 10-bit CLK90( CLK180( CLK270( verilog code for adc verilog code of 8 bit comparator ADC Verilog Implementation ADC DAC Verilog 2 bit Implementation verilog code of 16 bit comparator adc verilog analog to digital converter verilog verilog code of 4 bit comparator verilog code of 3 bit comparator verilog code for serial multiplier
2012 - verilog code for eeprom i2c controller

Abstract: EP4CE22F17C6 qpf 128
Text: will write Verilog HDL code for a simple 32-bit counter, add a phase-locked loop (PLL) megafunction as , Input 3.3V Table 3-9 Pin Assignments for ADC Signal Name ADC_CS_N ADC_SADDR ADC_SDAT ADC_SCLK , part is implemented in Verilog HDL code with SOPC builder. The source code is not available on the , name>.v Description Top level Verilog HDL file for Quartus II 2 .qpf Quartus , . 31 4.6 ADC


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PDF EPCS16 EPCS64 verilog code for eeprom i2c controller EP4CE22F17C6 qpf 128
2011 - EP4CE22f17

Abstract: EP4CE22F17C6 12-bit ADC interface vhdl complete code for FPGA PWM fpga uart vhdl verilog code for eeprom i2c controller power wizard 1.1 wiring diagram ftdi ep4ce PINB13 ep4ce22
Text: Verilog HDL code for a simple 32-bit counter, add a phase-locked loop (PLL) megafunction as the clock , Verilog HDL file The resulting empty file is ready for you to enter the Verilog HDL code . 4. Type the , 3.3V 3.3V 3.3V 3.3V Table 3-9 Pin Assignments for ADC Signal Name ADC_CS_N ADC_SADDR ADC_SDAT , hardware part is implemented in Verilog HDL code with SOPC builder. The source code is not available on the , .htm Description Top level Verilog HDL file for Quartus II Quartus II Project File Quartus II


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2004 - verilog code for adc

Abstract: EPM3032ATC44-10 parallel to serial conversion verilog CPLD military ADS8411 ADS8412 verilog code for adc MSPS
Text: .4 Appendix A. Logic Diagram, Description, and Verilog Code of the CPLD Program , , Description, and Verilog Code of the CPLD Program Figure A-1. Logic Diagram Using ADS8411/ADS8412 as , clock to the 15th clock. At the 16th clock, it falls to LOW and conversion starts. A.3 Verilog Code , Application Report SLAA199 ­ May 2004 Using ADS8411/ADS8412 as a Serial ADC Bhaskar Goswami , use a parallel ADC as a serial ADC by using a low-cost CPLD. This concept is tested with a Texas


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PDF SLAA199 ADS8411/ADS8412 ADS8411/12 16-bit, verilog code for adc EPM3032ATC44-10 parallel to serial conversion verilog CPLD military ADS8411 ADS8412 verilog code for adc MSPS
2010 - verilog code for adc

Abstract: adc controller vhdl code adc vhdl A2F500 adc verilog adc vhdl source code verilog code for apb PDMA verilog code for ahb bus matrix ACTEL flashpro
Text: ADC data or PPE Filtered Data or PPE processed data is made available for the PDMA to transfer to , , and starts processing as soon as it detects a non-empty ADC . The PPE microcode is responsible for , channel for ADC data transfer 4. Processing of ADC data to extract ADC result Configuring Hardware , . 3 SmartFusion: Using ACE with PDMA Configuring PDMA Channel for ADC data transfer Setting up , Files for Application Note File/Folder Name Description SmartFusion_TOP.pdb Verilog Libero


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PDF AC352 verilog code for adc adc controller vhdl code adc vhdl A2F500 adc verilog adc vhdl source code verilog code for apb PDMA verilog code for ahb bus matrix ACTEL flashpro
2006 - verilog code voltage regulator

Abstract: verilog code for adc verilog code voltage regulator vhdl verilog code for amba apb bus simple ADC Verilog code 16bit microprocessor using vhdl vhdl code for frequency divider verilog code for apb vhdl code for Clock divider for FPGA APB VHDL code
Text: in Actel Libero IDE Model RTL Version ­ ­ · Verilog and VHDL Core Source Code Fully , can be configured using toplevel parameters ( Verilog ) or generics (VHDL). For a detailed description , ( Verilog and VHDL) March 2006 © 2006 Actel Corporation 1 See Actel's website for the latest version , Simulation: OVI-Compliant Verilog Simulators and Vital-Compliant VHDL Simulators Core Verification · Key Features Comprehensive VHDL and Verilog Testbenches · User Can Easily Modify User


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PDF 51700066PB-0/3 verilog code voltage regulator verilog code for adc verilog code voltage regulator vhdl verilog code for amba apb bus simple ADC Verilog code 16bit microprocessor using vhdl vhdl code for frequency divider verilog code for apb vhdl code for Clock divider for FPGA APB VHDL code
2007 - PR68A

Abstract: QSH-060-01-F-D-A verilog code to generate sine wave PR69A verilog code for sine wave using FPGA vhdl code to generate sine wave 12-bit ADC interface vhdl code for FPGA PR63A sine wave output for fpga using verilog code ADS644X
Text: sample rates. Please see the TI ADS6XXX-EVM Board User Guide and the ADS6425 ADC Data Sheet for further , conditions for these 16 test runs are shown. 5 Lattice Semiconductor Lattice TI ADC Demo User , Lattice Semiconductor Lattice TI ADC Demo User's Guide Figure 5. Graph of results for tests 13 , . Demo Reference Design Verilog Sample Code , -Permission: Lattice Semiconductor grants permission to use this code for use in synthesis for any Lattice


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PDF ADS644X ADS642X ADS6245EVM) ADS6000 b0110 b0000 b0000000000 PR68A QSH-060-01-F-D-A verilog code to generate sine wave PR69A verilog code for sine wave using FPGA vhdl code to generate sine wave 12-bit ADC interface vhdl code for FPGA PR63A sine wave output for fpga using verilog code
2014 - Not Available

Abstract: No abstract text available
Text: Digital Converter ( ADC ) add-on suitable for most FPGA development kits. The OpenADC features a flexible , Connector for external clock input ▶▶ Separate voltage regulators for ADC & LNA ▶▶ Digilent Pmodâ , applications this will be acceptable, since the clock may only be used to generate the sample clock for the ADC . There will be many additional delays which will need to be compensated for in the ADC sample chain , for more detailed information about possible ADC output configurations. The ADC has a ‘duty cycle


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2007 - digital alarm clock vhdl code

Abstract: alarm clock design of digital VHDL verilog code for adc ADC Verilog Implementation alarm clock design of digital verilog alarm clock verilog hdl digital alarm clock vhdl code in modelsim xilinx vhdl code for digital clock UG192 alarm clock verilog code
Text: Outputs Channel selection outputs. The ADC input mux channel selection for the current ADC conversion , wizard can be configured to generate either a VHDL or Verilog wrapper for System Monitor. 3. Click , for the System Monitor ADC . However, the System Monitor ADC requires a clock source in the range of , Introduction LogiCORE Facts The System Monitor provides an integrated solution for thermal management , through a JTAG interface enabling a powerful tool for debugging and testing during hardware development


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PDF DS608 UG192) digital alarm clock vhdl code alarm clock design of digital VHDL verilog code for adc ADC Verilog Implementation alarm clock design of digital verilog alarm clock verilog hdl digital alarm clock vhdl code in modelsim xilinx vhdl code for digital clock UG192 alarm clock verilog code
2001 - XAPP029

Abstract: verilog rtl code of Crossbar Switch adc controller vhdl code XAPP172 Insight Spartan-II demo board 12-bit ADC interface vhdl code for FPGA vhdl code for pn sequence generator XAPP014 verilog code for cdma transmitter ADC DAC Verilog 2 bit Implementation
Text: FIFOs using the Block SelectRAM+ memory in the Spartan-II FPGAs. Verilog and VHDL code is available for , Verilog or VHDL code . A hand-placed version of the design runs at 170 MHz in the -6 speed grade. XAPP132 , that developers will find helpful for both code creation and hardware development. Examples of hardware code (VHDL or Verilog ) as well as "C" code are provided to augment the development of Handspring , The design strategies for loadable and non-loadable binary counters are significantly different. This


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PDF Q4-01 XAPP004 XAPP005 XC3000 Desi49 XC18V00, XC9500XL, XC9500XV, XAPP501 XC9500, XAPP029 verilog rtl code of Crossbar Switch adc controller vhdl code XAPP172 Insight Spartan-II demo board 12-bit ADC interface vhdl code for FPGA vhdl code for pn sequence generator XAPP014 verilog code for cdma transmitter ADC DAC Verilog 2 bit Implementation
2009 - verilog code for adc

Abstract: block diagram of ct scanner sdi verilog code analog to digital converter verilog 080450 OR127 ADAS1128
Text: Verilog code GENERAL DESCRIPTION The ADAS1128 is a 128-channel, current-to-digital, analog-todigital converter ( ADC ). It contains 128 low power, low noise, low input current integrators, simultaneous , 128-Channel, 24-Bit Current-to-Digital ADC ADAS1128 FEATURES 128-channel, low level , reduces external hardware. An SPI-compatible serial interface allows configuration of the ADC using the , × 10 mm, mini-BGA package. For more information on the ADAS1128, contact Analog Devices, Inc, at


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PDF 128-Channel, 24-Bit ADAS1128 2500e] ADAS1128 D08045F-0-6/09 verilog code for adc block diagram of ct scanner sdi verilog code analog to digital converter verilog 080450 OR127
2009 - block diagram of ct scanner

Abstract: ADAS1128 Wire diagram of ct scanner verilog code for adc digital to analog converter radiation ct scanner daisy chain verilog fpga radiation adc verilog sdi verilog code
Text: board Reference design with reference layout FPGA Verilog code The ADAS1128 is a 128-channel, current-to-digital, analog-todigital converter ( ADC ). It contains 128 low power, low noise, low input current , 128-Channel, 24-Bit Current-to-Digital ADC ADAS1128 FEATURES GENERAL DESCRIPTION 128 , configuration of the ADC using the SDI input. The SDO output allows the user to daisy-chain several ADCs on a , believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use


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PDF 128-Channel, 24-Bit ADAS1128 2500e-] ADAS1128 D08045F-0-9/10 block diagram of ct scanner Wire diagram of ct scanner verilog code for adc digital to analog converter radiation ct scanner daisy chain verilog fpga radiation adc verilog sdi verilog code
2010 - block diagram of ct scanner

Abstract: ADAS1126
Text: board Reference design with reference layout FPGA Verilog code The ADAS1126 is a 32-channel, current-to-digital, analog-todigital converter ( ADC ). It contains 32 low power, low noise, low input current , 32-Channel, 24-Bit Current-to-Digital ADC ADAS1126 FEATURES GENERAL DESCRIPTION 32 , configuration of the ADC using the SDI input. The SDO output allows the user to daisy-chain several ADCs on a , is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of


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PDF 32-Channel, 24-Bit ADAS1126 2500eâ ADAS1126 D08786F-0-3/11 block diagram of ct scanner
2010 - block diagram of ct scanner

Abstract: ADAS1126 OR31 verilog code for adc adas sensor x-ray sdi verilog code AN31 ct scanner AN15
Text: board Reference design with reference layout FPGA Verilog code The ADAS1126 is a 32-channel, current-to-digital, analog-todigital converter ( ADC ). It contains 32 low power, low noise, low input current , 32-Channel, 24-Bit Current-to-Digital ADC ADAS1126 FEATURES GENERAL DESCRIPTION 32 , configuration of the ADC using the SDI input. The SDO output allows the user to daisy-chain several ADCs on a , . However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents


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PDF 32-Channel, 24-Bit ADAS1126 2500e-] ADAS1126 D08786F-0-9/10 block diagram of ct scanner OR31 verilog code for adc adas sensor x-ray sdi verilog code AN31 ct scanner AN15
2010 - block diagram of ct scanner

Abstract: Wire diagram of ct scanner ct scanner or31 sensor or31 verilog code for adc sdi converter digital to analog converter radiation fpga radiation adc verilog
Text: board Reference design with reference layout FPGA Verilog code The ADAS1127 is a 64-channel, current-to-digital, analog-todigital converter ( ADC ). It contains 64 low power, low noise, low input current , 64-Channel, 24-Bit Current-to-Digital ADC ADAS1127 FEATURES GENERAL DESCRIPTION 64 , configuration of the ADC using the SDI input. The SDO output allows the user to daisy-chain several ADCs on a , accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any


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PDF 64-Channel, 24-Bit ADAS1127 2500e-] ADAS1127 D08785F-0-9/10 block diagram of ct scanner Wire diagram of ct scanner ct scanner or31 sensor or31 verilog code for adc sdi converter digital to analog converter radiation fpga radiation adc verilog
1999 - vhdl program for parallel to serial converter

Abstract: No abstract text available
Text: code : ◊ VHDL Source Code or/and VERILOG Source Code or/and ◊ Encrypted, or plain text EDIF â , available to conserve additional power. These modes make the D68HC11F1 IP Core especially attractive for , the exact configuration to meet users’ requirements. There is no need to pay extra for not used , —Š 17 priority levels ◊ Dedicated vector for each interrupt ♦ Main16-bit timer/counter system â , ADC converter controller (option) ♦ EEPROMCTRL – External EEPROM controller (option) All


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PDF D68HC11F D68HC11F1 D68HC11F1 16-bit, D6802 D6803 D6809 DF6805 D68HC05 vhdl program for parallel to serial converter
1999 - D6802

Abstract: MC68HC11KS2 generating pwm verilog code DF6811E multi channel UART controller using VHDL ADC Verilog Implementation D6803 verilog code for eeprom i2c controller MC68HC11K D68HC11
Text: select DELIVERABLES Source code : VHDL/ VERILOG Source Code or/and Encrypted, or plain text EDIF , are two formats of delivered IP Core VHDL, Verilog RTL synthesizable source code called HDL Source , attractive for automotive and battery-driven applications. The D68HC11K has built in real time hardware on , extra for not used features and wasted silicon. It includes fully automated testbench with complete , Microcontroller Core can be used as direct replacement for any of the following HC11 Microcontrollers


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PDF D68HC11K D68HC11K 16-bit, D6802 D6803 D6809 DF6805 D68HC05 D6802 MC68HC11KS2 generating pwm verilog code DF6811E multi channel UART controller using VHDL ADC Verilog Implementation D6803 verilog code for eeprom i2c controller MC68HC11K D68HC11
1999 - verilog program to generate PWM pulses

Abstract: 8-bit ADC interface vhdl complete code for FPGA adc controller vhdl code D6802 generating pwm verilog code DF6811E vhdl code for parallel to serial converter interface of ADC to UART in VHDL vhdl code for accumulator motorola 68hc11e
Text: : VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF VHDL & VERILOG test , delivered IP Core VHDL, Verilog RTL synthesizable source code called HDL Source FPGA EDIF/NGO/NGD/QXP , especially attractive for automotive and battery-driven applications. The D68HC11E has built in real time , need to pay extra for not used features and wasted silicon. It includes fully automated testbench with , sources 17 priority levels Dedicated vector for each interrupt Main16-bit timer/counter system 16


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PDF D68HC11E D68HC11E 68HC11E 16-bit, cir64k D6802 D6803 D6809 DF6805 verilog program to generate PWM pulses 8-bit ADC interface vhdl complete code for FPGA adc controller vhdl code D6802 generating pwm verilog code DF6811E vhdl code for parallel to serial converter interface of ADC to UART in VHDL vhdl code for accumulator motorola 68hc11e
2006 - verilog code voltage regulator

Abstract: CORE8051 vhdl code for 16 BIT BINARY DIVIDER ADC rtl code scaler verilog code verilog code for apb adc verilog APB VHDL code microcontroller using vhdl verilog code for adc
Text: CoreAI. Fully RTL Version ­ Verilog and VHDL Core Source Code ­ · General Description , can be configured using toplevel parameters ( Verilog ) or generics (VHDL). For a detailed description , generics (VHDL), described in Table 4, for configuring the RTL code . All parameters and generics are , internal data FIFO for storing up to 256 ADC conversion results for later reading by a microprocessor, or , Fusion datasheet for further information.) Table 15 · ADC Control Register 1 (high-order) Bits


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PDF 16-Bit verilog code voltage regulator CORE8051 vhdl code for 16 BIT BINARY DIVIDER ADC rtl code scaler verilog code verilog code for apb adc verilog APB VHDL code microcontroller using vhdl verilog code for adc
1995 - verilog code for 4 bit ripple COUNTER

Abstract: 8-bit ADC interface vhdl complete code for FPGA generating pwm verilog code D Flip Flops timer counters using jk flip flops vhdl code for 4 bit ripple COUNTER verilog HDL program to generate PWM verilog code for 8 bit shift register MSM65524 verilog code for adc
Text: Verilog netlist to the customer for post-layout simulation. Once design and post-layout simulation is , , lower power consumption relative to throughput, and greater flexibility and reliability. For code , required. The following table indicates the cells available for both Cadence Concept and Verilog systems , SOFTWARE DEVELOPMENT SUPPORT OKI provides software development support for assembly code development, C , trademarks, and Cadence and Verilog are registered trademarks of Cadence Design Systems, Inc. Design


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2010 - Not Available

Abstract: No abstract text available
Text: the ADC . 1 The asynchronous clock enable signal for the clk signal. This signal turns on/off , relying on any published information and before placing orders for products or services. Document last updated for Altera Complete Design Suite version: Document publication date: 10.0 September 2010 , measurement feature in the FPGA. The TSD block includes an 8-bit analog to digital converter ( ADC ), a clock , ALTTEMP_SENSE megafunction provides the following features: An internal TSD with built-in 8-bit ADC


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PDF UG-01074-3
2000 - Flash-ADC

Abstract: verilog code for adc simple ADC Verilog code 4bit CMOS devider 3bit flash adc 4-bit flash adc AL1208
Text: fed to the last 3-bit flash ADC decides final 3-bit digital digital code . 3. AL1208H has the error , 4. Verilog Modeling - Verilog modeling needs 64bits for only one analog real signal. SEC ASIC , AL1208H 10BIT 20MSPS ADC 10BIT 20MSPS ADC AL1208H GENERAL DESCRIPTION FEATURES The AL1208H is a CMOS 10-bit A/D converter for video applications. It is a three-step pipelined A/D converter which consists of sample & hold, three multiplying DACs, a 4-bit flash adc and three 3-bit flash


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PDF AL1208H 10BIT 20MSPS AL1208H 10-bit 20MSPS Flash-ADC verilog code for adc simple ADC Verilog code 4bit CMOS devider 3bit flash adc 4-bit flash adc AL1208
simple ADC Verilog code

Abstract: 4-bit flash adc verilog code for adc Flash-ADC 10-bit Flash-ADC adc 4bit analog to digital converter verilog BW1217X
Text: be higher than 66dB at least for less than 1/2LSB of SAH error voltage at 10bit ADC and its , 64bits for only one analog real signal. 12 0.35µm 10-BIT 30MSPS ADC µ BW1217X FEEDBACK , 0.35µm 10-BIT 30MSPS ADC µ BW1217X GENERAL DESCRIPTION The bw1217x is a CMOS 10-bit A/D converter for video applications. It is a three-step pipelined A/D converter which consists of sample & , °C 1 0.35µm 10-BIT 30MSPS ADC µ BW1217X FUNCTIONAL BLOCK DIAGRAM VDDA AINT AINC SHA


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PDF 10-BIT 30MSPS BW1217X bw1217x 10Bit simple ADC Verilog code 4-bit flash adc verilog code for adc Flash-ADC 10-bit Flash-ADC adc 4bit analog to digital converter verilog
2000 - adc 12bit 5msps

Abstract: BL1208H
Text: least for less than 1/2LSB of SAH error voltage at 10bit ADC and its conversion frequency is 5MHz, its , BL1208H 10BIT 5MSPS ADC 10BIT 5MSPS ADC BL1208H GENERAL DESCRIPTION FEATURES The BL1208H is a CMOS 10-bit A/D converter for video applications. It is a three-step pipelined A/D converter which consists of sample & hold, three multiplying DACs, a 4-bit flash adc and three 3-bit flash , STCB EOC DO[9:0] OVF UDF CKIN Ver 1.1 (Feb. 2000) No responsibility is assumed by SEC for


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PDF BL1208H 10BIT BL1208H 10-bit 10Bit 100mW adc 12bit 5msps
2000 - verilog code for adc

Abstract: CL1208H simple ADC Verilog code cl1208 verilog adc pipeline
Text: multiplying DAC is fed to the last 3-bit flash ADC decides final 3-bit digital digital code . 2. FLASH , for less than 1/2LSB of SAH error voltage at 10bit ADC and its conversion frequency is 20MHz, its , CL1208H 10BIT 10MSPS ADC 10BIT 10MSPS ADC CL1208H GENERAL DESCRIPTION FEATURES The CL1208H is a CMOS 10-bit A/D converter for video applications. It is a three-step pipelined A/D converter which consists of sample & hold, three multiplying DACs, a 4-bit flash adc and three 3-bit flash


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PDF CL1208H 10BIT 10MSPS CL1208H 10-bit 10MSPS verilog code for adc simple ADC Verilog code cl1208 verilog adc pipeline
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