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verilog code for 8 bit shift register Datasheets Context Search

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2001 - vhdl code for shift register using d flipflop

Abstract:
Text: Initialization in VHDL and Verilog Code A shift register can be initialized in VHDL or Verilog code for both synthesis and simulation. For synthesis, the attribute is attached to the 16- bit shift register , register is needed. Each CLB resource can be configured using the 8 LUTs as a 128- bit shift register . This section provides generic VHDL and Verilog submodules and reference code examples for implementing from 16- bit , provided in VHDL and Verilog code . Table 2-20 lists available submodules. Table 2-20: Shift Register


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PDF 16-bit 128-bit SRLC16E) SRLC16E h0000; vhdl code for shift register using d flipflop verilog code for 8 bit shift register verilog code for 64 32 bit register verilog code for shift register vhdl code for 8 bit shift register VHDL of 4-BIT LEFT SHIFT REGISTER verilog code for 8 bit register vhdl code for 128 bit register verilog code for 4 bit shift register SRL16
2005 - vhdl code 16 bit LFSR

Abstract:
Text: for the look-up tables where they are used as 16- bit shift registers. Using this Shift Register LUT , as the output, emulating an 8-bit shift register . Note that since the address lines control the mux , Primitive Initialization in VHDL and Verilog Code A shift register can be initialized in VHDL or Verilog , provided in VHDL and Verilog code . Table 2 lists available submodules. Table 2: Shift Register Submodules , _16 is the template for the 16- bit shift register ) and the "C" extension means the template is


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PDF SRL16) XAPP465 SRL16 16-bit vhdl code 16 bit LFSR verilog code 16 bit LFSR VHDL 32-bit pn sequence generator vhdl code for 32 bit pn sequence generator vhdl code for shift register using d flipflop vhdl code for pn sequence generator fpga cdma by vhdl examples vhdl code 16 bit LFSR with VHDL simulation output vhdl code for 8 bit shift register
1991 - verilog code for 16 bit carry select adder

Abstract:
Text: Verilog Code . 2-51 8-bit , Verilog Code . 2-57 8-bit , Verilog Code . 2-58 8-bit , . 2-33 Verilog Code . 2-34 4- bit , . 2-35 Verilog Code . 2-36 4- bit


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PDF XC2064, XC3090, XC4005, XC5210, XC-DS501 verilog code for 16 bit carry select adder X8978 8 bit carry select adder verilog codes verilog code of 8 bit comparator SR-4X UNSIGNED SERIAL DIVIDER using verilog verilog code for johnson counter verilog code for half subtractor ieee vhdl asm chart
2002 - verilog code for 64 32 bit register

Abstract:
Text: resource can be configured using the 8 LUTs as a 128- bit shift register . This section provides generic VHDL and Verilog submodules and reference code examples for implementing from 16- bit up to 128- bit shift , shift register can be initialized in VHDL or Verilog code for both synthesis and simulation. For , Verilog code . Table 2-29 lists available submodules. Table 2-29: Shift Register Submodules Length 32 bits , attributes. The V2_SRL16E shift register instantiation code examples (in VHDL and Verilog ) illustrate these


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PDF RAM16X1S h0000; RAM16X1S SRLC16E SRLC16E UG012 verilog code for 64 32 bit register verilog code for 8 bit shift register verilog code for 8 bit fifo register vhdl code for 8 bit shift register vhdl code for 4 bit shift register vhdl code for shift register using d flipflop vhdl code for 8 bit register SRLC32E VHDL of 4-BIT LEFT SHIFT REGISTER SRLC64E
1997 - design of UART by using verilog

Abstract:
Text: FLAG & SIGNAL DESCRIPTION 8 bit "transmit hold register " used to hold the contents of the data bus, when new data is written to the module. 8 bit "transmit shift register ", used for shifting out the , that has been received at the rx input. 8 bit "receive shift register ", used for shifting in the , single 8 bit bi-directional CPU interface. Address mapping for the transmitter and receiver channels can , loaded into the "transmit shift register ", and the "transmit hold register " again is ready for new data


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PDF QAN20 QL12x16B-2PL68C QL2007-2PL84C design of UART by using verilog verilog code for UART baud rate generator verilog code for uart verilog code for serial transmitter QL2007-2PL84C QAN20 uart verilog code uart verilog MODEL verilog hdl code for uart UART DESIGN
2002 - vhdl code for rs232 receiver

Abstract:
Text: This application note provides a functional description of VHDL and Verilog source code for a UART , discussed. To obtain the VHDL (or Verilog ) source code described in this document, go to section VHDL (or Verilog ) Code Download, page 3 for instructions. Introduction The Universal Asynchronous Receiver , communication over serial communication links as RS232. The reference VHDL and Verilog code implements a UART , ] while data is shifted in serially into the receiver shift register rsr[7:0]. This provides the


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PDF XAPP341 XC95144, XCR3128XL, XC2C128 RS232. XAPP341 XCR3128 XCR3128XL vhdl code for rs232 receiver xilinx uart verilog code interface of rs232 to UART in VHDL vhdl code for uart communication vhdl code for serial transmitter vhdl code 16 bit microprocessor uart verilog code verilog code for serial transmitter verilog code for 8 bit shift register parallel to serial conversion vhdl
2000 - vhdl code for rs232 receiver

Abstract:
Text: This application note provides a functional description of VHDL and Verilog source code for a UART , discussed. To obtain the VHDL (or Verilog ) source code described in this document, go to section "VHDL (or Verilog ) Code Download" on page 3 for instructions. Introduction The Universal Asynchronous Receiver , communication over serial communication links as RS232. The reference VHDL and Verilog code implements a UART , shifted in serially into the receiver shift register rsr[7:0]. This provides the controller flexibility


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PDF XAPP341 XC95144 XCR3128XL RS232. XAPP341 XCR3128 vhdl code for rs232 receiver verilog code for uart communication vhdl code for uart communication xilinx uart verilog code uart verilog code verilog code for serial transmitter interface of rs232 to UART in VHDL 16 bit register vhdl vhdl code for serial transmitter UART using VHDL
2000 - xilinx uart verilog code

Abstract:
Text: This application note provides a functional description of VHDL and Verilog source code for a UART , . To obtain the VHDL (or Verilog ) source code described in this document, go to section "VHDL (or Verilog ) Code Download" on page 3 for instructions. Introduction The Universal Asynchronous Receiver , communication over serial communication links as RS232. The reference VHDL and Verilog code implements a UART , shifted in serially into the receiver shift register rsr[7:0]. This provides the controller flexibility


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PDF XAPP341 XC95144 XCR3128 RS232. XAPP341 xilinx uart verilog code vhdl code for rs232 receiver vhdl code for uart communication vhdl code for shift register 16 bit register vhdl vhdl code for serial transmitter vhdl code for rs232 interface uart verilog code vhdl code for 8 bit shift register UART using VHDL
verilog code for cdma transmitter

Abstract:
Text: "short code ", 15- bit PN maximal length shift registers. A one-half chip delay, equal to (813.8ns / 2) or , implementation. The Walsh generator Verilog code also illustrates several key points for reliable design. In the , and interleaving functions. A Walsh code generator. A 42- bit long PN (pseudonoise) generator of , source, a 7- bit maximal PN generator was used. The 42- bit long code was implemented as a 31- bit long PN, maximal length shift register . This step was taken to preserve registers in the CPLD and to make design


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PDF 9152MHz CY37256 com/an918 MAX2361: AN918, APP918, Appnote918, verilog code for cdma transmitter verilog code for matrix inversion 15-bit* pn sequence digital mixer verilog code code for pn generator in digital PN generator circuit 4 bit pn sequence generator verilog code cdma pn sequence generator verilog code digital radio verilog code
1993 - 16 word 8 bit ram using vhdl

Abstract:
Text: MHz data rate using the DDR mode with a 72- bit wide bus. Fully synthesizable Verilog /VHDL code is , synthesizable code for configuring FIFOs of any desired width and depth. Fully synthesizable Verilog /VHDL code , generating the FULL and EMPTY control flags. Fully synthesizable Verilog /VHDL code is available for the , parameterizable Verilog and VHDL code to cascade several block RAMs configured as 32 x 8 CAM. CAM speed is , techniques. Fully synthesizable Verilog /VHDL code is available for the reference design. XAPP261


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PDF XAPP252: GS8170DxxB-333 XAPP268: UG002 16 word 8 bit ram using vhdl vhdl code for phase shift verilog code for 16 bit ram vhdl code for memory in cam ternary content addressable memory VHDL verilog code for 16 bit shifter verilog code for 16 bit common bus 8 bit ram using vhdl vhdl code for Digital DLL vhdl code for clock phase shift
2002 - vhdl code direct digital synthesizer

Abstract:
Text: for at least the hold time of the register . 19 AN 238: Using Quartus II Verilog HDL & VHDL , page 8 for details. 22 Altera Corporation AN 238: Using Quartus II Verilog HDL & VHDL , for the best logic optimization. Figure 8 shows sample VHDL code that prevents an unintentional latch , of the sel inputs. When targeting the code in Figure 8 for a StratixTM device, omitting the final , methodologies Following Altera-recommended guidelines for writing HDL code Following guidelines for using


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2005 - KEYPAD 4 X 4 verilog

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Text: the keypad rows, a barrel shift register is initialized with all ones except for one bit preset to a zero. Each bit of the shift register drives a CPLD output pin that is connected to a row of the keypad , Verilog source code for a keypad scanner. The code is used to target the lowest density, 32 , disable the shift register for how ever long the key is pressed. At this point the shift register is , encoders are used, one for the row bits (outputs of the shift register ), and another for the column inputs


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PDF XAPP512 32-macrocell XC2C32A QFG32 KEYPAD 4 X 4 verilog KEYPAD 4 X 3 verilog source code verilog code for keypad scanner KEYPAD verilog Code keypad in verilog verilog code for barrel shifter verilog code for 64 bit barrel shifter verilog code 16 bit processor verilog code for 16 bit barrel shifter circuit diagram of keypad interface with dtmf
2002 - verilog code for 16 bit ram

Abstract:
Text: resource can be configured using the 8 LUTs as a 128- bit shift register . This section provides generic VHDL and Verilog submodules and reference code examples for implementing from 16- bit up to 128- bit shift , Table 2-25, wider library primitives are available for 2- bit , 4- bit , and 8-bit RAM. Table 2-25 , structures can be initialized in VHDL or Verilog code for both synthesis and simulation. For synthesis, the , SelectRAM_32D - SelectRAM_64D Templates for the SelectRAM_16S module are provided in VHDL and Verilog code


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PDF 128-bit 16-bit UG012 verilog code for 16 bit ram verilog code for 64 32 bit register RAM64X1D vhdl code for 4 bit ram vhdl codes examples vhdl code for 8 bit ram RAM32X8S RAM16X8S RAM16X1S 8 bit ram using vhdl
2007 - verilog code for 4-bit alu with test bench

Abstract:
Text: .100 11.3.7.2 8-Bit Working Register 11.3.7.3 16- bit Working Register Address Space .101 11.3.7.4 16- bit Working Register Address Limitation .101 , to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of , license under patent or other rights. Cypress products are not warranted nor intended to be used for


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2001 - crc verilog code 16 bit

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Text: here to replicate the shift operation of the "32- bit CRC" register . The " 8-bit CRC Out" register , application note provides Verilog point solutions for CRC- 8 , CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC , next-state equations for CRC-32 registers. Included with this application note is Verilog source code for , generates equations for any CRC width, data input width, and polynomial, G(x). The Verilog code is included


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PDF XAPP209 CRC-12, CRC-16, CRC-32, CRC-32. geG256 crc verilog code 16 bit CRC-16 and CRC-32 Ethernet verilog code CRC8 CRC-32 LFSR crc 16 verilog 802.3 CRC32 cyclic redundancy check verilog source CRC-16 and CRC-32 verilog code 8 bit LFSR cyclic redundancy check
1998 - verilog code for adc

Abstract:
Text: - File ADCtop.v" on page 8 which shows an example of top-level Verilog code for the ADC 2.00 , resistors and capacitors. An 8-bit ADC can be implemented in about 16 Virtex CLBs, and a 10- bit ADC requires , middle of the voltage range. For each complete sample, only the upper bit of the DAC input is initially , . This process continues for each bit of the DAC input. The DAC is one bit wider than the ADC output. This is required in order for the lowest numbered bit of the ADC output to be significant. When all


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PDF XAPP155 10-bit CLK90( CLK180( CLK270( verilog code for adc verilog code of 8 bit comparator ADC Verilog Implementation ADC DAC Verilog 2 bit Implementation verilog code of 16 bit comparator adc verilog analog to digital converter verilog verilog code of 4 bit comparator verilog code of 3 bit comparator verilog code for serial multiplier
2009 - 8086 vhdl

Abstract:
Text: optimize your HDL code for the Actel architecture. Examples in both VHDL and Verilog code are provided to , writing Verilog or VHDL code . Additionally, Verilog and VHDL have reserved words that cannot be used for , synthesis tools do not typically support the don't care value as well as Verilog tools. Verilog // 8 bit 4 , device, you must become familiar with the architecture of the device and then code your design for that architecture. Efficient, standard HDL code is essential for creating good designs. The structure of the design


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2001 - Not Available

Abstract:
Text: code . Additionally, Verilog and VHDL have reserved words that cannot be used for signal or entity names , value as well as Verilog tools. Verilog // 8 bit 4:1 multiplexor with don't care X, 3:1 equivalent mux , then code your design for that architecture. Efficient, standard HDL code is essential for creating , material with instructions to optimize your HDL code for the Actel architecture. Examples in both VHDL and Verilog code are provided to illustrate these coding styles and to help implement the code into your


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1991 - verilog hdl code for parity generator

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Text: Syntax" chapter for unsupported Verilog constructs. Register Selection The placement of registers , Chapter 8 , "Writing Circuit Descriptions" describes how to write a Verilog description to ensure an , System Reference Guide for more information. Verilog Reference Guide vii Verilog Reference , constructs. For exceptions, see the "Unsupported Verilog Language Constructs" section of the " Verilog , simulator. 2. Write Verilog language test drivers for the Verilog HDL simulator. The drivers supply


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PDF XC2064, XC3090, XC4005, XC5210, XC-DS501 verilog hdl code for parity generator verilog code for half adder using behavioral modeling verilog code mealy for vending machine drinks vending machine circuit verilog disadvantages SR flip flop using discrete gates vending machine hdl vending machine xilinx schematic verilog hdl code for encoder system verilog
2006 - verilog code for 8 bit shift register

Abstract:
Text: . 2­9 Design Example: Configurable 8-Bit SIPO or PISO Shift Register , . 2­10 Generate a Configurable 8-Bit SIPO or PISO Shift Register . 2­10 Implement the Configurable 8-Bit SIPO or PISO Shift Register . 2­15 Functional Results - Simulate the 8-Bit Shift Register in Quartus II . 2­17 Functional Results - Simulate the 8-Bit Shift Register in ModelSim-Altera


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2000 - verilog code 16 bit LFSR

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Text: using the SRL16 ( Shift Register Look-Up Table) primitive for area-efficient designs. The first LFSR , , and Spartan-II architectures, a four-input LUT can also function as a 16- bit shift register with a single output accessed by the LUT's address lines. This 16- bit shift register function can be accessed , it repeats. For a shift register of fixed length N, the number and duration of the sequences it can , maximal length sequence for a shift register of length N is referred to as an m-sequence, and is defined


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PDF XAPP220 XAPP211) XAPP217) SRL16 41-stage, 41-stage SRL16s. verilog code 16 bit LFSR vhdl code 16 bit LFSR verilog code 8 bit LFSR vhdl code 8 bit LFSR simple LFSR 8 shift register by using D flip-flop verilog hdl code for parity generator vhdl code Pseudorandom Streams Generator SRL16 VHDL 32-bit pn sequence generator
2002 - 32x32 multiplier verilog code

Abstract:
Text: loopback test modes. Bit 1 is for serial loopback and bit 0 is for internal parallel loopback. Shuts down , bit of the 10- bit encoded TXDATA bus for each byte specified by the byte-mapping section. If 8B/10B , [15: 8 } byte or RXDATA [7:0] byte in the transceivers internal data path. True: Aligns comma with 20- bit , /10B translation. MCOMMA_10B_VALUE This 10- bit vector defines minus-comma for the purpose of raising , RXCOMMADET when minus-comma is detected. This 10- bit vector defines plus-comma for the purpose of raising


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PDF UG012 32x32 multiplier verilog code 4x4 unsigned multiplier VERILOG coding vhdl code for lvds driver 12v relay interface with cpld in vhdl MULT18X18 verilog/verilog code for lvds driver 80C31 instruction set book national semiconductor vhdl pulse interval encoder DO-DI-ADPCM64
1999 - vhdl code for spi controller implementation on

Abstract:
Text: second data pin. Another way to view this transfer is that an 8-bit shift register in the master and another 8-bit shift register in the slave are connected as a circular 16- bit shift register . When a transfer occurs, this distributed shift register is shifted eight bit positions; thus, the characters in , output Slave select outputs 8-Bit Shift Register LSB mi si Read Data Buffer clk addr , license for DELIVERABLES Source code : VHDL Source Code or/and VERILOG


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1999 - verilog code for 8 bit shift register

Abstract:
Text: second data pin. Another way to view this transfer is that an 8-bit shift register in the master and another 8-bit shift register in the slave are connected as a circular 16- bit shift register . When a transfer occurs, this distributed shift register is shifted eight bit positions; thus, the characters in , DESCRIPTION clk 8-Bit Shift Register addr(1:0) input Processor address lines cs input , . Single Design license for DELIVERABLES Ø Source code : ¨ VHDL Source Code or/and ¨ VERILOG


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2010 - verilog code for correlator

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Text: programmable logic designs. Synthesis tools optimize HDL code for both logic utilization and performance , Variation Wrapper File-Megafunction wrapper file for instantiation in a Verilog HDL design. Code f 6­5 For , instantiate the megafunction directly in your Verilog HDL, VHDL, or AHDL code by calling the megafunction and , Code " on page 6­7 f For synthesis tool features and options, refer to your synthesis tool


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PDF QII51007-10 verilog code for correlator vhdl code for complex multiplication and addition vhdl code for accumulator vhdl code CRC vhdl code of carry save multiplier vhdl code for lvds driver verilog code for implementation of rom vhdl code for sr flipflop vhdl code for multiplexer 32 BIT BINARY advanced synthesis cookbook
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