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LTC4064EMSE#PBF Linear Technology LTC4064 - Monolithic Linear Charger for Back-Up Li-Ion Batteries; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTC4064EMSE Linear Technology LTC4064 - Monolithic Linear Charger for Back-Up Li-Ion Batteries; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTC4064EMSE#TR Linear Technology LTC4064 - Monolithic Linear Charger for Back-Up Li-Ion Batteries; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTC4064EMSE#TRPBF Linear Technology LTC4064 - Monolithic Linear Charger for Back-Up Li-Ion Batteries; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LT5568-2EUF#TRPBF Linear Technology LT5568-2 - GSM/EDGE Optimized, High Linearity Direct Quadrature Modulator; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
LT5568-2EUF#PBF Linear Technology LT5568-2 - GSM/EDGE Optimized, High Linearity Direct Quadrature Modulator; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C

verilog code for 2D linear convolution Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1997 - verilog code for 2D linear convolution

Abstract: verilog code for GPS correlator vhdl code numeric controlled oscillator pipeline rx UART AHDL design verilog code car parking free verilog code of median filter verilog code for 2D linear convolution filtering verilog code for median filter LED Dot Matrix vhdl code 16 QAM modulation verilog code
Text: File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL instantiation templates Megafunction , trademark laws. Altera Corporation acknowledges the trademarks of other organizations for their respective , . Verilog and Cadence are registered trademarks of Cadence Design Systems, Inc. SCVL, SCVL-S, MOR , for a particular purpose, or non-infringement of any patent, copyright, or their intellectual property rights. In the absence of written agreement to the contrary, Altera assumes no liability for Altera


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PDF M-CAT-AMPP-02 EPF10K10, EPF10K20, EPF10K30, EPF10K40, EPF10K50, EPF10K70, EPF10K100, EPF8282, EPF82828A, verilog code for 2D linear convolution verilog code for GPS correlator vhdl code numeric controlled oscillator pipeline rx UART AHDL design verilog code car parking free verilog code of median filter verilog code for 2D linear convolution filtering verilog code for median filter LED Dot Matrix vhdl code 16 QAM modulation verilog code
1997 - free vHDL code of median filter

Abstract: free verilog code of median filter verilog code for UART with BIST capability verilog code for 2D linear convolution verilog code for 2D linear convolution filtering rx UART AHDL design vhdl code direct digital synthesizer 8051 interface ppi 8255 verilog code for median filter vhdl median filter
Text: in MAX+PLUS II GDFs Include File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL , megafunction descriptions and partner profiles for each AMPP partner. The information in this catalog is current as of the print date, but megafunction specifications and availability are subject to change. For , applicable standards compliance, and a table with fitting and performance specifications. See page 11 for , Peripherals Telecommunications and Data Communications (Telecom & Datacom) DSP for Imaging DSP for


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1997 - verilog code for carry look ahead adder

Abstract: verilog code to generate sine wave verilog code for carry look ahead adder 32 verilog code for 8 bit carry look ahead adder verilog code of carry look ahead adder 8 bit carry look ahead verilog codes verilog code for 2D linear convolution verilog code of sine rom carry look ahead adder QAN19
Text: . In these designs, using a non-linear digital design eliminates the need for circuit board , frequency control makes DDS systems ideal for systems that require precise frequency sweeps such as radar , Phase Accumulator Sinusoidal ROM Sin Output Lookup (D-1:0) Table Optional phase adder for , of bits used to address the sinusoidal ROM table. For system designs that require amplitude , the value into an analog voltage and holds the value for one sample clock period. The time domain


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PDF QAN19 verilog code for carry look ahead adder verilog code to generate sine wave verilog code for carry look ahead adder 32 verilog code for 8 bit carry look ahead adder verilog code of carry look ahead adder 8 bit carry look ahead verilog codes verilog code for 2D linear convolution verilog code of sine rom carry look ahead adder QAN19
1997 - verilog code for carry look ahead adder

Abstract: verilog code for 8 bit carry look ahead adder verilog code to generate sine wave 8 bit carry look ahead verilog codes QAN19 carry look ahead adder verilog code for discrete linear convolution verilog code for 2D linear convolution verilog code of carry look ahead adder verilog code of sine rom
Text: . In these designs, using a non-linear digital design eliminates the need for circuit board , frequency control makes DDS systems ideal for systems that require precise frequency sweeps such as radar , Phase Accumulator Sinusoidal ROM Sin Output Lookup (D-1:0) Table Optional phase adder for , of bits used to address the sinusoidal ROM table. For system designs that require amplitude , the value into an analog voltage and holds the value for one sample clock period. The time domain


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PDF QAN19 verilog code for carry look ahead adder verilog code for 8 bit carry look ahead adder verilog code to generate sine wave 8 bit carry look ahead verilog codes QAN19 carry look ahead adder verilog code for discrete linear convolution verilog code for 2D linear convolution verilog code of carry look ahead adder verilog code of sine rom
2010 - Not Available

Abstract: No abstract text available
Text: : Introduction The 2D FIR Filter IP core performs real-time 2D convolution of windowed portions of incoming , interface. Quick Facts Table 1-1 through Table 1-4 give quick facts about the 2D FIR Filter IP core for LattceECP2, LatticeECP2M, LatticeECP3, and LatticeXP2 devices. Table 1-1. 2D FIR Filter Quick Facts for , Semiconductor Introduction Table 1-2. 2D FIR Filter Quick Facts for LatticeECP2M 2D FIR IP configurations , Simulation Mentor Graphics ModelSim SE 6.3F Table 1-3. 2D FIR Filter Quick Facts for LatticeECP3 2D


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PDF IPUG89 MULT18X18 LFXP2-40E-6F484C D-2010 03L-SP1
2011 - Not Available

Abstract: No abstract text available
Text: 2D Edge Detector IP core is provided for Aldec Active-HDL ( Verilog and VHDL) simulator, Mentor , target device. Table 3-1 provides the list of user configurable parameters for the 2D Edge Detector IP , . Getting Started The 2D Edge Detector IP core is available for download from the Lattice IP Server using , GUI dialog box shown in Figure 4-1. The IPexpress tool GUI dialog box for the 2D Edge Detector IP , Edge Detector IP for LatticeECP3 device. Figure 4-3. 2D Edge Detector IP Core Directory Structure


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PDF IPUG86 720x480 1280x720 LFXP2-40E-6F672Cdevice
1996 - VMIC reflective

Abstract: EPM7128Q altera flex10k EPM7160 Transition xilinx FPGA IIR Filter amd 9513 PL-BITBLASTER VMIPCI-5588 EPF10K20A EPM9560GC280
Text: migration product for MAX+PLUS II version 7.1 in December 1996. The ordering code for the library is , Optimized, Fixed-Coefficient 2-D Video Convolvers Video convolution involves transforming an image by , 82 (Highly Optimized 2-D Convolvers in FLEX Devices), which will be available in December 1996. For , convolution window is fixed. Figure 1. Sample Convolution Window Many convolution windows used for , - verilog The genmem utility will produce the file csdp_ram_64x8.v for simulation and the file csdp_ram


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PDF 104MHz FLEX10KA 16-tap VMIC reflective EPM7128Q altera flex10k EPM7160 Transition xilinx FPGA IIR Filter amd 9513 PL-BITBLASTER VMIPCI-5588 EPF10K20A EPM9560GC280
vhdl code dds

Abstract: chip dmd ti dlp PL84 vhdl code direct digital synthesizer QD-PQ208 QL16x24BL QAN19 sequential multiplier Vhdl dont let the sun go down on me QD-PF100144
Text: through a redesign and are the ideal silicon solution for Verilog or VHDL based designs. Stay tuned for , Verilog simulation. The purpose for including these articles is to give the designer already familiar , included with QuickWorks. By entering Verilog code , however, a designer can create stimulus that is much , /* characters, and end with the */ characters. The first line of Verilog code in the above example is a , the default module name for test fixtures automatically While knowledge of Verilog will be helpful


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PDF 208-pin QL2005 PB256 QL2003 QL2005 QP-PL44 QP-PL68 QP-CG68 QP-PF100 vhdl code dds chip dmd ti dlp PL84 vhdl code direct digital synthesizer QD-PQ208 QL16x24BL QAN19 sequential multiplier Vhdl dont let the sun go down on me QD-PF100144
2004 - verilog code hamming

Abstract: c1823.zip an1823 hamming code 512 bytes SLC nand hamming code 512 bytes flash hamming ecc STMicroelectronics NAND256W3A hamming 7 bit hamming code nand error correction
Text: bits called a code word. Convolution Codes, where the code words produced depend on both the , Code for ECC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , Code for ECC Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . 11 ECC HARDWARE CODE GENERATION AND CORRECTION - VERILOG , BLOCK CODES The Block Code family can be divided up into (see Figure 1.): Linear Codes, where


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PDF AN1823 Byte/1056 verilog code hamming c1823.zip an1823 hamming code 512 bytes SLC nand hamming code 512 bytes flash hamming ecc STMicroelectronics NAND256W3A hamming 7 bit hamming code nand error correction
2004 - c1823.zip

Abstract: verilog code hamming flash hamming ecc an1823 LP07 LP06 LP03 LP05 hamming code-error detection correction hamming code
Text: bits called a code word. s Convolution Codes, where the code words produced depend on both the , Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pseudo Code for , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pseudo Code for , . . . . . . . . . . . . . . . . . 10 ECC HARDWARE CODE GENERATION AND CORRECTION - VERILOG MODEL . , CODES The Block Code family can be divided up into (see Figure 1.): s Linear Codes, where every


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PDF AN1823 c1823 c1823.zip verilog code hamming flash hamming ecc an1823 LP07 LP06 LP03 LP05 hamming code-error detection correction hamming code
2006 - verilog code for discrete linear convolution

Abstract: verilog code for ultrasonic sensor with fpga verilog code for linear convolution by circular c image enhancement verilog code verilog code for linear convolution by circular adc matlab code vhdl code for Circular convolution iir filter butterworth verilog verilog code image processing filtering pressure sensor MATLAB program
Text: Co-Processors Altera Corporation To illustrate these issues, Figure 3 shows a C code fragment for a , processors running a set of pipelined assembly and C code . The DSP processor(s) would be responsible for the , Builder A parallel DMA module that operates at high speed designed in DSP Builder The C code for the , telecommunications (see Building Blocks for Rapid Communication System Development white paper). Digital signal , processor, this only allows for a few tens of thousands of instructions for the entire calculation. This


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2000 - XILINX vhdl code REED SOLOMON encoder decoder

Abstract: "Galois Field Multiplier" verilog Reed-Solomon Decoder verilog code XILINX vhdl code download REED SOLOMON encoder decoder XILINX vhdl code download REED SOLOMON vhdl code for 8-bit parity generator vhdl code for a 9 bit parity generator Reed-Solomon encoder encoder verilog coding viterbi convolution
Text: , Spartan, SpartanTM-II, VirtexTM, and VirtexTM-E devices · Programmable solution for high data rate , polynomial · Single encoder implementation supports any valid data block length · Systematic code structure where each code word can be partitioned into original data block and appended parity symbols · , VHDL, Verilog Instantiation Templates Reference Designs & Application Notes None Additional Items , FPGA-based core for systems where data error detection/correction is required. The core implements the full


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PDF 4000X, XILINX vhdl code REED SOLOMON encoder decoder "Galois Field Multiplier" verilog Reed-Solomon Decoder verilog code XILINX vhdl code download REED SOLOMON encoder decoder XILINX vhdl code download REED SOLOMON vhdl code for 8-bit parity generator vhdl code for a 9 bit parity generator Reed-Solomon encoder encoder verilog coding viterbi convolution
1999 - "Galois Field Multiplier" verilog

Abstract: XILINX vhdl code REED SOLOMON encoder decoder vhdl code for bit interleaver Reed-Solomon Decoder verilog code xilinx vhdl code for digital clock 4005XL viterbi convolution
Text: Features · · Programmable solution for high data rate ReedSolomon encoding ISS can configure to support a , data block length Systematic code structure where each code word can be partitioned into original data , Verification Test Vectors VHDL, Verilog Instantiation Templates Reference Designs & Application Notes None , encoder is a Xilinx FPGA-based core for systems where data error detection/correction is required. The , circuitry using a single Xilinx FPGA. The source code version of the core is extremely flexible due to its


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PDF 4000XL, "Galois Field Multiplier" verilog XILINX vhdl code REED SOLOMON encoder decoder vhdl code for bit interleaver Reed-Solomon Decoder verilog code xilinx vhdl code for digital clock 4005XL viterbi convolution
2008 - verilog code for image processing

Abstract: image processing verilog code image edge detection verilog code dct verilog code fpga frame buffer vhdl examples fpga based image processing for implementing edge detection in image using vhdl VHDL code DCT sample verilog code for memory read
Text: rigorous code coverage measurements. Deliverables The core includes everything required for successful implementation: VHDL or Verilog RTL source code Post-Synthesis EDIF (netlist release) Sophisticated , Does not insert extra idle cycles and compensates host stalls ­ perfect for video encoders , image transform context a well known example is the 2D -Discrete cosine transform ( 2D -DCT), especially the 8x8 block 2D -DCT, found among others in the MPEG video compression and in JPEG image compression


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1998 - lms algorithm using verilog code

Abstract: lms algorithm using vhdl code ATM machine working circuit diagram using vhdl verilog code for lms adaptive equalizer for audio verilog code for lms adaptive equalizer digital IIR Filter VHDL code 8086 microprocessor based project verilog DTMF decoder qpsk demodulation VHDL CODE verilog code for fir filter using DA
Text: Verilog HDL files are available from most partners, a source code license is usually more expensive than a , directly for an authorization code ; the AMPP partner will generate this code based on your MAX+PLUS II PC , File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL instantiation templates Megafunction , printing date, but megafunction specifications and availability are subject to change. For the most current , Data Communication (Telecom and Datacom) Digital Signal Processing (DSP) For additional details on


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2008 - verilog code for image processing

Abstract: image processing verilog code dct algorithm verilog code fpga frame buffer vhdl examples image edge detection verilog code verilog code for pixel converter fpga based image processing for implementing dct verilog code pixel vhdl dct algorithm for verilog
Text: . Deliverables The core includes everything required for successful implementation: VHDL or Verilog RTL source code Post-Synthesis EDIF (netlist release) Sophisticated self-checking Testbench ( Verilog versions , transform context a well known example is the 2D -Discrete cosine transform ( 2D -DCT), especially the 8x8 block 2D -DCT, found among others in the MPEG video compression and in JPEG image compression. Streaming , Raster-to-Block converter core is designed to be the perfect standalone and on-the-fly conversion solution for


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1999 - Not Available

Abstract: No abstract text available
Text: complete Verilog or VHDL design and ends when the EDIF file is created using Exemplar Leonardo Spectrum. Tool Flow The following is a step-by-step flow for synthesis of a Verilog or VHDL design through Leonardo Spectrum. RTL VHDL and Verilog Leonardo Spectrum Synthesis Vantis Technology Library , Targeting MACH® Using Exemplar's Leonardo Spectrum v1998. 2d with DesignDirect-CPLD v1 , from a Verilog or VHDL design with a MACH device using Exemplar Leonardo Spectrum ver.1998.2d. The EDIF


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PDF v1998
1999 - Not Available

Abstract: No abstract text available
Text: complete Verilog or VHDL design and ends when the EDIF file is created using Exemplar Leonardo Spectrum. Tool Flow The following is a step-by-step flow for synthesis of a Verilog or VHDL design through , less. For example, bcd2led.edf. Targeting MACH Using Exemplar's Leonardo Spectrum v1998. 2d With , Targeting MACH® Using Exemplar's Leonardo Spectrum v1998. 2d with DesignDirect-CPLD v1 , from a Verilog or VHDL design with a MACH device using Exemplar Leonardo Spectrum ver.1998.2d. The


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PDF v1998
1999 - C371 FPGA

Abstract: No abstract text available
Text: fits into a Cypress PLD. Warp generates a file for device programming, and VHDL or Verilog timing models are generated for post-synthesis simulation. Figure 2. Loading the Cypress Library There are , and Leonardo Spectrum version v1998. 2d were used. Design Flow The Cypress Exemplar Logic design , Cypress will provide a choice of device families. Version v1998. 2d supports both the FLASH370iTM and the Ultra37000TM families. After choosing a family, a pull down menu will appear for selecting the specific part


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2008 - atmel 018

Abstract: image edge detection verilog code edge detection in image using vhdl grayscale verilog code
Text: and rigorous code coverage measurements. Deliverables The core includes everything required for successful implementation: VHDL or Verilog RTL source code Post-Synthesis EDIF (netlist release , , noise reduction filters etc. In the image transform context a well known example is the 2D -Discrete cosine transform ( 2D -DCT), especially the 8x8 block 2DDCT, found among others in the MPEG video , is designed to be the perfect standalone and on-the-fly conversion solution for the JPEG image


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1996 - 8251 intel microcontroller architecture

Abstract: 8251 usart vhdl source code for 8086 microprocessor verilog coding for asynchronous decade counter verilog code for 8254 timer verilog code for median filter 8251 uart vhdl verilog code for iir filter SERVICE MANUAL oki 32 lcd tv VHDL CODE FOR HDLC controller
Text: >.tdf), VHDL, Verilog HDL, or AHDL file Symbol File (.sym) for use in MAX+PLUS II , VHDL- or Verilog HDL-based design files that are optimized for the Altera FLEX 10K device family , RAM is used for program memory, application code can be loaded with a memory download mode , description of each AMPP megafunction, and a listing of corporate profiles and contact information for each , megafunctions. Some products listed in the AMPP partner profiles are available for non-Altera device


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2001 - vhdl code for Clock divider for FPGA

Abstract: cyclic redundancy check verilog source AT40K microcontroller using vhdl vhdl code CRC 32
Text: Syntactically correct Verilog or VHDL templates and HDL code from System Designer's macro generators simplify the development of HDL code for FPSLIC products. Benefits No Hand Coding of HDL Code ­ Designers , Verilog description. The synthesis tool will generate a gate-level netlist of the function for simulation , FPSLIC FPGA array. Benefits VHDL or Verilog Designs That Are Optimized for Atmel FPSLIC Architecture , Behavioral Designs ­ System Designer ensures that VHDL and Verilog designs are optimized for the FPSLIC


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1996 - AHDL adder subtractor

Abstract: EPF8452A EPF8820A parallel adder using VERILOG
Text: . The equation for this filter is: 8 y(n) = x ( n )h ( n ) n=1 For a linear phase response , , low-pass filtering, and video convolution functions. Only a limited selection of off-the-shelf FIR filter , devices (PLDs) are an ideal choice for implementing FIR filters. Altera FLEX devices, including the FLEX , filters. For example, you can use a FLEX device for one or more critical filtering functions in a DSP , addition for the vector multiplier shown in Figure 2 can be optimized by using look-up tables (LUTs) in a


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1996 - AHDL adder subtractor

Abstract: 3-bit binary multiplier using adder VERILOG 8 bit binary multiplier using adders
Text: ) = x(n)h(n) n=1 8 For a linear phase response FIR filter, the coefficients are symmetric , , low-pass filtering, and video convolution functions. Only a limited selection of off-the-shelf FIR filter , (PLDs) are an ideal choice for implementing FIR filters. Altera FLEX devices, including the FLEX 10K and FLEX 8000 families, are flexible, high-performance devices that can easily implement FIR filters. For example, you can use a FLEX device for one or more critical filtering functions in a DSP


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2000 - Exemplar

Abstract: No abstract text available
Text: a VHDL netlist, which then fits into a Cypress PLD. generates a file for device programming, and VHDL or Verilog timing models are generated for post-synthesis simulation. :DUS :DUS Figure 2 , : In this application note, Warp2® release 5.1 and Leonardo Spectrum version v1998. 2d were used , under the FPGAs heading. Selecting Cypress will provide a choice of device families. Version v1998. 2d , will appear for selecting the specific part. Finally, click on LOAD LIBRARY to complete the targeting


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