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Part Manufacturer Description Datasheet Download Buy Part
LTC1565-31IS8 Linear Technology LTC1565-31 - 650kHz Continuous Time, Linear Phase Lowpass Filter; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
LTC1069-7IS8 Linear Technology LTC1069-7 - Linear Phase 8th Order Lowpass Filter; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
LTC1064-7CSW#TRPBF Linear Technology LTC1064-7 - Linear Phase, 8th Order Lowpass Filter; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC1069-7CS8 Linear Technology LTC1069-7 - Linear Phase 8th Order Lowpass Filter; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LTC1565-31CS8 Linear Technology LTC1565-31 - 650kHz Continuous Time, Linear Phase Lowpass Filter; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LTC1565-31IS8#TR Linear Technology LTC1565-31 - 650kHz Continuous Time, Linear Phase Lowpass Filter; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C

verilog code for 2D linear convolution filtering Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2010 - Not Available

Abstract:
Text: : Introduction The 2D FIR Filter IP core performs real-time 2D convolution of windowed portions of incoming , interface. Quick Facts Table 1-1 through Table 1-4 give quick facts about the 2D FIR Filter IP core for LattceECP2, LatticeECP2M, LatticeECP3, and LatticeXP2 devices. Table 1-1. 2D FIR Filter Quick Facts for , Semiconductor Introduction Table 1-2. 2D FIR Filter Quick Facts for LatticeECP2M 2D FIR IP configurations , Simulation Mentor Graphics ModelSim SE 6.3F Table 1-3. 2D FIR Filter Quick Facts for LatticeECP3 2D


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PDF IPUG89 MULT18X18 LFXP2-40E-6F484C D-2010 03L-SP1
1997 - verilog code for 2D linear convolution

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Text: File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL instantiation templates Megafunction , trademark laws. Altera Corporation acknowledges the trademarks of other organizations for their respective , . Verilog and Cadence are registered trademarks of Cadence Design Systems, Inc. SCVL, SCVL-S, MOR , for a particular purpose, or non-infringement of any patent, copyright, or their intellectual property rights. In the absence of written agreement to the contrary, Altera assumes no liability for Altera


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PDF M-CAT-AMPP-02 EPF10K10, EPF10K20, EPF10K30, EPF10K40, EPF10K50, EPF10K70, EPF10K100, EPF8282, EPF82828A, verilog code for 2D linear convolution verilog code for GPS correlator vhdl code numeric controlled oscillator pipeline rx UART AHDL design verilog code car parking free verilog code of median filter verilog code for 2D linear convolution filtering verilog code for median filter LED Dot Matrix vhdl code 16 QAM modulation verilog code
1997 - free vHDL code of median filter

Abstract:
Text: in MAX+PLUS II GDFs Include File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL , megafunctions, with sample rates ranging from 2 kHz to over 75 MHz, are ideal for solving filtering problems , megafunction descriptions and partner profiles for each AMPP partner. The information in this catalog is current as of the print date, but megafunction specifications and availability are subject to change. For , applicable standards compliance, and a table with fitting and performance specifications. See page 11 for


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1996 - VMIC reflective

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Text: migration product for MAX+PLUS II version 7.1 in December 1996. The ordering code for the library is , Optimized, Fixed-Coefficient 2-D Video Convolvers Video convolution involves transforming an image by , 82 (Highly Optimized 2-D Convolvers in FLEX Devices), which will be available in December 1996. For , convolution window is fixed. Figure 1. Sample Convolution Window Many convolution windows used for , - verilog The genmem utility will produce the file csdp_ram_64x8.v for simulation and the file csdp_ram


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PDF 104MHz FLEX10KA 16-tap VMIC reflective EPM7128Q altera flex10k EPM7160 Transition amd 9513 xilinx FPGA IIR Filter PL-BITBLASTER VMIPCI-5588 EPF10K20A 304 QFP amkor
1996 - digital FIR Filter verilog code

Abstract:
Text: methods, including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL) Useful for a variety of applications, including high performance, realtime video and image filtering ; radio frequency (RF) filtering ; radar; magnetic resonance imaging (MRI) applications; multi-rate digital signal , because they can be customized for specialized applications by modifying the source code . In addition , , pipelining, and symmetry Optimized for FLEX 10K and FLEX 8000 devices Coefficients implemented as look-up


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PDF 64-tap digital FIR Filter verilog code verilog code for fir filter FIR Filter verilog code digital FIR Filter VHDL code verilog code for serial multiplier verilog code to generate chirp wave FIR FILTER implementation in c language convolution Filter verilog HDL code 3x3 bit parallel multiplier code fir filter in vhdl
1996 - verilog code for parallel fir filter

Abstract:
Text: methods, including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL) Useful for a variety of applications, including high performance, realtime video and image filtering ; radio frequency (RF) filtering ; radar; magnetic resonance imaging (MRI) applications; multi-rate digital signal , because they can be customized for specialized applications by modifying the source code . In addition , , pipelining, and symmetry Optimized for FLEX 10K and FLEX 8000 devices Coefficients implemented as look-up


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PDF 64-tap verilog code for parallel fir filter verilog code for serial multiplier convolution Filter verilog HDL code 8 tap fir filter vhdl FIR FILTER implementation in c language digital FIR Filter verilog HDL code FIR Filter verilog code design of FIR filter using lut multiplier vhdl a digital FIR Filter with verilog HDL code digital FIR Filter verilog code
1996 - AHDL adder subtractor

Abstract:
Text: , low-pass filtering , and video convolution functions. Only a limited selection of off-the-shelf FIR filter , filters. For example, you can use a FLEX device for one or more critical filtering functions in a DSP , . The equation for this filter is: 8 y(n) = x ( n )h ( n ) n=1 For a linear phase response , devices (PLDs) are an ideal choice for implementing FIR filters. Altera FLEX devices, including the FLEX , addition for the vector multiplier shown in Figure 2 can be optimized by using look-up tables (LUTs) in a


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1996 - AHDL adder subtractor

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Text: , low-pass filtering , and video convolution functions. Only a limited selection of off-the-shelf FIR filter , (PLDs) are an ideal choice for implementing FIR filters. Altera FLEX devices, including the FLEX 10K and FLEX 8000 families, are flexible, high-performance devices that can easily implement FIR filters. For example, you can use a FLEX device for one or more critical filtering functions in a DSP , ) = x(n)h(n) n=1 8 For a linear phase response FIR filter, the coefficients are symmetric


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2000 - verilog code for fir filter

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Text: _05_040400 Figure 5: Example Showing Filter Requirements for a Low Pass Filter As an exercise in FIR filtering , the , : Spartan-II Architecture A wide range of arithmetic functions for fast Fourier transforms (FFTs), convolution , are implemented using generalpurpose programmable DSP chips for low-rate applications. Alternatively, special-purpose, fixed function DSP chipsets and application-specific integrated circuits (ASICs) are used for , the past 15 years have opened new paths for DSP design engineers. The FPGA maintains the high


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PDF WP116 verilog code for fir filter FIR FILTER implementation xilinx verilog coding for fir filter digital FIR Filter verilog code digital FIR Filter VHDL code verilog code for discrete linear convolution verilog code for mpeg4 FIR Filter verilog code xilinx FPGA IIR Filter 8 tap fir filter verilog
2006 - verilog code for discrete linear convolution

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Text: Co-Processors Altera Corporation To illustrate these issues, Figure 3 shows a C code fragment for a , high data rate, real-time signal ( for example, bandpass filtering a noisy sensor signal), and displays , processors running a set of pipelined assembly and C code . The DSP processor(s) would be responsible for the , Builder A parallel DMA module that operates at high speed designed in DSP Builder The C code for the , telecommunications (see Building Blocks for Rapid Communication System Development white paper). Digital signal


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1997 - verilog code for carry look ahead adder

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Text: . In these designs, using a non-linear digital design eliminates the need for circuit board , frequency control makes DDS systems ideal for systems that require precise frequency sweeps such as radar , Phase Accumulator Sinusoidal ROM Sin Output Lookup (D-1:0) Table Optional phase adder for , of bits used to address the sinusoidal ROM table. For system designs that require amplitude , the value into an analog voltage and holds the value for one sample clock period. The time domain


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PDF QAN19 verilog code for carry look ahead adder verilog code to generate sine wave verilog code for carry look ahead adder 32 verilog code for 8 bit carry look ahead adder verilog code of carry look ahead adder 8 bit carry look ahead verilog codes verilog code for 2D linear convolution verilog code of sine rom QAN19 carry look ahead adder
1997 - verilog code for carry look ahead adder

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Text: . In these designs, using a non-linear digital design eliminates the need for circuit board , frequency control makes DDS systems ideal for systems that require precise frequency sweeps such as radar , Phase Accumulator Sinusoidal ROM Sin Output Lookup (D-1:0) Table Optional phase adder for , of bits used to address the sinusoidal ROM table. For system designs that require amplitude , the value into an analog voltage and holds the value for one sample clock period. The time domain


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PDF QAN19 verilog code for carry look ahead adder verilog code for 8 bit carry look ahead adder verilog code to generate sine wave 8 bit carry look ahead verilog codes QAN19 carry look ahead adder verilog code for discrete linear convolution verilog code for 2D linear convolution verilog code of sine rom QAM phase angle control magnitude
1998 - lms algorithm using verilog code

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Text: Verilog HDL files are available from most partners, a source code license is usually more expensive than a , directly for an authorization code ; the AMPP partner will generate this code based on your MAX+PLUS II PC , File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL instantiation templates Megafunction , printing date, but megafunction specifications and availability are subject to change. For the most current , Data Communication (Telecom and Datacom) Digital Signal Processing (DSP) For additional details on


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2011 - verilog code for interpolation filter

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Text: : Inferring Stratix V DSP Blocks for FIR Filtering Applications January 2011 Altera Corporation Verilog , for the DSP block implementation that the Quartus II software infers from this Verilog HDL code . Each multiplier-adder plus register is mapped to an 18 × 18 DSP block element. Example 1. Verilog HDL Code for , Stratix V DSP Blocks for FIR Filtering Applications January 2011 Altera Corporation Verilog HDL , Corporation AN639: Inferring Stratix V DSP Blocks for FIR Filtering Applications Page 24 Verilog HDL


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PDF AN639: AN-639-1 27-bit verilog code for interpolation filter VHDL code for polyphase decimation filter using D 16 bit Array multiplier code in VERILOG 32 bit adder vhdl code 8 tap fir filter verilog systolic multiplier and adder vhdl code verilog code for decimation filter verilog code for parallel fir filter vhdl code for 8-bit signed adder
2011 - Not Available

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Text: 2D Edge Detector IP core is provided for Aldec Active-HDL ( Verilog and VHDL) simulator, Mentor , target device. Table 3-1 provides the list of user configurable parameters for the 2D Edge Detector IP , . Getting Started The 2D Edge Detector IP core is available for download from the Lattice IP Server using , GUI dialog box shown in Figure 4-1. The IPexpress tool GUI dialog box for the 2D Edge Detector IP , Edge Detector IP for LatticeECP3 device. Figure 4-3. 2D Edge Detector IP Core Directory Structure


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PDF IPUG86 720x480 1280x720 LFXP2-40E-6F672Cdevice
vhdl code dds

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Text: through a redesign and are the ideal silicon solution for Verilog or VHDL based designs. Stay tuned for , Verilog simulation. The purpose for including these articles is to give the designer already familiar , included with QuickWorks. By entering Verilog code , however, a designer can create stimulus that is much , /* characters, and end with the */ characters. The first line of Verilog code in the above example is a , the default module name for test fixtures automatically While knowledge of Verilog will be helpful


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PDF 208-pin QL2005 PB256 QL2003 QL2005 QP-PL44 QP-PL68 QP-CG68 QP-PF100 vhdl code dds chip dmd ti dlp PL84 vhdl code direct digital synthesizer QD-PQ208 QL16x24BL QAN19 dont let the sun go down on me dlp mirror chip chip dmd ti
2004 - verilog code hamming

Abstract:
Text: bits called a code word. Convolution Codes, where the code words produced depend on both the , Code for ECC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , Code for ECC Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . 11 ECC HARDWARE CODE GENERATION AND CORRECTION - VERILOG , BLOCK CODES The Block Code family can be divided up into (see Figure 1.): Linear Codes, where


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PDF AN1823 Byte/1056 verilog code hamming c1823.zip an1823 hamming code 512 bytes SLC nand hamming code 512 bytes flash hamming ecc STMicroelectronics NAND256W3A 7 bit hamming code hamming error correction code
2004 - c1823.zip

Abstract:
Text: bits called a code word. s Convolution Codes, where the code words produced depend on both the , Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pseudo Code for , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pseudo Code for , . . . . . . . . . . . . . . . . . 10 ECC HARDWARE CODE GENERATION AND CORRECTION - VERILOG MODEL . , CODES The Block Code family can be divided up into (see Figure 1.): s Linear Codes, where every


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PDF AN1823 c1823 c1823.zip verilog code hamming flash hamming ecc an1823 AI09 7 bit hamming code hamming code hamming code-error detection correction LP03 LP05
1999 - digital FIR Filter verilog code

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Text: above 100 megasamples per second (MSPS), making PLDs ideal for high-speed filtering applications. The , FIR filter models (also known as bit-true models) in the Verilog HDL and VHDL languages, and for the MATLAB environment (M-files and Model Files). Automatically generating the code required for the , processing (DSP) applications Family: APEXTM 20K, FLEX® 10K, FLEX 8000, and FLEX 6000 Ordering Code , impulse response (FIR) filter development environment Highly optimized for Altera® device architectures


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2008 - verilog code for 2-d discrete wavelet transform

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Text: XAPP932 Two-Dimensional Linear Filtering ( 2D FIR) DS-SYSGEN-4SL-PC XAPP933 Video Virtual , · World Class Development tools 2-D Discrete Cosine Transform (DCT) - Algorithms and IP cores for , Performance FPGAs For Signal Processing It is no accident that Xilinx FPGAs serve an increasingly vital , for higher quality, higher bandwidth, and inexpensive wired and wireless communications of voice , exponentially. This is due in large part to the need for interoperability and data exchange across myriad


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2008 - vhdl code for DES algorithm

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Text: Two-Dimensional Linear Filtering ( 2D FIR) XAPP933 Video Virtual Socket Architecture XAPP919 PowerPC , Implementations FPGA Implementation of Adaptive Temporal Kalman Filter for Real Time Video Filtering FPGA , Highest Performance FPGAs For Signal Processing It is no accident that Xilinx FPGAs serve an , global demand for higher quality, higher bandwidth, and inexpensive wired and wireless communications , grown exponentially. This is due in large part to the need for interoperability and data exchange


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1998 - wavelet transform verilog

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Text: Forward and Inverse Discrete Wavelet Transform ( 2D -DWT) using the 9/ 7 filters for the DWT , using 5/3 on both rows or columns for the forward and the inverse 2D DWT. The filter_engine consists of , RC_2DDWT: Combine 2D Forward/ Inverse Discrete Wavelet Transform November 30, 2001 Product , devices No Internal TRI's Fully synchronous design 2D combined forward/inverse wavelet transform using , input pixel (34,67 Mpixels/sec for Virtex-II family) EDIF netlist, Source RTL (optional) rc


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PDF 512x512 JPEG2000 JTC1/SC29/WG11, wavelet transform verilog verilog 2d filter xilinx wavelet transform FPGA single port ram testbench vhdl virtex 5 fpga based image processing verilog testbench for controlunit testbench vhdl ram 16 x 4 testbench verilog ram 16 x 8
2000 - XILINX vhdl code REED SOLOMON encoder decoder

Abstract:
Text: , Spartan, SpartanTM-II, VirtexTM, and VirtexTM-E devices · Programmable solution for high data rate , polynomial · Single encoder implementation supports any valid data block length · Systematic code structure where each code word can be partitioned into original data block and appended parity symbols · , VHDL, Verilog Instantiation Templates Reference Designs & Application Notes None Additional Items , FPGA-based core for systems where data error detection/correction is required. The core implements the full


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PDF 4000X, XILINX vhdl code REED SOLOMON encoder decoder "Galois Field Multiplier" verilog Reed-Solomon Decoder verilog code XILINX vhdl code download REED SOLOMON encoder decoder XILINX vhdl code download REED SOLOMON vhdl code for a 9 bit parity generator vhdl code for 8-bit parity generator encoder verilog coding convolution encoders Reed-Solomon encoder
1999 - "Galois Field Multiplier" verilog

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Text: Features · · Programmable solution for high data rate ReedSolomon encoding ISS can configure to support a , data block length Systematic code structure where each code word can be partitioned into original data , Verification Test Vectors VHDL, Verilog Instantiation Templates Reference Designs & Application Notes None , encoder is a Xilinx FPGA-based core for systems where data error detection/correction is required. The , circuitry using a single Xilinx FPGA. The source code version of the core is extremely flexible due to its


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PDF 4000XL, "Galois Field Multiplier" verilog XILINX vhdl code REED SOLOMON encoder decoder vhdl code for bit interleaver Reed-Solomon Decoder verilog code xilinx vhdl code for digital clock 4005XL viterbi convolution
2008 - verilog code for image processing

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Text: rigorous code coverage measurements. Deliverables The core includes everything required for successful implementation: VHDL or Verilog RTL source code Post-Synthesis EDIF (netlist release) Sophisticated , Does not insert extra idle cycles and compensates host stalls ­ perfect for video encoders , image transform context a well known example is the 2D -Discrete cosine transform ( 2D -DCT), especially the 8x8 block 2D -DCT, found among others in the MPEG video compression and in JPEG image compression


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