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Part Manufacturer Description Datasheet Download Buy Part
LT1102 Linear Technology IC INSTRUMENTATION AMPLIFIER, 500 uV OFFSET-MAX, Instrumentation Amplifier
LM308AN8 Linear Technology IC OP-AMP, 500 uV OFFSET-MAX, PDIP8, PLASTIC, DIP-8, Operational Amplifier
LT1114IJ8 Linear Technology IC QUAD OP-AMP, 500 uV OFFSET-MAX, CDIP8, HERMETIC SEALED, CERDIP-8, Operational Amplifier
LM308AN8#PBF Linear Technology IC OP-AMP, 500 uV OFFSET-MAX, PDIP8, PLASTIC, DIP-8, Operational Amplifier
LT1113IJ8 Linear Technology IC DUAL OP-AMP, 500 uV OFFSET-MAX, CDIP8, HERMETIC SEALED, CERDIP-8, Operational Amplifier
LT1101MJ8/883B Linear Technology IC INSTRUMENTATION AMPLIFIER, 500 uV OFFSET-MAX, 0.037 MHz BAND WIDTH, CDIP8, CERDIP-8, Instrumentation Amplifier

udl 500 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2006 - debus

Abstract: ATA5590 crc5 calculation transistor UHF manual iso15434 125 kHz RFID kit reader speed limit UDL500 ISO15962 RFID interrogator car Speed Sensor using RFID
Text: ATA5590 with the UDL 500 reader. The ATA5590 allows using a memory area other than the ID page for , 867.6) with a maximum output power of 2W ERP, and 12 channels at a maximum output power of 500 mW ERP , output power of 500 mW ERP. Channel bandwidth: 250 kHz 3. FCC part 15: 50 available channels (902 MHz to 928 MHz) with a maximum output power of 4W EIRP. Channel bandwidth: 500 kHz For the European radio , : faster then Aloha). In Polling mode, up to 135 transponder serial numbers can be stored in the UDL


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PDF ATA5590 4910B debus ATA5590 crc5 calculation transistor UHF manual iso15434 125 kHz RFID kit reader speed limit UDL500 ISO15962 RFID interrogator car Speed Sensor using RFID
2005 - UDL42

Abstract: UDL33 UDL44 UDL45
Text: and AHB slave interfaces between ARM subsystem and UDL 1 channel serial interface (UART) Integrated , logic ( UDL ) complexity of max. 250,000 raw gates for µPD66702 and 440,000 raw gates for µPD66703 · Max , · · · · · · · · · · · Package 240FPBGA 256PBGA UDL complexity 250,000 raw gates 440,000 raw , Memory External Memory or UDL 16-bit MII Interface UDL I/Os ARM Subsystem (ARMSS , Logic ( UDL ) AHB1 AHB2 AHB3 to AHB master AHB-to-APB Bridge Decoder WPC SRAM (8 KBytes


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PDF PD66702, PD66703 32-Bit UDL42 UDL33 UDL44 UDL45
CON008

Abstract: IE-V850E-MC-EM1-B IE-V850E-MC-A IE-V850E-MC V850E1 NB85E IE-V850E-MC-MM2 UPA67C transistor manual substitution FREE DOWNLOAD transistor manual substitution
Text: .43 APPENDIX B UDL BOARD INTERFACE CONNECTOR LOCATIONS .45 APPENDIX C UDL INTERFACE CONNECTOR SIGNAL TABLE (VIEWED FROM IE-V850E-MC-EM1-B , .48 NB85E Pin and UDL Connector Correspondence Tables , .65 APPENDIX D ELECTRICAL SPECIFICATIONS OF UDL INTERFACE , is possible by connecting the IE-V850E-MC-A, IE-V850E-MC-EM1-B, and UDL (User Design Logic) board


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PDF d88-6130 CON008 IE-V850E-MC-EM1-B IE-V850E-MC-A IE-V850E-MC V850E1 NB85E IE-V850E-MC-MM2 UPA67C transistor manual substitution FREE DOWNLOAD transistor manual substitution
1997 - Not Available

Abstract: No abstract text available
Text: Shelves and clips UDL * 185kg Shelf clip (4 per shelf 2 x LH, 2 x RH) Shoe * UDL = Uniformly , Shelves can be adjusted using the clips at 50mm intervals on the uprights. Top cap UDL * 185kg Tang * UDL = Uniformly distributed load Cleat Available in two depths according to the system chosen , and top shelf beams Max UDL (945kg) 185kg Beam clip 135kg 135kg 135kg 135kg 135kg 135kg , 231-226 231-232 231-248 The basic and additional bays shown above must not have a combined UDL


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PDF 18swg 1090mm 500mm 1090mm
transistor manual substitution FREE DOWNLOAD

Abstract: ic manual substitution FREE con039 connector vpa9 transistor manual substitution timer oscillator-IC 555 sksa 1/3 UPA67C MC 151 transistor IE-V850E-MC
Text: .43 APPENDIX B UDL BOARD INTERFACE CONNECTOR LOCATIONS .45 APPENDIX C UDL INTERFACE CONNECTOR SIGNAL TABLE (VIEWED FROM IE-V850E-MC-EM1-B , .48 NB85E Pin and UDL Connector Correspondence Tables , .65 APPENDIX D ELECTRICAL SPECIFICATIONS OF UDL INTERFACE , is possible by connecting the IE-V850E-MC-A, IE-V850E-MC-EM1-B, and UDL (User Design Logic) board


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PDF IE-V850E-MC-EM1-B, IE-V850E-MC-MM2 V850E1 NB85E U14482EJ2V0UM00 transistor manual substitution FREE DOWNLOAD ic manual substitution FREE con039 connector vpa9 transistor manual substitution timer oscillator-IC 555 sksa 1/3 UPA67C MC 151 transistor IE-V850E-MC
2005 - 32 bit AHB lite bus

Abstract: ARM7 microcontroller pin configuration ARM7TDMI-STM-based multiport memory controller EB-SOCLITEPLUS-EP1S60V1 ARM7TDMI-S external bus interface unit suffix part number NEC microcontroller A1658 bridge 4580 a16902ee
Text: ) AHB2AHB Bridge AHB4 APB IRC Timer Watchdog Interrupt UDL (User Defined Logic , boundary scan · User-defined logic ( UDL ) area for custom function integration - Sea-of-Gates type 0.25 µm drawn gate length Gate Array ASIC architecture - Two UDL size options: - Option A: up to 250K , range: -40 to +85°C · Packages: - 240-pin FPBGA for UDL option A - 256-pin BGA for UDL option B , additional signals required for interrupts and reset are made available to the UDL . Memory The memory


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PDF A16582EE6V0PL00 32 bit AHB lite bus ARM7 microcontroller pin configuration ARM7TDMI-STM-based multiport memory controller EB-SOCLITEPLUS-EP1S60V1 ARM7TDMI-S external bus interface unit suffix part number NEC microcontroller A1658 bridge 4580 a16902ee
2003 - nec 0511

Abstract: A1504 UDL 2003
Text: the customer is required to design the UDL (User Defined Logic) area of the SoCLite device a smooth an easy design flow becomes important. The target is to integrate the customer specific UDL design , traditional gatearray ASICs, the UDL area consists of a pre-diffused sea-of-gates array. Custom logic is , UDL design flow starts with the design input in form of VHDL. The design is simulated at the , gate level. The UDL part can be simulated together with the SoCLite ARM subsystem by using a model for


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PDF A15047EE1V2PL00 nec 0511 A1504 UDL 2003
2002 - st vu

Abstract: X242 X243 MN863584-D gg15
Text: : 500 kHz max. * LCD drive voltage : VEE +40 V max. * Driver output level 3 , X243 X244 - STVU UD="L " STVU X244 X243 X242 · · · X3 X2 X1 - STVD UD 5-4 , direction UD="L " : X244 X1 - Pin Name Description Shift clock of the internal shift register , UD="L " STVD / STVU Output Input OEVSEL="H" : OEV=Active high OEVSEL="L" : OEV=Active low , ODE="H," OEVSEL="H," and UD="H" 1 2 3 4 5 6 7 243 244 ): UD="L " 245 246


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PDF MN863584 N863584-D 244-pin SDF00031AEM MN863584-D st vu X242 X243 MN863584-D gg15
A08 RF Amplifier

Abstract: UDL-503 SI04 AVANTEK transistor avantek Low Noise Amplifier
Text: ©AVANTEK UDL -503 Thin-Film Limiting Amplifier 5 to 500 MHz FEATURES APPLICATIONS • Frequency Range: 5 to 500 MHz • Output Power Flatness: ±0.8 dB (Typ) • Input Power Range: 40.0 dB • Low Phase Shift Variation • High Even-Harmonic Suppression DESCRIPTION The UDL -503 Is a three-stage bipolar RF limiting amplifier having 38 dB (typ) of small signal gain. Emitter-coupled pair design , ,2 " 0 . Phase Shift y / s 100 200 300 409 500 600 700


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PDF UDL-503 UDL-503 50-ohm 125-C 240C/W 8S035 A08 RF Amplifier SI04 AVANTEK transistor avantek Low Noise Amplifier
2000 - NB85E

Abstract: V850E PCISLOT VR41
Text: channel for FPGA download VR412x or NB85E UDL (FPGA) or NEC IP or Customer Card System Bus , System Block Diagram PCI-Slot UDL (FPGA) or NEC IP or Customer Card PCI-Slot UDL (FPGA) or NEC IP or Customer Card PCI-Slot UDL (FPGA) or NEC IP or Customer Card PCI-Slot UDL (FPGA) or NEC IP or Customer Card PCI-Slot UDL (FPGA) or NEC IP or Customer Card PCI-Slot PCI-Bridge UDL (FPGA


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PDF A14706EE1V0PL00 NB85E V850E PCISLOT VR41
2003 - ARM7tdmi functional diagram

Abstract: SMALL ELECTRONICS PROJECTS free 32-bit ARM A1504 A15402EE1V0UM00 AMBA AHB memory controller AMBA APB UART
Text: - JTAG interface for debug and boundary scan · User-defined logic ( UDL ) area for custom function , reset are made available to the UDL . Clock Generation The SoCLite clock generation has two parts: an oscillator and a programmable PLL. The output frequency to the UDL area is selectable in the , 32 interrupts: 29 interrupts from the UDL and 3 from the ARM® subsystem. All interrupts are priority , watchdog timer, generating a reset on overflow. UDL The sea-of-gates type gate array area for the UDL


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PDF A15045EE5V3PL00 ARM7tdmi functional diagram SMALL ELECTRONICS PROJECTS free 32-bit ARM A1504 A15402EE1V0UM00 AMBA AHB memory controller AMBA APB UART
2003 - JTAG via rs232

Abstract: No abstract text available
Text: for the user defined logic ( UDL ). An FPGA development environment from either Xilinx or Altera can be used to design the UDL part. The prototype chip and the FPGA make up a complete SoCLite device , between the ARM subsystem and the UDL in the final SoCLite chip. All signals such as APB, interrupts , are the external UDL signals (133 pins). Features · · · · Ordering Information FPGA , Expansion connectors for external memory bus and UDL pins Board Size: 220mm x 160mm Power supply included


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PDF A15046EE3V2PL00 JTAG via rs232
2002 - A15647EE2V0DS00

Abstract: A15402EE1V0UM00 CMOS-9HD ea-9hd number of pins of ARM7 bv08
Text: bit (APB Slave) Interrupt Controller up to 29 interrupt sources (APB Slave) UDL Reset , UDL . Preliminary Data Sheet A15647EE2V0DS00 7 SoCLite Table of Contents INTERNAL BLOCK , . 11 Internal Pins between ARM subsystem and UDL , and Boundary Scan Interface SoCLite (2) Internal Pins between ARM subsystem and UDL Table 1-2: Pin Name Internal Pins between ARM subsystem and UDL Direction Function PRESETn


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PDF PD65977S1-xxx-B6 A15647EE2V0DS00 A15402EE1V0UM00 CMOS-9HD ea-9hd number of pins of ARM7 bv08
bdv 83 do

Abstract: CMOS-9HD A15647EE1V0DS00 ea-9hd
Text: . . . . . . 30 2.2.2 Internal Pins between ARM subsystem and UDL . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . 95 Synchronization of Interrupt Sources from UDL . . . , 15.3.3 Reset by UDL Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . 45 On-chip peripheral I/O and UDL area , . 140 APB Bus to UDL Area Signals


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PDF 32-Bit PD65977S1-xxx-B6 A15402EE1V0UM00 sta8-6130 bdv 83 do CMOS-9HD A15647EE1V0DS00 ea-9hd
UDL-502

Abstract: No abstract text available
Text: ©AVAJNTESC UDL -5Ö2 Thin-Film Limiting Amplifier 5 to 500 MHz - FEATURES APPLICATIONS • Frequency Rangs: 5 to 500 MHz • All FM Systems • Output Power Flatness: • • Communications ±0.5 dB (Max.) »Telemetry • Input Power Range: 30,0 dB • Radar Warning • Low Phase Shift Variation • Measurement Systems • High Even-Harmonic Dipcase,p.i6-u Suppression . DESCRIPTION The UDL -502 is a three-stage bipolar RF limiting amplifier with conversion. The RF signal is coupled through the amplifier by


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PDF UDL-502 50-ohm an200 15dBm
IRF 930

Abstract: te connectivity dq 94v-0 alco adp04 ADP04 ADPA1004 DM 321 94v-0 scale
Text: STRENGTH: 500 VAC. LIEE EXPECTANCY: 1000 CYCLES MECHANICAL: ACTUATION EORCE: 800g MAX. ENVIRONMENTAL , .078] ADP10STR04 3-1571999-9 OBSOLETE tl irf 1 n ^~> 38 n n^Rl Anpin^APM 7 11qqq P 1 UDL I u , / 1999 — 4 Tl Ipr n OA Q/L r n^Ql AnpnncAfiA A e. 1 qqq 7 1 UDL J . U / o aui udJau'i- O I O / I , A HA r a npnnn/i -t. a t=,~71 qqq i 1 UDL nurujui U J/1JjJ 1 OBSOLETE tapr °r prn °\a/itpi , ] ADP05STR04 1-1571999-4 OBSOLETE Tl IRF s 1 A 68 r 5^81 i 1 c,-/1 qqq 7 1 udl u nurujjnut 1 j / 1 j j


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PDF ADP04 MATER10 14FEB05 15FEB05 IRF 930 te connectivity dq 94v-0 alco adp04 ADP04 ADPA1004 DM 321 94v-0 scale
2001 - Not Available

Abstract: No abstract text available
Text: to 190K raw gates available for User Defined Logic • APB interconnection to the UDL â , made available to the UDL . Clock Generation SoCLite clock generation has three parts: an , 32 interrupts: 29 interrupts from the UDL and 3 from the ARM® subsystem. All interrupts are , timer is used as a watchdog timer, generating a reset on overflow. UDL The sea-of-gates area for the User Defined Logic has a size of 190K raw gates. The UDL area is connected via the APB bus with the


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PDF A15045EE4V0PL00
irf 930

Abstract: ADP04 ADPA02S04
Text: RESISTANCE: 100 MEGOHMS MIN. @ 100 VDC. DIELECTRIC STRENGTH: 500 VAC. LIEE EXPECTANCY: 1000 CYCLES MECHANICAL , OBSOLETE Tl IRF 1 n ^~> 38 n n^Rl AnpincAPM 7 11qqq P 1 UDL I u /\ur i uo/ \u i u J / I a J J u TUBE , AnpnncAfiA -i c"7 i qqq 1 UDL J . U / o AUI UdJAU'i- O I O / I J J J O r-\ /I n A r n ~71-1 "I 1 UBE 9 24.o4 .9 / o ADP09b04 o—15/1999—z Tl IRF q ^ A HA r a npnnn/i -t. 1 !=,-/1 qqq i 1 UDL , 1-1571999-4 OBSOLETE Tl IRF s 1 A 68 r 5^81 i 1 c,-/1 qqq 7 1 udl u nUruJjnUT 1 J / 1 J J J u TUBE 5


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PDF ADP04 14FEB05 15FEB05 irf 930 ADP04 ADPA02S04
ARM7 pin configuration

Abstract: 32 bit AHB lite bus altera jtag ethernet ARM7 microcontroller pin configuration arm7 SRAM EP1S60
Text: environment from Altera® can be used to design the UDL part. The prototype chip and the FPGA make up a , identical to the internal connections between the ARM® subsystem and the UDL in the final System-on-Chip , external connectors for test and evaluation purposes, as are the external UDL signals. Block Diagram , ) Expansion connectors for logic analyser Expansion connectors for external memory bus and UDL pins Board


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PDF 10/100M important030 A17207EE1V1PL00 ARM7 pin configuration 32 bit AHB lite bus altera jtag ethernet ARM7 microcontroller pin configuration arm7 SRAM EP1S60
Not Available

Abstract: No abstract text available
Text: I0AVANTEK FEATURES · Frequency Range: 5 to 500 MHz · Output Power Flatness: ±0.8 dB (Typ) · Input Power Range: 40.0 dB · Low Phase Shift Variation · High Even-Harmonic Suppression DESCRIPTION The UDL , . Emitter-coupled pair design provides even-harmonic suppression and low AM-to- UDL -503 T hin-F ilm L im itin g A m p lifie r 5 to 500 MHz APPLICATIONS · · · · · All FM Systems Communications Telemetry Radar , 0 0 £ s a 0« i I " i " / rs ' s 100 200 300 400 500 600 700 -7 0 Frequency


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PDF UDL-503 50-ohm 240C/W CA95Q35
2010 - v850e2

Abstract: V850E2M 144LQFP renesas v850e2 V850E2 core 176-LQFP V850E1 SH 10KB
Text: UDL 600Kgate V850E2M Core V850E2M Ether CAN Ether CAN EP-1 200MHz UDL , - EP-x 150MHz EP-1 UDL 80Kgate V850E2M Core V850E2M


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PDF V850Next V850E2M V850E2 V850E1 176LQFP 168KB/32KB 200MHz V850ES V850E/MA3 144LQFP/161FBGA v850e2 V850E2M 144LQFP renesas v850e2 V850E2 core 176-LQFP V850E1 SH 10KB
32 bit AHB lite bus

Abstract: usb to rj45 connection diagram sub-d9 F uclinux JTAG MINI nec cpld SUBD25
Text: logic ( UDL ) that expand the functionality of the ARM7TDMI-based embedded microcontroller system , K raw ASIC gates UDL (Type: Altera Cyclone) · Flash (4 Mbytes) · SDRAM (32 Mbytes) · Serial port , AHB bus USB buffer UDL pins USB buffer I/F Multipoint connector System-on-Chip Lite


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PDF U17431EE1V0PL00 32 bit AHB lite bus usb to rj45 connection diagram sub-d9 F uclinux JTAG MINI nec cpld SUBD25
Not Available

Abstract: No abstract text available
Text: AVANTEK INC 44E ]> im n b h 0006137 L B A V A . UDL -503 Thin-Film Limiting Am plifier 5 to 500 MHz 'T "^ -O c o \ ì FEATURES APPLICATIONS • Frequency Range: 5 to 500 MHz • Output Power Flatness: ±0.8 dB (Typ) • Input Power Range: 40.0 dB • Low Phase Shift , The UDL -503 Is a three-stage bipolar RF limiting amplifier having 38 dB (typ) of small signal gain , Frequency, MHz y I * £ o .* 8 Power Input, dBm 0 / V y s 200 300 400 500 600


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PDF UDL-503 UDL-503 240C/W 100mW
electrolytic capacitors panasonic catalog

Abstract: No abstract text available
Text: leakage current < Initial specified value After storing for 500 hours at 60 °C, 90 % Capacitance , specified value DC leakage current < Initial specified value After storing for 500 hours at 60 °C , After storing for 500 hours at 60 °C, 90 % Capacitance change of initial measurd value tan d DC , measured value < Initial specified value < Initial specified value After storing for 500 hours at 60 , specified value After storing for 500 hours at 60 °C, 90 % Moisture resistance +70, –20 % â


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PDF
UTL502

Abstract: pp48
Text: ¥ & i H E W LE T T mLUM P A C K A R D Avantek Products IF/RF Limiting Amplifiers Selection Guide UDL S eries UTL S eries PPL S eries D escrip tion HP limiting amplifiers, available in TO-8, dual-inline and surfacem ount PlanarPak packages, are excellent for application in ECM, radar and instrum , R-Series screening, see Reliability Screening, Section 6. UDL /UTL S eries Thin-Film Limiting A m , D C ) + 15, -15 + 15 + 15 P age N um ber 1-406 1-408 1-404 M od el UTL-502 UTL-503 UDL -503 C


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PDF PP-48 UTL-502 UTL-503 UDL-503 PPL-504, PPL-504 UTL502 pp48
Supplyframe Tracking Pixel