The Datasheet Archive

Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
TC75S102F TC75S102F ECAD Model Toshiba Electronic Devices & Storage Corporation Operational Amplifier, 1.5V to 5.5V, I/O Rail to Rail, IDD=0.27μA, SOT-25
TLX9188 TLX9188 ECAD Model Toshiba Electronic Devices & Storage Corporation Photocoupler (phototransistor output), DC input, 3750 Vrms, SO6, Automotive
TLP3412SRHA TLP3412SRHA ECAD Model Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 60 V/0.4 A, 500 Vrms, S-VSON4T
TLP3407SRL TLP3407SRL ECAD Model Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 60 V/1 A, 500 Vrms, S-VSON4T
TCR2EE18 TCR2EE18 ECAD Model Toshiba Electronic Devices & Storage Corporation LDO Regulator, Fixed Output, 1.8 V, 200 mA, SOT-553 (ESV)
TLP3483 TLP3483 ECAD Model Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 200 V/0.35 A, 500 Vrms, P-SON4

ttl input convert to vga output Datasheets Context Search

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ttl input convert to vga output

Abstract: CRTTOLCD-5 CRTtoLCD JILI-30 15 pin vga pin out connections dvi to lvds 4558 pin configuration DVI-D CONNECTIONS kontron JILI30
Text: , with analog RGB and DVI Input (for TTL Flatpanels) CRTtoLCD OSD-Panel-Set 22010 OSD-Panel-Set KAB-COMtoTTL Part.-No. 61021 Cable adapter to convert RS232 Signals to TTL (for configuration of , RGB- and DVI-Video sources TTL RGB (FLEX32) or LVDS (KAB-JILI30) output Highest picture quality by , standard VGA connector All color depths up to 24 bits/pixel DVI-Input Features Standard DVI-D-Connector , LVDS) Output up to SXGA @ 75Hz Form Factor 180 x 119.5 mm Mechanically compatible to CRTtoLCD-1, -2


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PDF FLEX32) KAB-JILI30) DE-22081 22092008PDL ttl input convert to vga output CRTTOLCD-5 CRTtoLCD JILI-30 15 pin vga pin out connections dvi to lvds 4558 pin configuration DVI-D CONNECTIONS kontron JILI30
ttl input convert to vga output

Abstract: rgb 18 bit to lvds CRTtoLCD-5 KAB-JILI30 dvi convert to vga 4558 pin configuration JILI30 TTL RGB to analog RGB 15 pin vga pin out connections 24 bit lvds lcd interface
Text: convert RS232 Signals to TTL (for configuration of controller via PC) Corporate Offices Europe, Middle , Plug&Display connections of flatpanels to analog RGB- and DVI-Video sources TTL RGB (FLEX32) or LVDS , RGB-Interface, Resolution up to UXGA 60 Hz 15 Pin standard VGA connector All color depths up to 24 bits/pixel , Features: Backlight dimming support FLEX32 (18 Bit TTL ) JILI30 (2x 24 Bit LVDS) Output up to SXGA @ 75 Hz Input Voltage Dimensions: OSD-Panel


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PDF FLEX32) KAB-JILI30) DE-22081 30082006PDL ttl input convert to vga output rgb 18 bit to lvds CRTtoLCD-5 KAB-JILI30 dvi convert to vga 4558 pin configuration JILI30 TTL RGB to analog RGB 15 pin vga pin out connections 24 bit lvds lcd interface
1998 - AIT2138

Abstract: Composite Video to VGA decoder NTSC PAL to LCD converter SCL SDA VSYNC HSYNC PXCK image TTL to vga TV DIGITAL DECORDER CIRCUIT DIAGRAM vga to composite video converter composite video to vga converter TA 8783 N 0/aitech 2138
Text: output video timing become independent. The AIT2138 has the capability to accept VGA input not , through an external SDRAM or EDO memory which allows the AIT2138 to accept VGA input not necessarily , Reference Input , Unbuffered VGA Horizontal Sync VGA Vertical Sync +0.85V 81 +0.85V 93 TTL , Synchronization Signal Output TTL 82 Encoder VREF D/A Voltage Reference Input / Output +1.235V , TTL 32 PDO_14 DQM, Data Input / Output mask TTL 33 Encoder Controls Video Inputs


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PDF AIT2138 AIT2138 Composite Video to VGA decoder NTSC PAL to LCD converter SCL SDA VSYNC HSYNC PXCK image TTL to vga TV DIGITAL DECORDER CIRCUIT DIAGRAM vga to composite video converter composite video to vga converter TA 8783 N 0/aitech 2138
1998 - AIT2139

Abstract: No abstract text available
Text: output video timing become independent. The AIT2139 has the capability to accept VGA input not , ://WWW.AITECH.COM 8/36 $,7 VGA to NTSC/PAL Encoder EDO Memory I/O PDI0-15 Pixel Data Input / Output , external SDRAM or EDO memory which allows the AIT2139 to accept VGA input not necessarily synchronized , de-coupling the input and output , the stable time-base ensures adherence to the television standards. HTTP://WWW.AITECH.COM 2/36 $,7 VGA to NTSC/PAL Encoder Input A/D conversion Eight-bit A


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PDF AIT2139
1998 - 437080

Abstract: No abstract text available
Text: memory which allows the AIT2138 to accept VGA input not necessarily synchronized with TV timing. The , , S-Video, RGB or YUV output signals. The AIT2138 comprises all of the circuitry necessary to convert , AIT2138 has the capability to accept VGA input not necessarily synchronized with TV timing, to , oscillator or crystal to an internal oscillator circuit. As a result of de-coupling the input and output , Composite Synchronization Signal Output TTL 82 Encoder VREF D/A Voltage Reference Input


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PDF AIT2138 437080
1998 - TA 8783 N

Abstract: NTSC PAL to LCD converter VGA to NTSC AIT2139 TA 8783 Composite Video to VGA decoder TV DIGITAL DECORDER CIRCUIT DIAGRAM NEC-PC98 ait2138 genesis lcd controller
Text: external SDRAM or EDO memory which allows the AIT2139 to accept VGA input not necessarily synchronized , AIT2139 has the capability to accept VGA input not necessarily synchronized with TV timing, to , crystal to an internal oscillator circuit. As a result of de-coupling the input and output , the stable , Composite Synchronization Signal Output TTL 82 Encoder VREF D/A Voltage Reference Input , _13 RAS\, Row Address Strobe TTL 32 PDO_14 DQM, Data Input / Output mask TTL 33 Encoder


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PDF AIT2139 TA 8783 N NTSC PAL to LCD converter VGA to NTSC TA 8783 Composite Video to VGA decoder TV DIGITAL DECORDER CIRCUIT DIAGRAM NEC-PC98 ait2138 genesis lcd controller
1998 - TV DIGITAL DECORDER CIRCUIT DIAGRAM

Abstract: AIT2138 scart vga aitech 2138 VGA to NTSC to pal b vga to tv converter video vga to composite convert EIA-608 VM700T 6-bit ram-dac video converter
Text: accomplished through an external SDRAM or EDO memory which allows the AIT2138 to accept VGA input not , independent. The AIT2138 has the capability to accept VGA input not necessarily synchronized with TV timing , de-coupling the input and output , the stable time-base ensures adherence to the television standards. HTTP://WWW.AITECH.COM 2/33 $,7 VGA to NTSC/PAL Encoder Input A/D conversion Eight-bit A/D , 31 PDO_13 RAS\, Row Address Strobe TTL 32 PDO_14 DQM, Data Input / Output mask TTL


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PDF AIT2138 TV DIGITAL DECORDER CIRCUIT DIAGRAM scart vga aitech 2138 VGA to NTSC to pal b vga to tv converter video vga to composite convert EIA-608 VM700T 6-bit ram-dac video converter
1998 - AIT2139

Abstract: aitech 2138 TV DIGITAL DECORDER CIRCUIT DIAGRAM ait2138
Text: timing become independent. The AIT2139 has the capability to accept VGA input not necessarily , de-coupling the input and output , the stable time-base ensures adherence to the television standards. HTTP://WWW.AITECH.COM 2/35 $,7 VGA to NTSC/PAL Encoder Input A/D conversion Eight-bit A/D , Reference Input , Unbuffered VGA Horizontal Sync VGA Vertical Sync +0.85V 81 +0.85V 93 TTL , Synchronization Signal Output TTL 82 Encoder VREF D/A Voltage Reference Input / Output +1.235V


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PDF AIT2139 aitech 2138 TV DIGITAL DECORDER CIRCUIT DIAGRAM ait2138
2013 - Not Available

Abstract: No abstract text available
Text: from the video controller IC. These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and VCC 。 These drivers have a nominal 60Ω output impedance to , buffer inputs. Vertical sync signal buffer input . Connects to the VGA Controller side of the vertical , Capacitance from ESD Protection Diodes at Less than 5pF Typical  * TTL to CMOS Level−Translating , 14 VSYNC 15 VSYNC_OUT DESCRIPTION Horizontal sync signal buffer output . Connects to the


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PDF QW-R223-021
TDC1048C3V

Abstract: 5962-8760001XA 59628760001XA
Text: Significant Bit IN Vert TTL 12 Convert CONV Convert TTL 17 Analog Input V|N , Figure 3. Convert Input Equivalent Circuit +vc c Output Coding Table B inary Step Range -2 , clocked latching comparators, combining logic, and an output buffer register. A single convert signal , comparator array compares the input signal with 255 reference voltages to produce an N-of-255 code , the output coding to be either straight binary or offset two's complement, In either true or


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PDF TDC1048 TDC1048 28-pin 5962-8760001XA TDC1048C3C TDC1048C3V 962-87600013A TDC1048B6C TDC1048C3V 5962-8760001XA 59628760001XA
VGA Signal Generator

Abstract: GSP600 S/BIP/SCB345100/B/30/10/trident up conversion frame rate overlay
Text: SUBCARRIER OUTPUT . 17.734475 MHz signal phase-locked to the chroma burst signal. PCLK from VGA chip. TTL , creates the D-15 SYNC OUTPUT for the monitor connection to allow for TV projec­ tion output of the VGA , not wire. For ICS use only, wire to pin 57. Clock signal input for VGA chip. Inverts field 1 and , input . Mode identification output signal. HIGH indicates a VGA mode, LOW indicates a PAL mode. BURST , sources and will synchronize (genlock) a VGA controller to either the external video input or an internal


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PDF GSP600 GSP600 GSP600? DDQlb31 VGA Signal Generator S/BIP/SCB345100/B/30/10/trident up conversion frame rate overlay
Not Available

Abstract: No abstract text available
Text: input from a camcorder or a VCR and will synchronize (genlock) the VGA or Super VGA controller to the , to VIDEO INPUT 1 or VIDEO INPUT 2. The GSP500 provides an RGB-toNTSC encoder with the VIDEO OUTPUT , INPUT tells the encoder whether to display the VGA image or external video for each pixel. Assuming , Clock Regulation The GSP500 looks at the input sync from the VGA control­ ler and determines how to , modifies sync characteristics to permit operation with VCR input . Mode identification output signal. HIG H


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PDF GSP500 GSP500 GSP500?
Not Available

Abstract: No abstract text available
Text: the monitor connection to allow for TV projec­ tion output o f the VGA images. The PIX EL SW IT C H infor­ mation derived from external CKEY INPUT tells the encoder whether to display the VGA image or , VCOOUT FILTSEL For ICS use only, wire to pin 57. 54 DOTCLOCK Clock signal input for VGA chip , modifies sync characteristics to permit operation with VCR input . 57 VGA /NTSC Mode identification , signal phase-locked to the chroma burst signal. PCLK from VGA chip. 67 DATAOUT TTL level


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PDF GSP500 GSP500 RS-170A GSP500?
1999 - ttl input convert to vga output

Abstract: diagram vga port VGA201
Text: Controller IC (SYNC1, SYNC2). These buffers accept TTL input levels and convert them to CMOS output levels , typical TTL to CMOS level-translating buffers with power down mode for HSYNC and VSYNC lines Three power , without causing the SYNC buffers to draw any current from the VCC3 supply. When the PWR_UP input is LOW , CALIFORNIA MICRO DEVICES VGA201 Pin Diagram VGA PORT COMPANION CIRCUIT Features 7 channels of ESD protection for all VGA port connector pins meeting IEC-61000-4-2 Level-4 ESD requirements


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PDF VGA201 IEC-61000-4-2 16-pin VGA-201 I00-4-2 VGA201 PACVGA201Q ttl input convert to vga output diagram vga port
bt478

Abstract: No abstract text available
Text: V DC Voltage Applied t o GND-0.5 V to V ^ Max+0.5 V Outputs for HIGH Output State DC Input , 160 200 2 4 160 200 clocks mA Test Conditions: TTL Input Level: 0 to 3 V with tp, tF , Clock source pin ( TTL compatible Input ) This input operates at the pixel clock rate of the system. It is to be driven by a dedicated TTL buffer. The rising edge of CLK latches the SYNC, BLANK, PIX0 , significant bit. BLANK Blank ( TTL compatible Input ) The BLANK input , when active, overrides the color


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PDF Am81C471/478 Bt471 Bt478 RS-343A/RS-170 44-pln Am81C478 bt478
C471

Abstract: C478 RS-170 RS-343A bt478
Text: significant bit. rd Read Control Input ( TTL compatible Input ) RD must be a logical zero to read data from , falling edge of RD. WR Write Control Input ( TTL compatible Input ) WR must be a logical zero to write , to.GND-0.5 V to V^ Max+0.5 V Outputs for HIGH Output State DC Input Voltage GND , .):Voc-5.0V,T, + 25»C Test Conditions: TTL Input Level: 0 to 3 V with t, tF (10-90%) S 3 ns RSM , DESCRIPTION Timing Section CLK Clock source pin ( TTL compatible Input ) This input operates at the pixel


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PDF Am81C471/478 Bt471 Bt478 44-pln RS-343A/RS-170 C471 C478 RS-170 RS-343A bt478
2001 - Hsync Vsync analog to digital convert

Abstract: Hsync Vsync convert Hsync Vsync VGA rgb to hsync vsync VSYNC HSYNC DDC_CLOCK DDC_DATA Hsync Vsync separate ttl input convert to vga output Hsync Vsync Hsync Vsync RGB HSYNC, VSYNC input output
Text: buffers will accept TTL input levels and convert them to CMOS output levels that swing between GND and VCC. These drivers have a nominal 60 output impedance to match the characteristic impedance of the , protection diodes, < 5pF typical · TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines · , Output Voltage IOL = 4mA, VCC = 4.5V IIN Input Current MAX UNIT 1 IF = 10mA V , pins at VCC or GND; All other input and output floating R,G, B (Note 1) 5 pF HSYNC, VSYNC


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PDF PACVGA105 IEC-1000-4-2 16-Lead PACVGA105Q Hsync Vsync analog to digital convert Hsync Vsync convert Hsync Vsync VGA rgb to hsync vsync VSYNC HSYNC DDC_CLOCK DDC_DATA Hsync Vsync separate ttl input convert to vga output Hsync Vsync Hsync Vsync RGB HSYNC, VSYNC input output
1998 - SPC8106F0C

Abstract: B800 D477 SPC8106 VGA ramdac 46E8h crt monochrome display 8-bit VGA ramdac
Text: memory array of 256 locations of 6 bits each and hardware to convert VGA palette writes to gray-scale , ,38 Register Select 2 output . This output should be connected to the RS2 input of the RAMDAC , registers in the RAMDAC. 40 477 Control Signal. This output should be connected to the 477/471 input , connecting a standard VGA monitor to the system. The target markets for this device are small, cost , consumption, low component count, and the ability to run most VGA software on a 640×480 LCD panel display are


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PDF PF816-02 SPC8106F0C 85ns/100ns SPC8106F0C B800 D477 SPC8106 VGA ramdac 46E8h crt monochrome display 8-bit VGA ramdac
2012 - STDP9320

Abstract: STDP7320 Turbo186 STDP7310 STDP9320-BB STDP9310 lvds to eDP 2560x1600 STDP9210 HDMI lvds scaler 1920 1200
Text: to 205 MHz) ­ Integrated 2:1 MUX to receive VGA and component input High-speed dual LVDS Tx (STDP73x0 , Multifunctional monitors including 3D monitor, max input and output resolution up to WQXGA (STDP93x0), FHD , -bit 16-bit TTL Input Yes Yes Yes No No Output Package STDP9320-BB STDP9310-BB STDP9210-BB STDP7320-BB , Video processing supports full or partial capture of 4096 x 2160 format scaled to 2560 x 2160 output , Color Convert LINE_IN_R LINE_IN_L MAIN H & V DCDi SCALER, MPEGNR OSD to 4:4:4 ACC3


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PDF STDP9310, STDP9320, STDP9210, STDP7320, STDP7310 STDP93x0) STDP9210) STDP73x0) 10-bit STDP9320 STDP7320 Turbo186 STDP7310 STDP9320-BB STDP9310 lvds to eDP 2560x1600 STDP9210 HDMI lvds scaler 1920 1200
2014 - Not Available

Abstract: No abstract text available
Text: controller IC (SYNC1, SYNC2). These buffers accept TTL input levels and convert them to CMOS output levels , connector side of one of the sync lines. DDC signal input . Connects to the VGA controller side of one of , . Sync signal buffer input . Connects to the VGA controller side of one of the sync lines. Sync signal buffer output . Connects to the video connector side of one of the sync lines Sync signal buffer input . Connects to the VGA controller side of one of the sync lines. Sync signal buffer output . Connects to the


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PDF VGA7S019 VGA7S019 QW-R223-024
2001 - THC63LVDF84B

Abstract: ttl input convert to vga output THC63LVDF64B rx2 1107 THC63LVDF84A thine electronic Thine lvds receiver RX6 735
Text: /DATA (LVDS) RC +/RD +/- CLOCK (LVDS) RCLK +/20 to 85MHz PLL 7 7 7 7 CMOS/ TTL OUTPUT , ) CLOCK (LVDS) RCLK +/20 to 85MHz /PDWN LVDS TO TTL PARALLEL RA +/- LVDS TO TTL PARALLEL CMOS/ TTL OUTPUT PLL 7 7 7 RA0-6 RB0-6 RC0-6 RECEIVER CLOCK OUT (20 to 85MHz , Absolute Maximum Ratings1 Supply Voltage (Vcc) CMOS/ TTL Input Voltage CMOS/ TTL Output Voltage LVDS , tTHL TTL High to Low Transition Time 3.0 5.0 ns tRIP1 Input Data Position0 (T =


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PDF THC63LVDF84B/THC63LVDF64B THC63LVDF84B/THC63LVDF64B 24Bit/18Bit THC63LVDF84B 28bits 85MHz, THC63LVDF64B ttl input convert to vga output rx2 1107 THC63LVDF84A thine electronic Thine lvds receiver RX6 735
2002 - marking codes fairchild

Abstract: 1175AR3C40 Fairchild, 741 op-amp marking codes fairchild DIP
Text: analog-to-digital (A/D) converter employs a two-step flash architecture to convert analog signals into 8-bit digital , conversion at rates up to 40 Msps. The input signal is held in an integral track/hold stage during the conversion process. Operation is pipelined, with one input sample taken and one output word provided for each , -bit A/D quantizer output is gray-coded and converted to binary before it is combined with the coarse , Analog Input and Voltage References The TMC1175A converts analog signals in the range RB to RT into


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PDF TMC1175A 100mW TMC1175A TMC1175AM7C30 TMC1175AN2C30 TMC1175AN2B30 TMC1175AR3C30 marking codes fairchild 1175AR3C40 Fairchild, 741 op-amp marking codes fairchild DIP
2001 - THC63LVDF84B

Abstract: THC63LVDF84A f64a ttl input convert to vga output LVDS 18bit lvds 20 pin lcd panel 10 pin out TTL parallel to vga THC63LVDF64B thine electronic
Text: / TTL OUTPUT DATA (LVDS) RB +/RC +/RD +/- CLOCK (LVDS) RCLK +/20 to 85MHz PLL 7 7 7 , 85MHz) CLOCK (LVDS) RCLK +/20 to 85MHz LVDS TO TTL PARALLEL RA +/- LVDS TO TTL PARALLEL CMOS/ TTL OUTPUT PLL 7 7 7 RA0-6 RB0-6 RC0-6 RECEIVER CLOCK OUT (20 to 85MHz) /PDWN , uA Absolute Maximum Ratings1 Supply Voltage (Vcc) CMOS/ TTL Input Voltage CMOS/ TTL Output , ns tTHL TTL High to Low Transition Time 1.8 3.0 ns tRIP1 Input Data Position0 (T


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PDF THC63LVDF84B/THC63LVDF64B 24Bit/18Bit THC63LVDF84B/THC63LVDF64B THC63LVDF84B 28bits 85MHz, THC63LVDF64B 21bits THC63LVDF84A f64a ttl input convert to vga output LVDS 18bit lvds 20 pin lcd panel 10 pin out TTL parallel to vga thine electronic
2007 - Composite Video to VGA decoder circuit

Abstract: VGA capture SMPTE-274 SAA7108AE pal video sync generator ttl input convert to video output 16168 video auxiliary data
Text: Key benefits Ñ Supports output to most popular PC graphic controllers for easier integration Ñ , together with a TTL composite sync to feed SCART connectors. When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the RGB outputs and separate H and V syncs as well, serving as , 9-BIT VIDEO ADC1 scaled VIDEO and VBI data to VGA capture port, etc VBI DATA SLICER , PIXCLK OUT The video decoder uses line-locked clock decoding to convert PAL, SECAM and NTSC signals


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PDF SAA7108A/09A SAA7108A/09A high-qual306 SAA7108AE/SAA7109AE brb061 Composite Video to VGA decoder circuit VGA capture SMPTE-274 SAA7108AE pal video sync generator ttl input convert to video output 16168 video auxiliary data
Not Available

Abstract: No abstract text available
Text: Table consists of a memory array of 256 locations of 6 bits each and hardware to convert VGA palette , V in Input Voltage Vss-0.3 to V dd+0.3 V V out Output Voltage Vss-0.3 to V dd , falling edge of Register Select 2 output . This output should be connected to the RS2 input of the , registers in the RAMDAC. 40 477 Control Signal. This output should be connected to the 477/471 input , provided to allow connecting a standard VGA monitor to the system. The target markets for this device are


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PDF F816-02 SPC8106Foc 640x480 256x6 256x12 QFP17-144pin
Supplyframe Tracking Pixel