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Part Manufacturer Description Datasheet Download Buy Part
SN74190J-00 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, CDIP16
SN74190J Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, CDIP16
SN74190N-10 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDIP16
SN74190N Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDIP16, PLASTIC, DIP-16
SN74190N-00 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDIP16, PLASTIC, DIP-16
TTL-LOGIC-DATABOOK Texas Instruments TTL-LOGIC-DATABOOK

ttl 74190 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
74190 counter

Abstract: ttl 74190 74191 8 bit 74190 ttl 74191 74191 74191 state diagram counter 74190 74191 logic diagram 74191 counter
Text: TTL /MSI 93190/54190, 74190 93191/54191, 74191 UP/DOWN DECADE AND BINARY COUNTER DESCRIPTION - The , sets QA = A, qb = b, qq = c, and qd = d 8-292 TTL /MSI • 93190/54190, 74190 • 93191/54191, 74191 , 8-293 TTL /MSI • 93190/54190, 74190 • 93191/54191, 74191 ABSOLUTE MAXIMUM RATINGS (above which the , 's measured with all inputs grounded and all outputs open. 8-294 TTL /MSI • 93190/54190, 74190 • 93191 , , duty cycle < 50%, PRR < 1 MHz. 8-295 TTL /MSI • 93190/54190, 74190 • 93191/54191, 74191 PARAMETER


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74190

Abstract: 74LS191 pins ttl 74190 counter 74190 signetics 74190 74191 state diagram 74ls191 function table
Text: Signetics 74190 , 191, LS191 Counters '190 Presettable BCD/Decade Up/Down Counter '191 , TYPE 74190 74191 74LS191 TYPICAL fMAX 25MHz 25MHz 25MHz TYPICAL SUPPLY CURRENT (TOTAL) 65mA 65mA , Products Product S pecification Counters 74190 , 191, LS191 Asynchronous parallel load , mode or reaches " 9 " in the count-up mode for 74190 , and reaches " 1 5 " in the count-up mode for , Signetics Logic Products P roduct S pecification Counters 74190 , 191, LS191 o ir e c t io n


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PDF LS191 74LS191 25MHz 25MHz N74190N, N74191N, N74LS191N N74LS191D 74190 74LS191 pins ttl 74190 counter 74190 signetics 74190 74191 state diagram 74ls191 function table
ci 74190

Abstract: counter 74190 ci 74191 74190 74191 counter ttl 74191 74191 state diagram 74190 equivalent N74190N N74LS191N
Text: and count-down operation. The '191 is similar, but is a 4-bit binary counter. 74190 , 191, LS191 , Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74190 25MHz 65mA 74191 25MHz 65mA 74LS191 , By Its Respective Manufacturer Signetics Logic Products Product Specification Counters 74190 , 191 , reaches zero in the count-down mode or reaches "9" in the count-up mode for 74190 , and reaches "15" in , Material Copyrighted By Its Respective Manufacturer Signetics Logic Products Product Specification 74190


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PDF LS191 500ns 1N916, 1N3064, ci 74190 counter 74190 ci 74191 74190 74191 counter ttl 74191 74191 state diagram 74190 equivalent N74190N N74LS191N
74LS191 pins

Abstract: 74190 TTL 74190 74ls191 function table 74191 state diagram signetics 74190 74190 counter 74LS191 LS191 counter 74190
Text: Signetics Logic Products 74190 , 191, LS191 Counters '190 Presettable BCD/Decade Up/Down , -bit binary counter. TYPE TYPICAL f„AX TYPICAL SUPPLY CURRENT (TOTAL) 74190 25MHz 65mA 74191 25MHz 65mA , Respective Manufacturer Signetics Logic Products Product Specification Counters 74190 , 191, LS191 , zero in the count-down mode or reaches "9" in the count-up mode for 74190 , and reaches "15" in the , Its Respective Manufacturer Signetics Logic Products Product Specification Counters 74190 , 191


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PDF LS191 1N916, N3064, 500ns 74LS191 pins 74190 TTL 74190 74ls191 function table 74191 state diagram signetics 74190 74190 counter 74LS191 LS191 counter 74190
full adder using ic 74138

Abstract: full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 Application of Multiplexer IC 74151 IC 74138 74138 IC decoder Multiplexer IC 74151
Text: contain 14 MSI TTL functions for user evaluation. · May be erased for other uses upon completion of evaluation. · TTL /CMOS I/O compatibility. · Design implemented using Altera's A+PLUS Development System · , speeds and density of the EP1800 series make it suitable for LSI replacement of Low power Schottky TTL in , commonly used TTL SSI and MSI functions. These aid the first time user since the function of these blocks , TTL library designed for use with Altera's low cost schematic capture package LogiCaps. These blocks


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PDF EP1800JC-EV1 EPt800 68-pin EP1800JC-EV1 0UT20 0UT21 OUT22 0UT23 full adder using ic 74138 full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 Application of Multiplexer IC 74151 IC 74138 74138 IC decoder Multiplexer IC 74151
transistor d133

Abstract: ttl 7442 Decoder BCD 7 seg transistor 6B 7-seg ANODE COMMON 74LS247 74155 pin diagram of 74LS247 ttl 74191 75491
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D130 54/ 74190 , 74LS190 54/74191, 74LS191 0131 , 0 ■> Q 01 o _i 'in "3T Ol n je o TTL Yes No No 7.0 55 L Gas Discharge 80 D140 4L.7B, 9B 2 54/ 74145 1-of-10 OC Dvr TTL Yes No Yes 80 15 L Common Anode 215 D135 4L.7B 9B 3 54LS/ 74LS247 7-Seg Decoder/Dvr TTL Yes Yes No 12 15 L LED, Com Anode 30 D143 4L.6B, 9B 4 54LS/ 74LS248 7-Seg Decoder/Dvr TTL Yes Yes No 1.3 5.5 H — 125 D141 4L.6B, 9B 5 54LS/ 74LS249 7-Seg OC


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PDF 74LS190 74LS191 93L21, 54/74S139, 54LS/74LS139 54LS/74LS155 54LS/74LS156 93L01, 93L34, 54LS/74LS259 transistor d133 ttl 7442 Decoder BCD 7 seg transistor 6B 7-seg ANODE COMMON 74LS247 74155 pin diagram of 74LS247 ttl 74191 75491
7408 CMOS

Abstract: TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 TTL 74289 CMOS 4017 series ttl 74395 74106
Text: intervals along the row and column of the chip, also consist of I/O pads which are compatible of CMOS or TTL , Toggling Frequency: 40MHz • High density 3.5 micron geometries • TTL and CMOS I/O compatibility â , OF LS TTL TTL Pari No. Count TTL Part No. Count TTL Part No. Count TTL Part No. Count 7400 4 7470 , 74364 48 7443 29 74108 20 74190 80 74365 37 7444 29 74109 21 74191 76 74366 40 7445 29 74110 14 74192


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PDF KG10000 7408 CMOS TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 TTL 74289 CMOS 4017 series ttl 74395 74106
74139 demultiplexer

Abstract: 74169 SYNCHRONOUS 4-BIT BINARY COUNTER pin diagram 41 multiplexer 74153 3-8 decoder 74138 pin diagram bcd counter using j-k flip flop diagram pin diagram priority decoder 74148 CI 74151 74165 block diagram 74181 74175 clock 74151 demultiplexer
Text: are CMOS and TTL compatible • Each I/O interface cell can be used as an Input, push/pull, tri-state , Generator (0181) 63 27 74182 Look-Ahead Carry Generator (0182) 19 28 74190 Synchronous BCD Up/Down


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PDF MSM60300, MSM60700, MSM61000 MSM60300. MSM60700. MSMC0300 MSM60700 MSM61000 74139 demultiplexer 74169 SYNCHRONOUS 4-BIT BINARY COUNTER pin diagram 41 multiplexer 74153 3-8 decoder 74138 pin diagram bcd counter using j-k flip flop diagram pin diagram priority decoder 74148 CI 74151 74165 block diagram 74181 74175 clock 74151 demultiplexer
74169 SYNCHRONOUS 4-BIT BINARY COUNTER

Abstract: 74139 demultiplexer 3-8 decoder 74138 pin diagram 3-8 decoder 74138 CI 74151 pin diagram 41 multiplexer 74153 JK Shift Register 74195 Multiplexer 74153 bcd counter using j-k flip flop diagram CI 74138
Text: inputs/outputs are CMOS and TTL compatible · Each I/O interface cell can be used as an input, push/pull , 74166 74169 74175 74181 74182 74190 Logic Function Quadruple 2-line to 1-line Data Selector/Multiplexer


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PDF MSM60300, MSM60700, MSM61000 MSM61000 74169 SYNCHRONOUS 4-BIT BINARY COUNTER 74139 demultiplexer 3-8 decoder 74138 pin diagram 3-8 decoder 74138 CI 74151 pin diagram 41 multiplexer 74153 JK Shift Register 74195 Multiplexer 74153 bcd counter using j-k flip flop diagram CI 74138
IC 3-8 decoder 74138 pin diagram

Abstract: binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder full adder using Multiplexer IC 74151 ic 74151 MSI IC 74138 decoder ic 74148 block diagram
Text: macro code ttl CQDE 25 <0175> 74175 26 <0181> 74181 27 <0182> 74182 28 <0190> 74190 1 - D4 Q4 , /Vila are TTL level normal input buffers Vihb/Vilb are CMOS level normal input buffers Vmc/Vac are TTL , Min. Typ. Max, TTL level schmitt Trigger input threshold voltage VT+ - — 1,2 1.7 2.3 V VT- 0.8 , mm 1.0 1.5 2.0 ns 2ND (I: metal wiring length) 1.4 2.1 2.3 TTL level input buffer delay time , €” Type No. Function block name Logic function Max. No. of fan-outs Interface level TTL CMOS


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PDF MSM91H000 b72MS40 DQQ023b t-42-41 b724240 IC 3-8 decoder 74138 pin diagram binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder full adder using Multiplexer IC 74151 ic 74151 MSI IC 74138 decoder ic 74148 block diagram
IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Text: Support for TTL Macrofunctions Table 4. TTL Function Mappings in Altera-Provided LMFs (Part 1 o f 3 , Page 325 PLS-EDIF Data Sheet Table 4. TTL Function Mappings in Altera-Provided LMFs (Part 2 o , 74161 74162 74163 74164 74165 74166 74168 74169 74173 74174 74175 74181 74183 74190 74191 74192 74193 , . TTL Function Mappings in Altera-Provided LMFs (Part 3 o f 3) MAX+PLUS 74260 74261 74273 74279 74280


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74191, 74192, 74193 circuit diagram

Abstract: Truth Table 74161 IC 7402, 7404, 7408, 7432, 7400 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions 74191, 74192, 74193 counter 74168 truth table of ic 7495 A schematic diagram for the IC of 7411
Text: MAX+PLUSIITTL Macrofunction 74190 74191 74192 74193 74194 74195 74196 74197 74240 74241 74244 74251 74253 74257 , a NETED function to map. If no equivalent function currently exists in the MAX+PLUS II TTL , > Step 2: Design an equivalent circuit in AHDL if no equivalent function exists in the MAX+PLUS II TTL , relational operations. It is hierarchical, so that frequently used functions such as TTL and bus


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PDF HP400 QIC-24, 60-Mbytetape 74191, 74192, 74193 circuit diagram Truth Table 74161 IC 7402, 7404, 7408, 7432, 7400 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions 74191, 74192, 74193 counter 74168 truth table of ic 7495 A schematic diagram for the IC of 7411
sn 74373

Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor ic 74148 block diagram IC 74374
Text: app ed to corresp o n d in g prim itive and T T L functions in the M A X + P L U S II TTL M a croF u , libraries can be m app ed to corresp o n d in g prim itive and TTL functions in the M A X + P L U S 11 T T L , 74LS153 - MAX+PLUS il TTL Macrofunction 74147 74148 74151 74153 74154 74155 74156 74157 74158 74160 74161 74162 74163 74164 74165 74166 74169 74173 74174 74175 74181 74183 74190 74191 74192 74193 74194 , 74LS377 74LS379 74LS381 74LS390 74LS393 MAX+PLUS II TTL Macrofunction 74279 74280 74283 74290 74293


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truth table for ic 74138

Abstract: ALU IC 74183 16CUDSLR IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
Text: truth table C om plete sym bol library of basic gates and over 120 TTL m acro functions S u p p o rt for , includes basic logic gates and flipflops. The A+PLUS TTL M acroFunction Library has m ore than 120 TTLe q u , , 8FADD 7485, 74158, 74518, 8MCOMP 74184, 74185 7493, 74160, 74161, 74162, 74163, 74190 , 74191, 74393


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PDF 44-Mbyte, 386-based truth table for ic 74138 ALU IC 74183 16CUDSLR IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
priority encoder 74148

Abstract: priority encoder 74147 shift register 7495 msm7200 MSM7000 alu 74381 msm7500 74150 demultiplexer MSM72000 multiplexers 74 LS 150
Text: convert levels of both CMOS and TTL for all input/output buffers. Five types of master chips are prepared , • Macro functional block: 84 types ( TTL MSI equivalent) • All pins of schmitt input circuit are available. (Both CMOS and TTL levels are availa-ble.f • All pins of pull-up or pull-down resistance (120 , . of buffer cell Interface level Input buffer 1 BFIN Through input buffer 1 TTL 2 BFIC Through input buffer 1 CMOS 3 BCK Through clock input buffer 1 TTL 4 BCKN Invert clock input buffer 1 TTL


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PDF MSM70000 MSM71000, MSM72000, MSM71000 MSM74000] MSM75000] priority encoder 74148 priority encoder 74147 shift register 7495 msm7200 MSM7000 alu 74381 msm7500 74150 demultiplexer MSM72000 multiplexers 74 LS 150
asynchronous 4bit up down counter using jk flip flop

Abstract: counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu 7444 series Excess-3-gray code to Decimal decoder 74169 SYNCHRONOUS 4-BIT BINARY COUNTER counter 74169 MH 74151
Text: is able to convert levels of both CMOS and TTL for all input/output buffers. Ten types of master , €¢ Macro functional block: 84 types ( TTL MSI equivalent) • All pins of schmitt input circuit are available. (Both CMOS and TTL levels are available.) • All pins of pull-up or pull-down MOS (100 K , level Input buffer 1 BFIN Through input buffer 1 TTL 2 BFIC Through input buffer 1 CMOS 3 BCK Through clock input buffer 1 TTL 4 BCKN Invert clock input buffer 1 TTL 5 BST Invert schmitt trigger


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PDF MSM70V000 MSM70V000, asynchronous 4bit up down counter using jk flip flop counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu 7444 series Excess-3-gray code to Decimal decoder 74169 SYNCHRONOUS 4-BIT BINARY COUNTER counter 74169 MH 74151
74LS324

Abstract: 7400 TTL 74LS327 7402, 7404, 7408, 7432, 7400 80C96 74251 multiplexer 74LS324 equivalent 74C08 equivalent 74C923 equivalent Flip-Flop 7473
Text: (Complementary Metal Oxide Silicon) series are a pin-for-pln functional equivalent to the 7400 TTL family. They , Schottky, a type of TTL with a current and power reduction by a factor of 5 (compared to 7400 TTL ), and an , type of TTL . They have a schottky-barrier diode clamping on all normally saturated devices. 1-272 , equivalent to the 7400 TTL family. They have a wide power supply operating range, low power consumption, high , Abbreviation for Low Power Schottky, a type of TTL with a current and power reduction by a factor of 5


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PDF G0G513S 74C00 74H00 74LS00 74S00 74H01 74LS01 74C02 74LS02 74S02 74LS324 7400 TTL 74LS327 7402, 7404, 7408, 7432, 7400 80C96 74251 multiplexer 74LS324 equivalent 74C08 equivalent 74C923 equivalent Flip-Flop 7473
74139 for bcd to excess 3 code

Abstract: design a bcd counter using jk flip flop ttl 74118 priority encoder 74148 alu 74381 jk flip flop to d flip flop conversion 74541 buffer design excess 3 counter using 74161 two 3 to 8 decoders 74138 7444 series Excess-3-gray code to Decimal decoder
Text: convert levels of both CMOS and TTL for all input/output buffers. Ten types of master chips are prepared , : 31 types • I/O block: 57 types • Macro functional block: 84 types ( TTL MSI equivalent) • All pins of schmitt input circuit are available. (Both CMOS and TTL levels are available ) • All , Interface level Input buffer 1 BFIN Through input buffer 1 TTL 2 BFIC Through input buffer 1 CMOS 3 BCK Through clock input buffer 1 TTL 4 BCKN Invert clock input buffer 1 TTL 5 BST Invert schmitt


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PDF MSM70H000 MSM70H000, 74139 for bcd to excess 3 code design a bcd counter using jk flip flop ttl 74118 priority encoder 74148 alu 74381 jk flip flop to d flip flop conversion 74541 buffer design excess 3 counter using 74161 two 3 to 8 decoders 74138 7444 series Excess-3-gray code to Decimal decoder
counter 74168

Abstract: 3-8 decoder 74138 counter 74169 Multiplexer 74152 74183 adder 74381 alu 74169 binary counter 74175 flip flops 74151 8 by 1 Multiplexer flip flop 74379
Text: is able to convert levels of both CMOS and TTL for all input/output buffers. Ten types of master , functional block: 84 types ( TTL MSI equivalent) • All pins of schmitt input circuit are available. (Both CMOS and TTL levels are available.) • All pins of pull-up or pull-down MOS (100 Ki2) are available , buffer cell Interface level Input buffer 1 BFIN Through input buffer 1 TTL 2 BFIC Through input buffer 1 CMOS 3 BCK Through clock input buffer 1 TTL 4 BCKN Invert clock input buffer 1 TTL 5


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PDF MSM70V000 MSM70V000, counter 74168 3-8 decoder 74138 counter 74169 Multiplexer 74152 74183 adder 74381 alu 74169 binary counter 74175 flip flops 74151 8 by 1 Multiplexer flip flop 74379
ic 74226

Abstract: jk flip flop 74103 ic D flip flop 7474 7471 rs flip flop 4011 flip flop IC 7400 SERIES list 7414 NOT gate ic IC LA 74141 Ic ttl 7490, 7493, 7495 ci 74386
Text: N UM B ER OF GATES · TTL 7 4 0 0 SERIES TTL Part N o. 7400 7401 7402 7403 7404 7405 7406 7407 7408 , 45 6 5 8 7 7 6 6 6 9 8 8 16 15 14 20 15 14 20 14 20 17 80 27 57 80 73 12 19 320 TTL Part N o. 7490 , 74172 74173 74174 74175 74176 74177 74178 74179 74180 74181 74182 74183 74184 74185 74190 74191 G ate E , 100 100 80 76 TTL Part N o. 74192 74193 74194 74195 74196 74197 74198 74199 74225 74226 74245 74246


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PDF RP3G01 RP3G01 ic 74226 jk flip flop 74103 ic D flip flop 7474 7471 rs flip flop 4011 flip flop IC 7400 SERIES list 7414 NOT gate ic IC LA 74141 Ic ttl 7490, 7493, 7495 ci 74386
7408, 7404, 7486, 7432 use NAND gate

Abstract: JLCC-68 ci 74386 cI 74150 74153 full adder jLCC68 7402, 7404, 7408, 7432, 7400 74106 sln 7404 LCC-64
Text: 10.0 mA, available. Puli-up/pull-down input buffers available. Single 5V power supply. TTL , F-Macros are created and offered by Fujitsu to emulate the function of popular Industry-standard TTL , (F-Macros) which duplicate the function of many popular Industry-standard TTL devices and RAM macros which , Industry-standard TTL functions. They may be used In the design exactly the same as user macros. Designers's converting existing TTL designs to gate array will find the F-Macro a particularly useful Implementation


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PDF MB65XXXX MB66XXXX MB67XXXX MB65xxxx/MB66xxxx/MB67xxxx M865xxxx) MB67xxxx) MB66xxxx) 350AVB 540AVB 850AVB 7408, 7404, 7486, 7432 use NAND gate JLCC-68 ci 74386 cI 74150 74153 full adder jLCC68 7402, 7404, 7408, 7432, 7400 74106 sln 7404 LCC-64
up down counter using IC 7476

Abstract: 74154 shift register IC full adder using Multiplexer IC 74151 full adder circuit using ic 74153 multiplexer sk 7443 DN 74352 74183 adder full adder using ic 74138 pin function of ic 74390 function of latch ic 74138
Text: , available, Pull-up/pull-down Input buffers available. Single 5V power supply. TTL com patible I/O, CM O S , Industry-standard TTL devices. They are Identical In application to user macroa. Using F-Macros, a designer may , function of many popular Industry-standard TTL devices and RAM macros which provide from 1K to 2K of , 's F-Macros are direct software macro Implementations of popular Industry-standard TTL functions. They may be used In the design exactly the same as user macros. Designers's converting existing TTL designs to gate


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PDF 37417bH 0010S MB65XXXX MB66XXXX MB67XXXX MB65xxxx/MB66xxxx/MB67xxxx MB65xxxx) MB67xxxx) 350AVB S40AVB up down counter using IC 7476 74154 shift register IC full adder using Multiplexer IC 74151 full adder circuit using ic 74153 multiplexer sk 7443 DN 74352 74183 adder full adder using ic 74138 pin function of ic 74390 function of latch ic 74138
ttl 74191

Abstract: 74LS191M
Text: 54LS190, S N 5 4 L S 1 91 . . . J P A C K A G E SN 74190 , SN 74191 . . . N p a c k a g , (1 4 ) ABC(151 (1) (1 0 ) (9) 6 ,1 .4 _T ^ (131 (3 ) (2) qa TTL Devices 2-620 t C5 , ALLAS. TEXAS 7 5 2 6 5 621 TTL Devices D A TA SN54191, SN54LS191, SN74191 , ) '1 9 1 , 'L S 1 9 1 B I N A R Y C O U N T E R S TTL Devices P in n u m b e rs s h o w n are fo r , thirteen. i _ r > _ r IN P U T S _ r TTL Devices 2-62 4 _r ° A _ I r


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PDF SN54190, SN54191, SN54LS190, SN54LS191, SN74190, SN74191, SN74LS190, SN74LS191 54LS190, ttl 74191 74LS191M
counter 7468

Abstract: umi u26 "CMOS GATE ARRAY" fuji 74154 chip configuration 74181 74175 clock ci 7483 u26 umi CI 7408 74106 9 bit comparator using 7485
Text: 5V power supply. TTL compatible I/O, CMOS input and Schmitt trigger Input. Popular CAE , created and offered by Fujitsu to emulate the function of popular industry-standard TTL devices. They are , industry-standard TTL devices and RAM macros which provide from 1K to 2K of single-port static RAM on chip. Also , Industry-standard TTL functions. They may be used In the design exactly the same as user macros. Designers's converting existing TTL designs to gate array will find the F-Macro a particularly useful Implementation


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PDF MB65XXXX MB66XXXX MB67XXXX MB65xxxx/MB66xxxx/MB67xxxx MB65xxxx) MB67xxxx) MB66xxxx) J22833 CA95054-3197. D-6000 counter 7468 umi u26 "CMOS GATE ARRAY" fuji 74154 chip configuration 74181 74175 clock ci 7483 u26 umi CI 7408 74106 9 bit comparator using 7485
74ls82

Abstract: 74245 BIDIRECTIONAL BUFFER IC 74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC ic 7483 BCD adder Quad 2 input nand gate cd 4093 data sheet ic 74139
Text: €¢ TTL /CMOS and Schmitt trigger I/O compatibility • Slew-rate output buffers • High density Static , hardware platform for a multitude of high performance systems previously requiring TTL , Schottky TTL and , provide standard 1.5V and 3.5V input levels. TTL input buffers provide standard 0.8V and 2.0V input levels. Schmitt trigger input cells offer 1.2V of hysterisis for CMOS levels and 0.7V for TTL levels. More details , D 1.80 DRVTx Clock Driver with TTL Level Input Buffer U D 1.29 IBUFx CMOS Level Input Buffer N U D


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