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10484S8C Integrated Device Technology Inc SB-28, Tube
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trw 1048 Datasheets Context Search

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trw 1048

Abstract: trw1048 VlH24 Sample and Hold Amplifiers c 2579 power transistor
Text: Integrateli De vice Technology, Inc. CMOS FLASH A/D CONVERTER IDT75C48 FEATURES: 8-bit resolution 30 MSPS conversion rate Guaranteed no missing codes Pin- and function-compatible with TRW 1048 Low power consumption: 500mW Extended analog input range On-chip EDC (Error Detection and Correction) Improved output logie HIGH drive, no pull-up needed No sample and hold required Differentsai Phase < 1 Degree Diff-e rential Gain < 2% Selectable output formats TTL-compatible Availabfe in 28-pin CERDIP and


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PDF IDT75C48 500mW 28-pin MIL-STD-883, 75C48 16-II trw 1048 trw1048 VlH24 Sample and Hold Amplifiers c 2579 power transistor
trw1048

Abstract: trw 1048
Text: CMOS FLASH A/D CONVERTER FEATURES: · 8-bit resolution · 30 MSPS conversion rate · Guaranteed no missing codes · Pin- and function-compatible with TRW 1048 · Low power consumption: 500mW · Extended analog input range · On-chip EDC (Error Detection and Correction) · Improved output logic HIGH drive, no pull-up needed · No sample and hold required · Differential Phase < 1 Degree · Differential Gain < 2% · Selectable output formats · TTL-compatible · Available in 28-pin Plastic DIP, CERDIP and LCC · Military


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PDF 500mW 28-pin MIL-STD-883, 75C48 IDT75C48 trw1048 trw 1048
Not Available

Abstract: No abstract text available
Text: CMOS FLASH A/D CONVERTER Integrated Device Technology* Inc. IDT75C48 FEATURES: 8-bit resolution 30 MSPS conversion rate Guaranteed no missing codes Pin- and function-compatible with TRW 1048 Low power consumption: 500mW Extended analog input range On-chip EDC (Error Detection and Correction) Improved output logic HIGH drive, no pull-up needed No sample and hold required Differential Phase < 1 Degree Differential Gain < 2% Selectable output formats TTL-compatible Available in 28-pin CERDIP and LCC


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PDF IDT75C48 500mW 28-pin MIL-STD-883, IDT75C48
Not Available

Abstract: No abstract text available
Text: M ITSUBISHI SEMICONDUCTORS & s n sc*o^e 5 M5M4C1000P,J,L-10,-12,-15 -n 1048 5 7 6 -B IT ( 1048 576-W ORD BY 1 -B IT ) DYNAM IC RAM —Fast Page Mode— S E P , 16, 1986 , SEMICONDUCTORS M5M4C1000P,J,L-10,-12,-15 1048 5 7 6 -B IT (1 0 4 8 576-W ORD BY 1 -B IT )D Y N A M IC RAM , Remark Fast page mode id e n tic a l M ITSUBISHI SEMICONDUCTORS M5M4C1000P,J,L-10,-12,-15 1048 5 7 6 -B IT ( 1048 S76-WORD BY 1 -B IT )D Y N A M IC RAM ABSOLUTE MAXIMUM RATINGS Parameter


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PDF M5M4C1000P 576-word
Not Available

Abstract: No abstract text available
Text: FLEX­ IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS The Lattice pLSI 1048 is a High-Density , Interconnectivity The basic unit of logic on the pLSI 1048 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 ,.F7, (see figure 1). There are a total of 48 GLBs in the pLSI 1048 device. Each GLB has , pLSI 1048 device are selected using the Clock Distribution Network. Four dedicated clock pins (YO, Y1 , Network can also be driven from a special clock GLB (DO on the pLSI 1048 device). The logic of this GLB


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PDF pLS11048 1048-80LQ 120-Pin 1048-70LQ 1048-50LQ 1048-50LQI
238Q

Abstract: 7C371-66 7C371-83 CY7C371 CY7C372 FLASH370 319q CLCC 64 pins footprint
Text: . Max. Min. Max. Reset/Preset Parameters tRW Asynchronous Reset Width 10 12 15 20 ns tRR , ■r Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK " tRW " X X -tRcr zxxxx - *RR ' r , Pd = 928 mW. Add 15 mff per output for a total output Pd = 120 mW. Therefore, the total Pd = 1048 mW , commercial temperature range, for the PLCC: Tj = ( 1.048 W)(45°C/W) + 75"C = 122"C at 500 LFPM Tj = ( 1.048 W


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PDF CY7C371 32-Macrocell 100MHz 44-pin CY7C372 FLASH370 22V10 238Q 7C371-66 7C371-83 319q CLCC 64 pins footprint
Not Available

Abstract: No abstract text available
Text: reconfigurable systems. A functional superset of the ispLSI 1048 architecture, the ispLS11048E device adds two , > " u .6 6.5 7.5 13.5 15.0 15.0 th l tsu2 tco2 th2 tr1 trw l tptoeen tptoedis tgoeen tgoedis twh , .) fmax (Ext.) fmax (Tog.) tsul tcol thl tsu2 tco2 th2 tr1 trw l tptoeen tptoedis tgoeen tgoedis twh twl


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PDF 1048C 16-bit
ACT1020

Abstract: CY7C384-1GI CY7C383-1JC 48 pin clcc footprint 7c383 O443 CY7C383-1GC CLCC 64 pins footprint CY7C384 CLK503
Text: tcwi.o Clock LOW Time 3.6 3.6 3.6 3.6 3.6 ns tsw Set Width 2.1 2.1 2.1 2.1 2.1 ns tRW Reset Width 1.9 1.9 , – •set tRW ■tRESET X Output Delay OUTPUT t0UTLH toUTHL 4-284 CYPRESS SEMICONDUCTOR bSE D 256^2 , . Therefore, the total Pd = 1048 mW. For a PLCC, 8ja = 45°C/W at 500 LFPM, and ©ja = 64'CAV for still air , Ta and Ta = 75'C worst-case commercial temperature range, for the PLCC: Tj = ( 1.048 W)(45°C/W) + 75"C = 122"C at 500 LFPM Tj = ( 1.048 W)(64°C/W) + 75'C = 142°C in still air This calculation is for


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PDF CY7C383 CY7C384 84-pin 16-bit T-90-20 ACT1020 CY7C384-1GI CY7C383-1JC 48 pin clcc footprint 7c383 O443 CY7C383-1GC CLCC 64 pins footprint CLK503
1048-50LQ

Abstract: I1048 S9089 isplsi device layout
Text: Semiconductor Corporation Features Lattice ispLSI and pLSI 1048 High-Density Programmable , T he ispLSI and pLSI 1048 are H igh-D ensity Program m able Logic D evices w hich contain 288 , is a rchitecturally and pa ra m e trica lly com patible to the pLSI 1048 device, but m ultiplexes , ispLSI and pLSI 1048 d evices is the G eneric Logic B lock (GLB). T he G LB s are labeled A0, A1 . F7 (see figure 1). T here are a total of 48 G LBs in the ispLSI and pLSI 1048 devices. Each G LB has 18


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PDF 1048-80LQ 1048-70LQ 1048-50LQ 1048-50LQ 120-Pin I1048 S9089 isplsi device layout
ORP10

Abstract: No abstract text available
Text: 1048 is a High-Density I 'rogi^mihabte Logic Device which contains 288 Regis ters, 9(5JJnjyersal I/O , total ol 48 GLBs in the pLSI 1048 /883 device. Each GLB has 18 inputs, a pro grammable AND/OR/XOR array , Specifications pLSf 1048 /883 T-4 6 -19-07 GND to 3.0V S3ns 10% to 90% 1.5V 1.5V See Figure 2 Figure 2 , u l to o l th1 tsu2 tco2 th2 trl trw l ten tdis twh twl tsu5 th5 1. 2. 3. 4. 5. UNITS 24 ns ns , pLSl 1048 883 Tim ing Model GRP Feedback I Pod. In #26 I/O Reg Bypass 4 PT Bypass #33 D


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PDF MIL-STD-883 pLS11048 pLS11048/883 G0S443 T-46-19-07 132-Pin r130t pLS11048-50LG/883 ORP10
Not Available

Abstract: No abstract text available
Text: Instruments Incorporated c 181 Dynamic R A M Modules TM4Z56FC1. TM4257FC1 1.048 ,576 BY 1 BIT , tW C S *CW L fRW L l CA H l RAH *AR t DH *DHR l DH fRCH tRRH tW CH *W CR tp c tPCM tRC *WC tRW C *CP , interval tRW D *REF l RCD 30 60 ns 120 4 ns ms Dynamic R A M Modules Continued next , Write-command hold time after C A S low W rite-command hold time after *W CS *CW L tRW L l CA H *RAH *AR *DH *DHR *DH tRCH *RRH tW CH *W CR tp c *PCM *RC (W C tRW C *CP *CPN *C A S tRP *RA S tW P *T XA S C l A SR


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PDF TM4256FC1, TM4257FC1 22-Pin FC1-20
Not Available

Abstract: No abstract text available
Text: ' 1048 High-Density Programmable Logic Functional Block Diagram - tpd = 15 ns Propagation Delay - , |^ Ì% f j| y ia tfo rm s - PC: steMijfppPlatfc Î Description }LSl%nd pLSI 1048 are High-Density , to the pLSI 1048 device, but multiplexes four of the dedicated input pins to control in-system programming. The basic unit of logic on the ispLSI and pLSI 1048 devices is the Generic Logic Block (GL.B). , 1048 devices. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be


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PDF 0212-B0B-ssp1048 pLS11048 1048-50LQI 1048-50LQI 120-Pin -48-iap
Not Available

Abstract: No abstract text available
Text: 1048 /883 in-system programmable Large Scale Integration High-Oensity Programmable Logic - - F ^ d 'r , » and parametrically compatible to the pLSI 1048 /883 de - Synchronous and Asynchronous docks vice, but , are labeled A0, A1 . F7 (see figure 1). There are a total of 48 GLBs in the ispLSI 1048 /883 device , trw l ten tdls twh twl tsu5 th5 1. 2. 3. 4. 5. T-46-19-07 -50 MIN. MAX. 24 ns :ji s v'i; % 30.7 , C O N D U C T O R SSE D GGGEMfiti 223 LAT Lattice ispLSI 1048 883 Timing Model


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PDF MIL-STD-883 ispLS11048 ispLS11048/883 132-Pln 132-Pin ispLS11048-50LG/883
Not Available

Abstract: No abstract text available
Text: pLSÌ 1048 Lattice programmable Large Scale Integration High-Density Programmable Logic , Description The Lattice pLSI 1048 is a High-Density Programmable Logic Device which contains 288 Registers , Interconnectivity The basic unit of logic on the pLSI 1048 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 ,.F7, (see figure 1). There are a total of 48 GLBs in the pLSI 1048 device. Each GLB has , and the output drivers can source 4 mA or sink 8 mA. Clocks in the pLSI 1048 device are selected


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PDF pLS11048 pLS11048 1048-80LQ 120-Pin 1048-70LQ 1048-50LQ 1048-50LQI
ispLS11048

Abstract: 548-5N
Text: ispLSI 1048 In-System Programmable High Density PLD Functional Block Diagram Description The i|g L , Pool (GRP). The GRP [§Wides complete interconnectivity between all of these elements. The ispLSI 1048 , universal I/O cells by the ORP. The ispLSI 1048 device contains six of these Megablocks. The GRP has as , tc o l th1 tsu2 tco2 th2 tr1 trw l ten tdis twh tw l tsu5 th5 1. 2. 3. 4. DESCRIPTION1 Data , Specifications ispLS11048 ispLSI 1048 Tim ing Model I/O Cell GRP Feedback GLB ORP I/O Ceil ^


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PDF -48-isp ispLS11048 0212-80B isp1048 1048-80LQ 1048-70LG 1048-50LQÏ 120-Pin Q04lA-48-isp ispLS11048 548-5N
Not Available

Abstract: No abstract text available
Text: Lattice ispLSr 1048 in-system programmable Large Scale Integration High-Density Programmable , Interconnectivity The basic unit of logic on the ispLSI 1048 device is the Generic Logic Block (GLB). The GLBs , . Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1048 device , driven from a special clock GLB (DO on the ispLSI 1048 device). The logic of this GLB allows the user to , universal I/O cells by the ORP. The ispLSI 1048 device contains six of these Megablocks. 2 3/93. Rev


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PDF ispLS11048 1048-80LQ 120-Pin 1048-70LQ 1048-50LQ
Not Available

Abstract: No abstract text available
Text: isp L si 1048 I a t t ir p H I U w in-system programmable Large Scale Integration , input pins to control in-system pro­ gramming. The basic unit of logic on the ispLSI 1048 device is , compatible voltages and the output drivers can source 4 mA or sink 8 mA. Clocks in the ispLSI 1048 device , driven from a special clock GLB (DO on the ispLSI 1048 device). The logic of this GLB allows the user to , 1 12 Ext. Reset Pin to Output Delay - 17 - 17 - 22.7 ns trw l - 13


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PDF ispLS11048 ispLS11048 1048-80LQ 120-Pin 1048-70LQ 1048-50LQ 1048-50LQI
Not Available

Abstract: No abstract text available
Text: p L S r 1048 programmable Large Scale Integration Features J Functional Block Diagram , and Timing Simulation — PC and Workstation Platforms Description The Lattice pLSI 1048 is a , complete interconnectivity between all of these elements. The basic unit of logic on the pLSI 1048 device , igure 1. p L S 1 1048 rararara 01 90 8 9 66 rarav ora 87 66 85 64 ra ra ra ra 63 8 2 61 8 0 , GRP have been equalized to minimize timing skew and logic glitching. Clocks in the pLSI 1048 device


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PDF PLDs83 pLS11048 120-Pin
Not Available

Abstract: No abstract text available
Text: Specifications ispLSI and pLS11048 Lattice ispLSI and pLSI 1048 ;Semiconductor I , €” Optimized Global Routing Pool Provides Global Interconnectivity The ispLSI and pLSI 1048 are , truly reconfigurable systems. It is architecturally and parametrically compatible to the pLSI 1048 , unit of logic on the ispLSI and pLSI 1048 devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 . F7 (see figure 1). There are a total of 48 GLBs in the ispLSI and pLSI 1048 devices


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PDF pLS11048 pLS11048 1048-80LQ 120-Pin 1048-70LQ 1048-50LQ pLS11048-80LQ
Not Available

Abstract: No abstract text available
Text: lattice semiconductor LiflE D Lattice Features pLSI and ispLSI' 1048 High-Density , ®][c2|c3]|c4]^5][c6]|c7 | Output Routing Pool Description The Lattice pLSI and ispLSI 1048 are , architecturally and parametrically compatible to the pLSI 1048 device, but multiplexes four of the dedicated input pins to control in-system programming. The basic unit of logic on the pLSI and ispLSI 1048 , total of 48 GLBs in the pLSI and ispLSI 1048 devices. Each GLB has 18 inputs, a programmable AND/OR


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PDF 0212-80B-isp1043 ispLS11048 1048-80LQ 120-Pin 1048-70LQ 1048-50LQ
238Q

Abstract: 7C372-66 CY7C371 CY7C372 FLASH370 logic block diagram of cypress flash 370 device cypress FLASH370 device CY10E301 CLCC 64 pins footprint
Text: Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK ' tRW " X " tRO " x - tRR - Asynchronous Preset INPUT , Pd = 928 mW. Add 15 mff per output for a total output Pd = 120 mW. Therefore, the total Pd = 1048 mW , commercial temperature range, for the PLCC: Tj = ( 1.048 W)(45°C/W) + 75"C = 122"C at 500 LFPM Tj = ( 1.048 W


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PDF 0010514b CY7C372 64-Macrocell 100MHz 44-pin CY7C371 FLASH370 CY7C372is 238Q 7C372-66 logic block diagram of cypress flash 370 device cypress FLASH370 device CY10E301 CLCC 64 pins footprint
Not Available

Abstract: No abstract text available
Text: üiLattice ispLSI and pLSI 1048 i!:iic o r p o ° a n tfon’0r High-Density , €” PC and Workstation Platforms Description The ispLSI and pLSI 1048 are High-Density Program , architecturally and parametrically compatible to the pLSI 1048 device, but multiplexes four of the dedicated input pins to control in-system programming. The basic unit of logic on the ispLSI and pLSI 1048 , total of 48 GLBs in the ispLSI and pLSI 1048 devices. Each GLB has 18 inputs, a programmable AND/OR


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PDF 0212-8Q 1048-80LQ 120-Pin 1048-70LQ 1048-50LQ
Not Available

Abstract: No abstract text available
Text: superset of the ispLSI 1048 architecture, the ispLS11048E device adds two new global output enable pins , - 0.0 - tr1 A 12 Ext. R e set Pin to O u tp u t D elay trw l - 13 Ext , trw l - 13 Ext. R e set Pulse Duration tp to e e n B 14 tp to e d is C 15 , d (ns) ORDERING NUMBER PACKAGE 125 7.5 ispLS I 1048 E -12 5LQ 128-P in PQ FP 125 7.5 ispLS I 1048 E -12 5LT 128-P in T Q F P 100 10 ispLS I 1048 E -10 0LQ 128


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PDF 1048E 1048C 128-P 1048E -70LQ
TDC1002

Abstract: TDC1005B9A TDC1001 TDC1006 TDC1005 PIN-13DSB 1005B9A TMC3220 TMC2011 TDC1011
Text: Drawing, T[;=-55°C to 125°C. 2 TRW LSI Products Inc. TDC1005 Serial Shift Register Dual 64-Bit The TRW TDC1005 is a dual 64-bit positive-edge-triggered serial shift register which operates at 25MHz , (¡4 °A ®A TRW LSI Products Inc. P.O. Box 2472 La Jolla, CA 92038 Phone: (6191 457-1000 FAX: (619) 455-6314 © TRW Inc. 1990 40G00275 Rev. G-11/90 Printed in the U.S.A. TDC1005 TRvV Functional , 15 14 13 dsa 12 d1a 11 d0a 10 clk a 9 clk c 16 Pin CERDIP - B9 Package 4 TRW LSI Products Inc


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PDF TDC1005 TDC1006 TDC1011 3-18x8 21-36x4 TMC2011 TNIC2111 1-16x8 TDC1002 TDC1005B9A TDC1001 PIN-13DSB 1005B9A TMC3220
75008

Abstract: TRW POWER trw diode
Text: ■OPTEK TECHNOLOGY Optoelectronics Division TRW Electronic Components Group Product Bulletin , TRW Optoelectronics Division's infrared emitting diode chips are fabricated by solution epitaxial , centered at 935 nanometers. Since TRW has no control over the techniques the customer may use to alloy end bond chips, TRW cennot be held responsible for damage to the chips resulting from such techniques. Nor can TRW warrant the life or any other parameter after the chips have been bonded. Absolute Maximum


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PDF 0PC123 850i30 ClAl-930 75008 TRW POWER trw diode
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