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TSW3003EVM Texas Instruments TSW3003EVM-RF Transmit Chain Demonstration Kit
LM96550SQE/NOPB Texas Instruments Ultrasound Transmit Pulser 80-WQFN 0 to 70
LM96550SQ/NOPB Texas Instruments Ultrasound Transmit Pulser 80-WQFN 0 to 70
DS25BR120TSDX/NOPB Texas Instruments 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis 8-WSON -40 to 85
DS25BR120TSD/NOPB Texas Instruments 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis 8-WSON -40 to 85
GC5325IZND Texas Instruments Wideband Digital Predistortion Transmit Processor 352-BGA -40 to 85

transmit g1 Datasheets Context Search

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Not Available

Abstract: No abstract text available
Text: via the transmit G1 and third Z2 bytes. The transmit G1 -byte (bits 1 - 4 ) contains the number of B3 , indicated by setting bits 1— of the transmit G1 -byte to 1001. A path remote-defect 4 indication (PR D I , enabled via the control register. A PRDI is indicated by setting bits 5 and 6 of the transmit G1 byte as , Decoupling • Access to Receive and Transmit Transport-Overhead (TOH) and Path-Overhead (POH) Bytes , (i.e., a reassembly device). On the transmit side, complete ATM cells are scrambled and placed in a


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PDF TNETA1600 08-MBIT/S 52-MBIT/S SDNS036
2003 - STS-48

Abstract: TSOT1610GPD mars10g T-PRO
Text: with provisionable BER. Optionally inserts path REI in the transmit G1 byte based on receive B3 , transmit (add) interface consists of one input port. The maximum bandwidth of the transmit signals is 10 , Path processing: - Full receive1 and transmit path processing for any valid2 mix of STS-1 and , will not require the backplane interface3): - The MARS10G T-Pro system transmit (add) interface consists of four input ports which can operate simultaneously. The system transmit data path includes 4:1


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PDF MARS10G TSOT1610GP /MARS10G TSOT1610GPD) STS-192/STM-64 STS-192/STM-64/STS-48/STM-16) STS-12. PB03-036SONT STS-48 TSOT1610GPD mars10g T-PRO
2003 - TSOT1605GP6

Abstract: D2488 STS-48 TDCS6440G TSOT1605GP6D
Text: provisionable BER. Optionally inserts path REI in the transmit G1 byte based on receive B3 errors. Extracts , transmit (add) interface consists of one input port. The bandwidth of the transmit signals is 5 Gbits/s , receive1 and transmit path processing for any valid2 mix of STS-1 and concatenated payloads from STS-3c to , backplane interface3): - The MARS5G T-Pro16 system transmit (add) interface consists of four input ports which can operate simultaneously. The system transmit data path includes 4:1 selection function which


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PDF T-Pro16 TSOT1605GP6 TD-Pro16 TSOT1605GP6D) STS-48/STM-16 TD-Pro16 STS-48/STM-16) T-Pro16 STS-12; STS-12s D2488 STS-48 TDCS6440G TSOT1605GP6D
2003 - STS-48

Abstract: TDCS6440G TSOT1605GP8 TSOT1605GP8D
Text: provisionable BER. Optionally inserts path REI in the transmit G1 byte based on receive B3 errors. Extracts , transmit (add) interface consists of one input port. The bandwidth of the transmit signals is 5 Gbits/s , interfaces operating at 2.5 GHz (T-Pro8). Path processing: - Full receive1 and transmit path processing , T-Pro8 system transmit (add) interface consists of four input ports which can operate simultaneously. The system transmit data path includes 4:1 selection function which can select input data at STS


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PDF TSOT1605GP8 TSOT1605GP8D) STS-48/STM-16 STS-48/STM-16) STS-12; STS-12s STS-48) PB03-107SONT STS-48 TDCS6440G TSOT1605GP8D
1996 - transmit g1

Abstract: STM 1 5A2 TD15 TNETA1600 TNETA1610 TNETA1611 TNETA151 ATM 38E
Text: far-end block-error (path FEBEs and line FEBEs) counts via the transmit G1 and third Z2 bytes. The , indicated by setting bits 5 and 6 of the transmit G1 byte as shown below. G1 BIT 5 G1 BIT 6 DEFECT , Decoupling Access to Receive and Transmit Transport-Overhead (TOH) and Path-Overhead (POH) Bytes Through , device). On the transmit side, complete ATM cells are scrambled and placed in a SONET/SDH synchronous , Transmit RAM J1 RD0 ­ RD15 RXSOC RXCLAV RCKI RRE D0 ­ D7 A0 ­ A10 RD/WR SEL LOPC IFPRGM


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PDF TNETA1600 08-MBIT/S 52-MBIT/S SDNS036 transmit g1 STM 1 5A2 TD15 TNETA1600 TNETA1610 TNETA1611 TNETA151 ATM 38E
2003 - STS-48

Abstract: TDCS6440G TSOT162G5P6 TSOT162G5P6D D2488 MARS2G5 1724P A2488
Text: transmit G1 byte based on receive B3 errors. Extracts and counts path REI (provisionable on a bit or , transmit (add) interface consists of one input port. The maximum bandwidth of the selected transmit , transmit path processing for any valid2 mix of STS-1 and concatenated payloads from STS-3c to STS , not require the backplane interface3): - The MARS2G5 T-Pro16 system transmit (add) interface consists of four input ports which can operate simultaneously. The system transmit data path includes 4:1


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PDF T-Pro16 TSOT162G5P6 TD-Pro16 TSOT162G5P6D) STS-48/STM-16 TD-Pro16 STS-48/STM-16) T-Pro16 STS-12; STS-12s STS-48 TDCS6440G TSOT162G5P6D D2488 MARS2G5 1724P A2488
2003 - TSOT1610GP6D

Abstract: TSOT1610GP6 STS-48 transmit g1
Text: transmit G1 byte based on receive B3 errors. Extracts and counts path REI (provisionable on a bit or , transmit (add) interface consists of one input port. The bandwidth of the selected transmit signals is , interfaces operating at 2.5 GHz (T-Pro16). Path processing: - Full receive1 and transmit path processing , T-Pro16 system transmit (add) interface consists of four input ports which can operate simultaneously. The system transmit data path includes 4:1 selection function which can select input data at STS


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PDF MARS10G T-Pro16 TSOT1610GP6 /MARS10G TD-Pro16 TSOT1610GP6D) STS-192/STM-64 TD-Pro16 STS-192/STM-64/STS-48/STM-16) TSOT1610GP6D STS-48 transmit g1
2003 - TSOT1610G

Abstract: transmit g1 MARS10G dfrm MARS10G T-UNI STS-48 TSOT1610GD
Text: Provides signal fail detection with provisionable BER. Optionally inserts path REI in the transmit G1 , contraclocked STS-192/STM-64/STS-48/STM-16). - The MARS10G TD-Uni system transmit (add) interface consists of one input port. The maximum bandwidth of the transmit signals is 10 Gbits/s: One 1 × 16/4 × 4 @ , interfaces operating at 2.5 GHz (T-Uni). Path processing: - Full receive1 and transmit path processing for , transmit (add) interface consists of five input ports which can operate simultaneously. The system


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PDF MARS10G TSOT1610G) TSOT1610GD) STS-192/STM-64 STS-192/STM-64/STS-48/STM-16) STS-192/STM-64/STS PB03-041SONT TSOT1610G transmit g1 dfrm MARS10G T-UNI STS-48 TSOT1610GD
2007 - 0x1758

Abstract: AU-AIS GR-253-CORE XRT94L33 XRT94L33IB ST VIPER application notes 0x11B3 574 91 256
Text: C2 Byte Value Register 0x00 Reserved 0x00 Transmit AU-4 Mapper/VC-4 Path ­ Transmit G1 , Transmit TUG-3/AU-3 Mapper VC-3 Path ­ Transmit G1 Byte Value Register 0x00 0xN984 ­ 0xN8992 0xN993 , transmit blocks allow flexible insertion of TOH and POH bytes through both Hardware and Software , level 2P for Packets · E3 and DS3 framers for both Transmit and Receive directions The SONET , 0x0383 20 0 Rev2.0.0 200 Reserved 0x00 Transmit Line Interface Control Register 0x00


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PDF XRT94L33 XRT94L33 0x1758 AU-AIS GR-253-CORE XRT94L33IB ST VIPER application notes 0x11B3 574 91 256
TS12864

Abstract: No abstract text available
Text: interface - G.751 receive and transmit performance monitoring (frame alignment, distant alarm indication) · , LINE SIDE Transmit Nibble or Byte Data Add B us^ 1 J L4M Level 4 Mapper TXC-03456 L- Transmit Clock In / » Receive Nibble or Byte Data Receive Clock Out Receive Clock In Drop B u s f , . .7 Transmit Line Interface Timing , . .27 Transmit Overhead Comm Channel T im in g


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PDF TXC-03456 TXC-03456-MB TS12864
1995 - transmit g1

Abstract: EDV54-120-31 751 sage
Text: interface - G.751 receive and transmit performance monitoring (frame alignment, distant alarm indication , Interface Port µP I/O LINE SIDE Transmit Nibble or Byte Data Add Bus L4M Transmit Clock , . 7 Transmit Line Interface Timing , . 27 Transmit Overhead Comm Channel Timing , . 28 Transmit Path Overhead Interface Timing


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PDF TXC-03456 TXC-03456-MB transmit g1 EDV54-120-31 751 sage
2000 - uPC1256

Abstract: EDV54-120-31 TXC-03456AIPQ
Text: interface - G.751 receive and transmit performance monitoring (frame alignment, distant alarm indication , Interface Control Port µP I/O LINE SIDE Transmit Nibble or Byte Data Add Bus L4M Level 4 Mapper Drop Bus TXC-03456 Transmit Clock In Receive Nibble or Byte Data Receive Clock Out , . 7 Transmit Line Interface Timing , . 27 Transmit Overhead Comm Channel Timing


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PDF TXC-03456 TXC-03456-MB uPC1256 EDV54-120-31 TXC-03456AIPQ
1995 - transmit g1

Abstract: No abstract text available
Text: .751 receive and transmit performance monitoring (frame alignment, distant alarm indication) · SDH/SONET bus , Transmit Nibble or Byte Data Add Bus L4M Level 4 Mapper TXC-03456 Transmit Clock In Receive Nibble , . 7 Transmit Line Interface Timing , . 27 Transmit Overhead Comm Channel Timing , . 28 Transmit Path Overhead Interface Timing


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PDF TXC-03456 TXC-03456-MB transmit g1
2007 - GI 312 diode

Abstract: VIPER IC TTB-10 XRT94L33IB XRT94L33 XRT94L31 GR-253-CORE SF 119 D sf 118 d 0x1718
Text: STS-3c Path ­ Transmit G1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path ­ , C2 Byte Value Register 0x00 Reserved 0x00 Transmit SONET Path ­ Transmit G1 Byte Value , SONET/SDH transmit blocks allow flexible insertion of TOH and POH bytes through both Hardware and , interface for ATM or level 2P for Packets · E3 and DS3 framers for both Transmit and Receive , 10 0 Rev1.0.0 100 Reserved 0x00 Transmit Line Interface Control Register 0x00


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PDF XRT94L31 XRT94L33 XRT94L33 GI 312 diode VIPER IC TTB-10 XRT94L33IB XRT94L31 GR-253-CORE SF 119 D sf 118 d 0x1718
2007 - LED VIPER

Abstract: VIPER IC AU-AIS GI 312 diode transistor st 431 VIPer Design Software viper 504 SF 119 D sf 118 d 574 91 256
Text: 0x00 Transmit AU-4 Mapper/VC-4 Path ­ Transmit G1 Byte Value Register 0x00 Reserved 0x00 , -3 Path ­ Transmit G1 Byte Value Register 0x00 0xN984 ­ 0xN8992 0xN993 0xN994 ­ 0xN995 0xN998 , · E3 and DS3 framers for both Transmit and Receive directions · Complete Transport , clock reference for its operation. The SONET/SDH transmit blocks allow flexible insertion of TOH and , .0.0 100 Reserved 0x00 Transmit Line Interface Control Register 0x00 RECEIVE STM-1 SOH


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PDF XRT94L31 XRT94L31 LED VIPER VIPER IC AU-AIS GI 312 diode transistor st 431 VIPer Design Software viper 504 SF 119 D sf 118 d 574 91 256
2007 - GR-253-CORE

Abstract: XRT94L33 XRT94L33IB led cross reference 0x0106 0x1950 574 91 256 Sts.1
Text: STS-3c Path ­ Transmit G1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path ­ , C2 Byte Value Register 0x00 Reserved 0x00 Transmit SONET Path ­ Transmit G1 Byte Value , transmit blocks allow flexible insertion of TOH and POH bytes through both Hardware and Software , level 2P for Packets · E3 and DS3 framers for both Transmit and Receive directions The SONET , REG STERS 0x0310 ­ 0x0382 0x0383 20 0 Rev2.0.0 200 Reserved 0x00 Transmit Line


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PDF XRT94L33 XRT94L33 GR-253-CORE XRT94L33IB led cross reference 0x0106 0x1950 574 91 256 Sts.1
pten

Abstract: multiplexers 74 LS 150 ts6566
Text: .751 receive and transmit pertormance monitoring (trame alignment, distant alarm indication) · SDH/SONET bus , Bus ^ y~ L4M Level 4 Mapper + Transmit Clock In Receive Nibble or Byte Data -> Receive Clock , ents Transmit Nibble or Byte Data contain Inform ation P R E L I M IN A R Y TABLE OF C , I PERFORMANCE I I MONITORING I TRANSMIT FRAME ALIGNMENT DETECTOR TRANSMIT AIS DETECTOR MOTOROLA , microprocessor, and can generate an interrupt and a 140 Mbit/s AIS when enabled. The 140 Mbit/s transmit line


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PDF TXC-03456 TXC-03456-M pten multiplexers 74 LS 150 ts6566
2001 - CX28250-23

Abstract: CX28250-26 GR-253-CORE RS8250 cx8250
Text: /RDI-P code will be inserted into the Transmit G1 /K2 byte for a period of at least 20 frames. The , 1-12 1.3.3 Transmit Values for Z01 and Z02 Now Under Software Control . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . 1-17 1.3.10 Transmit Clock Control Bits Redefined . . . . . . , Interrupts/ G1 Latching (-26 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 , (-26 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.3.18 SONET Transmit


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PDF CX28250 RS8250-16 CX28250-23/-26 00386A CX28250-23 CX28250 RS8250 CX28250-26 GR-253-CORE cx8250
Not Available

Abstract: No abstract text available
Text: €¢ Nibble or byte 139.264 Mbit/s line interface - G.751 receive and transmit performance monitoring (frame , . APPLICATIONS • Broadband switching systems ^P I/O LINE SIDE i l Transmit Nibble or Byte Data ~h L4M Transmit Clock In Level 4 Mapper Receive Nibble or Byte Data + TXC , . 7 Transmit Line Interface Timing , .27 Transmit Overhead Comm Channel Timing


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PDF TXC-03456 DM220 TXC-03456-MB
1999 - bip 109

Abstract: 78P7200 CN8223 CN8223EPF
Text: , formatting, and transmit priority controls Idle cells generated and screened Statistics counts latched on , Transmit Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Transmit Framing Overhead Interface . . . . , . . . . . . . . . 2-19 2.4.1 2.4.2 2.4.3 2.5 Internally Framed Transmit Line Interface . . , Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Internally Framed


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PDF CN8223 CN8223 TR-TSV-000772, TR-TSV-000773, TR-NWT-000253, T1S1/92-185; bip 109 78P7200 CN8223EPF
1999 - BT8222KPF

Abstract: atm header error checking 78P7200 CN8223 CN8223EPF e3 frame formatter
Text: ATM and SMDS cell modes 4 FIFO ports with header screening, formatting, and transmit priority , . . . . . . . . . . . . . . . . . 2-22 Transmit Parallel Interface . . . . . . . . . . . . . . . . , . 2-15 Transmit Framing Overhead Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 2.4.3 2.5 Internally Framed Transmit Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.1.1 High-Speed PECL Transmit Interface . . . . . . . . . . . . .


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PDF CN8223 CN8223 TR-TSV-000772, TR-TSV-000773, TR-NWT-000253, T1S1/92-185; BT8222KPF atm header error checking 78P7200 CN8223EPF e3 frame formatter
1999 - N8222

Abstract: 28-22-21 bt8222
Text: ports with header screening, formatting, and transmit priority controls Idle cells generated and , . . . . . . . . . . . . . . . . . . . . . . 2-3 Internally Framed Transmit Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.1.1 High-Speed PECL Transmit , 2.4 2.4.1 2.4.2 2.4.3 2.5 2.5.1 2.5.2 2.5.3 2.6 2.6.1 Externally Framed Transmit Line Interface . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Transmit Framing Overhead


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PDF Bt8222 Bt8222 TR-TSV-000772, TR-TSV-000773, TR-NWT-000253, T1S1/92-185; N8222 28-22-21
1999 - n8223

Abstract: N-822 CN8223EPF AD6116 78P7200 CN8223 BT8222EPFE PROCESS CONTROL TIMER using 555 ic
Text: ATM and SMDS cell modes 4 FIFO ports with header screening, formatting, and transmit priority , Generation for Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . 2-26 2.6.1.2 Cell Generation Status and Status Interrupts for Transmit . . . . , Generation for Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 , . . . . . . . . . . . . . . . . . . 2-33 PLCP Transmit /Receive Synchronization . . . . . . . . . .


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PDF CN8223 CN8223 TR-TSV-000772, TR-TSV-000773, TR-NWT-000253, T1S1/92-185; n8223 N-822 CN8223EPF AD6116 78P7200 BT8222EPFE PROCESS CONTROL TIMER using 555 ic
2000 - lcd power board schematic APS 254

Abstract: hecs 50 G1M2 TPS16
Text: . 97 Transmit G1 Byte REI and RDI Insertion , Programmable error mask · C2 byte · Transmit selected value (e.g., microprocessor or POH interface) · G1 byte · , - Cell filtering (GFC, PTI and CLP fields) - Four-cell receive and transmit FIFOs (programmable-depth transmit FIFO) - Rate adaptation using idle or unassigned cells - HEC generator · PPP (IP packets , CRC-16 or CRC-32 detection/generation - CRC pass-through option - 256-byte receive and transmit FIFOs


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PDF TXC-06203 CRC-16 CRC-32 TXC-06203-MB lcd power board schematic APS 254 hecs 50 G1M2 TPS16
2001 - GFP 73 A

Abstract: MPC860 RDB PCF8594C-2 NM24C02U MPC860 HDMP-3001 GR-253-CORE CRC-32 AT24C04 tt 2194
Text: 24 3.9.1 Transmit SONET/SDH Processing Overview . 24 3.9.2 Receive SONET/SDH Processing Overview . 25 3.9.3 Transmit SONET/SDH Processing Details , SONET/SDH Transmit Registers . 56 5.4 SONET/SDH Receive Registers . 61 5.5 Ethernet Transmit , . . 112 8.4 Line Interface Receive and Transmit Timing . 112 8.5 TOH


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PDF HDMP-3001 HDMP-3001 5988-3853EN GFP 73 A MPC860 RDB PCF8594C-2 NM24C02U MPC860 GR-253-CORE CRC-32 AT24C04 tt 2194
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