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Part Manufacturer Description Datasheet Download Buy Part
LM3S5R31-IBA80-C3 Texas Instruments Stellaris Microcontroller 103-NFBGA
AD-1377-103-CRIMP-LOCATOR (994855-000) TE Connectivity (994855-000) AD-1377-103-CRIMP-LOCATOR
1017-103-0200 TE Connectivity Ltd 1017-103-0200
AA-400-103-LOW-FLOW-TIP TE Connectivity Ltd AA-400-103-LOW-FLOW-TIP
2157538-1 TE Connectivity Ltd SHELL 103,F SERIES,12 POS,PCB PINS
PIC16C765-I/JW Microchip Technology Inc 8-BIT, UVPROM, 24 MHz, RISC MICROCONTROLLER, CDIP40, 0.600 INCH, WINDOWED, MO-103, CERDIP-40

tods 103 Datasheets Context Search

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1998 - tods 103

Abstract: MSC1230
Text: tCSS 2 ms CS CLOCK-CS tCSH 2 ms CS- tODS CI=100pF 8 , tCSW CS tODS tODS tR tR 80% 20% SEG1~37 GRID1~3 2SEGGRID VDD1, 2, 3 tPCS , : 1 Bit 112 111 110 109 108 107 106 105 104 103 102 101 100 99 M0 xx xx xx xx xx 10 9 8 7


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PDF J2C0024-27-Y3 MSC1230 MSC1230 1111/3DutyUniversal MSC12301/31/3 MSC123011211110 MSC1230CSDATA-INCLOCK3 818V5V -30mA 56QFP tods 103
tods 103

Abstract: MSC1230 D102D101
Text: tCSS 2 ms CS CLOCK-CS tCSH 2 ms CS- tODS CI=100pF 8 , tCSW CS tODS tODS tR tR 80% 20% SEG1~37 GRID1~3 2SEGGRID VDD1, 2, 3 tPCS , : 1 Bit 112 111 110 109 108 107 106 105 104 103 102 101 100 99 M0 xx xx xx xx xx 10 9 8 7


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PDF J2C0024-27-Y3 MSC1230 MSC1230 1111/3DutyUniversal MSC12301/31/3 MSC123011211110 MSC1230CSDATA-INCLOCK3 818V5V -30mA 56QFP tods 103 D102D101
1998 - MSC1230

Abstract: OKI D51 vfd circuit diagram 2.7 kw DIGITAL VFD CLOCK IC d92 97 diode 42 pin microprocessor VFD drive MSC1230GS-2K SEG22 SEG23 12 pin 7 segment display pin configuration
Text: tCSH - 2 - ms CS-All Data Output Delay tODS CI=100 pF - 8 ms Slew , VALID tDH 3.8V 0.8V 3.8V 0.8V VALID Figure 1. Data Input Timing tCSW CS tODS tODS tR tR 3.8V 0.8V 80% 20% SEG1-37 GRID1-3 Figure 2. SEG or GRID Driver Output , 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 G2 111 110 109 108 107 106 105 104 103 102 101 100 , (MSB) 108 xx 107 xx 106 105 10 9 MSB 104 8 103 7 102 6 101 5 100 4


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PDF E2C0024-27-Y4 MSC1230 111-Bit MSC1230 112-bit 10-bit OKI D51 vfd circuit diagram 2.7 kw DIGITAL VFD CLOCK IC d92 97 diode 42 pin microprocessor VFD drive MSC1230GS-2K SEG22 SEG23 12 pin 7 segment display pin configuration
1998 - 210K6

Abstract: LSI37PWM3 tods 103
Text: fc tcw tDS tDH tCSW tCSL tRCSW tRCSL tCSS tCSH tPD tODS tR CL100pF CL100pF t20% to 80 , VDD tPCS tRCSW tRCSL 3.8V CS 0.8V 3 8/21 MSC1215xx l tCSW CS 3.8V 0.8V tODS tR SEG1~17 GRID1, 2 80% 20% tODS tR 4 SEGGRID 1 fFR 4096 bit times GRID1 16 bit times min GRID2 2032 , 1.56 1.46 1.37 1.27 1.17 1.12 1.07 1.03 0.98 0.93 0.88 0.83 0.78 0.73 0.68 0.63 0.000 Pulse Step


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PDF J2C002227Y2 MSC1215-xx MSC1215xx MSC1215xx1/2BiCMOS LSI37PWM3 VDD818V 42DIP DIP42P6002 MSC1215xxRS 210K6 tods 103
2000 - cr 4180 r4

Abstract: FJDL1215 MSC1215 210K6 tods 103 VDD818V
Text: 1 ms tODS CL100pF 8 ms tR CL100pF t20% to 80% or 80% to 20% of VDD , 3 8/22 FJDL1215-03 MSC1215-01 l tCSW CS 3.8V 0.8V tODS tODS tR SEG1~17 , 1.03 17 69.53 3.71 40 44.92 0.98 18 68.36 3.52 41 43.75 0.93 19 , /2048 1.27 2.744 24/2048 1.17 2.692 23/2048 1.12 2.650 22/2048 1.07 2.622 21/2048 1.03


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PDF FJDL1215-03 MSC1215-01 MSC1215-01 MSC1215-011/2BiCMOS LSI37PWM3 VDD818V 42DIP DIP42-P-600-2 MSC1215-01RS cr 4180 r4 FJDL1215 MSC1215 210K6 tods 103
2000 - FJDL1215

Abstract: MSC1215 cr 4180 r4
Text: 1 ms tODS CL100pF 8 ms tR CL100pF t20% to 80% or 80% to 20% of VDD , 3 8/22 FJDL1215-03 MSC1215-01 l tCSW CS 3.8V 0.8V tODS tODS tR SEG1~17 , 1.03 17 69.53 3.71 40 44.92 0.98 18 68.36 3.52 41 43.75 0.93 19 , /2048 1.27 2.744 24/2048 1.17 2.692 23/2048 1.12 2.650 22/2048 1.07 2.622 21/2048 1.03


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PDF FJDL1215-03 MSC1215-01 MSC1215-01 MSC1215-011/2BiCMOS LSI37PWM3 VDD818V 42DIP DIP42-P-600-2 MSC1215-01RS FJDL1215 MSC1215 cr 4180 r4
1998 - Not Available

Abstract: No abstract text available
Text: SEG,GRID fOSC fOSCI fFR fPWM fC tCW tDS tDH tCSW tCSL tCSS tCSH tPD tODS tR R4.7kW,C10pF , tODS SEG1~30 GRID1, 2 tR tODS tR 80% 20% 4 12/25 MSC1200xx/MSC1200Vxx l n l , 1.27 1.17 1.12 1.07 1.03 0.98 0.93 0.88 0.83 0.78 0.73 0.68 0.63 Threshold Voltage 3.000 2.950 2.900


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PDF J2C001627Y3 MSC1200-xx/MSC1200V-xx MSC1200xx/MSC1200Vxx MSC1200xx, MSC1200Vxx1/2BiCMOS64 MSC1200VxxCSDATA 11BIT 32PLA) MSC1200xx
2000 - 3525 PWM

Abstract: FJDL1200V MSC1200
Text: 1 ms SEG,GRID tODS C1100pF 8 ms tR C1100pF t20%80% or 80%20% 5 , tODS SEG1~30 GRID1, 2 tR tODS tR 80% 20% 4 12/26 FJDL1200V-03 MSC1200 , /2048 1.07 9 21/2048 1.03 8 20/2048 0.98 7 19/2048 0.93 6 18/2048


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PDF FJDL1200V-03 MSC1200-01/MSC1200V-01 MSC1200-01/MSC1200V-01 MSC1200-01, MSC1200V-011/2BiCMOS64 MSC1200V-01CSDATA 11BIT MSC1200-01 3525 PWM FJDL1200V MSC1200
2000 - MSC1215

Abstract: dip42 VFD MSM1215-01RS 2032b
Text: 1 ms SEG & GRID Outputs Delay Time from CS tODS CL=100 pF - 8 ms tR CL , tRCSL 3.8 V 0.8 V Figure 3. Power-on-Reset Timing tCSW CS 3.8 V 0.8 V tODS tODS tR , 3.91 39 45.70 1.03 17 69.53 3.71 40 44.92 0.98 18 68.36 3.52 41 , 3.980 11 23/2048 1.12 3.914 10 22/2048 1.07 3.831 9 21/2048 1.03 3.766 8 20/2048 0.98


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PDF FEDL1215-03 MSC1215-01 MSC1215-01 37-bit MSC1215 dip42 VFD MSM1215-01RS 2032b
CXD1244

Abstract: OCXX CXD1244S
Text: tlLRS tlLRH tWOB tODS tODH tWOB tODS tODH tWOB tODS tODH tWOB tODS tODH tR, tF CXD1244S Symbol , tODS 7 DATAO >-V d o / 2 ' 1i LRCKO Vdo/ 2 SONY. tw is r CXD1244S Item


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PDF CXD1244S within-100dB CXD1244S CXD1244 OCXX
2000 - FJDL1200V

Abstract: MSC1200 3525 PWM
Text: 1 ms SEG,GRID tODS C1100pF 8 ms tR C1100pF t20%80% or 80%20% 5 , tODS SEG1~30 GRID1, 2 tR tODS tR 80% 20% 4 12/26 FJDL1200V-03 MSC1200 , /2048 1.07 9 21/2048 1.03 8 20/2048 0.98 7 19/2048 0.93 6 18/2048


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PDF FJDL1200V-03 MSC1200-01/MSC1200V-01 MSC1200-01/MSC1200V-01 MSC1200-01, MSC1200V-011/2BiCMOS64 MSC1200V-01CSDATA 11BIT MSC1200-01 FJDL1200V MSC1200 3525 PWM
1998 - DIGITAL VFD CLOCK IC

Abstract: vfd circuit diagram 2.7 kw OKI D51 tods 103 MSC1230 MSC1230GS-2K SEG22 SEG23
Text: tCSH - 2 - ms CS-All Data Output Delay tODS CI=100 pF - 8 ms Slew , VALID tDH 3.8V 0.8V 3.8V 0.8V VALID Figure 1. Data Input Timing tCSW CS tODS tODS tR tR 3.8V 0.8V 80% 20% SEG1-37 GRID1-3 Figure 2. SEG or GRID Driver Output , 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 G2 111 110 109 108 107 106 105 104 103 102 101 100 , (MSB) 108 xx 107 xx 106 105 10 9 MSB 104 8 103 7 102 6 101 5 100 4


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PDF MSC1230 QFP56-P-910-0 65-2K DIGITAL VFD CLOCK IC vfd circuit diagram 2.7 kw OKI D51 tods 103 MSC1230 MSC1230GS-2K SEG22 SEG23
CXD1144BP

Abstract: CXD1144 sony dsp CXD11448P sony CXD1144 sony CXD Over Sampling Digital Filter LSI
Text: mode 8Fs, BCK24 CL = 25pF BCKOCL = 50pF 40 ns Output data set up time tODS 25 ns Output data , = 50pF 60 ns Output data set up time tODS 35 ns Output data hold time tODH 35 ns Output , data set up time tODS 20 ns Output data hold time tODH 20 ns Output BCK pulse width tWOB fx = 18.5MHz laS output mode 8Fs, CL = 25pF BCKOCL = 50pF 60 ns Output data set up time tODS 32 ns


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PDF CXD1144BP CXD1144BP 120dB 293rd) 20kHz) 150kHz) 50MIL) 50MIL CXD1144 sony dsp CXD11448P sony CXD1144 sony CXD Over Sampling Digital Filter LSI
CXD1244

Abstract: CXD1244S 40P12 sony format 02AA
Text: width tWOB Fx=16.9MHz t2S output mode 8Fs. CL=50pF 60 ns Output data set up time tODS 35 , 8Fs. BCK24 CL=50pF 40 ns Output data set up time tODS 20 ns Output data hold time tODH , data set up time tODS 32 ns Output data hold time tODH 32 ns Output signal Rise/Fall , Output BCKO VDOX0.9^ VdoxO.1 DATAO tR —- -t Vdd/2 twos toDS Vdo/2 J\_ toDH twoe toos LRCKO


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PDF CXD1244S CXD1244S -100dB SD1P-40P-121 CXD1244 40P12 sony format 02AA
1998 - 12v schematic of fluorescent lamps

Abstract: dip42 VFD 42 pin display driver Fluorescent display tube
Text: Outputs Delay Time from CS tODS CL=100 pF - 8 ms tR CL=100 pF t=20% to 80% or 80 , 3.8 V 0.8 V tODS tODS tR SEG1-17 GRID1, 2 tR 80% 20% Figure 4. SEG and GRID Output , 22/2048 1.07 35 92/2048 4.49 9 21/2048 1.03 34 88/2048 4.30 8 20


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PDF E2C0022-27-Y3 MSC1215-xx MSC1215-xx 37-bit DIP42-P-600-2 12v schematic of fluorescent lamps dip42 VFD 42 pin display driver Fluorescent display tube
CXD1144

Abstract: CXD1144BP Over Sampling Digital Filter LSI
Text: Output data hold time Output signal rise/fall time Symbol fx fecK tW IB tlDS tlDH tlLRS tlLRH tWOB tODS tOOH tWOB tODS tODH tWOB tODS tODH tWOB tODS tODH tR , tF CXD1144BP Condition Min. 12.0 Typ


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PDF CXD1144BP 120dB 293rd) 20kHz) 150kHz) CXD1144BP CXD1144 Over Sampling Digital Filter LSI
1999 - MWS5101AEL3

Abstract: MWS5101 MWS5101ELS MWS5101EL2 MWS5101DL3X MWS5101AEL3X CDP1822 MWS5101AEL2 MWS5101ADL3 MWS5101A
Text: - - 0 - - ns Output Disable Setup tODS 110 - - 150 - - ns , SELECT 2 tCS2H tCS2S OUTPUT DISABLE (NOTE) tODS tDS DI1-DI4 tDH DATA IN STABLE tWRW READ/WRITE tAS DON'T CARE NOTE: tODS is required for common I/O operation only; for


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PDF MWS5101, MWS5101A 256-Word MWS5101 MWS5101A MWS5101AEL3 MWS5101ELS MWS5101EL2 MWS5101DL3X MWS5101AEL3X CDP1822 MWS5101AEL2 MWS5101ADL3
CXD1144

Abstract: CXD11448P
Text: R S tlLRH tW OB tODS tODH tW OB tODS tODH tW OB tODS tODH tW O B tODS tODH tR , tF fx = 16.9MHz


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PDF CXD1144BP CXD1144BP 120dB 293rd) 20kHz) XD1144BP CXD1144 CXD11448P
1999 - cdp1822

Abstract: CD4000 CDP1802 CDP1822CD3
Text: Output Disable Setup tODS 5 140 - 225 - ns PARAMETER Write Pulse Width (Note 1 , CHIP-SELECT 2 tCSS2 OUTPUT DISABLE tCS2H (NOTE 1) tODS tDIS tDIH DATA IN STABLE DI1 - DI4 tWRW READ/WRITE tAS DON'T CARE NOTE 1 NOTE: 1. tODS is required for common I/O operation


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PDF CDP1822C/3 256-Word CDP1822C/3 CDP1822 CDP1802 CD4000 CDP1822CD3
1998 - MSC1201

Abstract: QFP44 SEG22 SEG23
Text: 2 ms DATA CLOCK-DATA tPD 1 ms tODS CL100pF 8 ms tR , 3.8V - 0.8V CS tODS tR tODS tR - 80% - 20% SEG1~30 GRID1, 2 3 SEGGRID 8/18


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PDF J2C0017-27-Y3 MSC1201-xx MSC1201-xx 60PWM MSC1201-xx1/2BiCMOS64 MSC1201-xxCSDATACLOCK3 GRID12 IOH-30mA 11BIT 30PLA MSC1201 QFP44 SEG22 SEG23
1997 - CD4000

Abstract: CDP1802 CDP1822 CDP1822CD3
Text: 280 - ns Output Disable Setup tODS 5 140 - 225 - ns PARAMETER , CHIP-SELECT 1 CHIP-SELECT 2 tCSS2 OUTPUT DISABLE tCS2H (NOTE 1) tODS tDIS tDIH DATA IN STABLE DI1 - DI4 tWRW READ/WRITE tAS DON'T CARE NOTE 1 NOTE: 1. tODS is required for


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PDF CDP1822C/3 256-Word CDP1822C/3 CDP1822 CDP1802 CD4000 125oC CDP1822CD3
D4859

Abstract: MSC1201 QFP44 SEG22 SEG23 CSM0
Text: 2 ms DATA CLOCK-DATA tPD 1 ms tODS CL100pF 8 ms tR , 3.8V - 0.8V CS tODS tR tODS tR - 80% - 20% SEG1~30 GRID1, 2 3 SEGGRID 8/18


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PDF J2C0017-27-Y3 MSC1201-xx MSC1201-xx 60PWM MSC1201-xx1/2BiCMOS64 MSC1201-xxCSDATACLOCK3 GRID12 IOH-30mA 11BIT 30PLA D4859 MSC1201 QFP44 SEG22 SEG23 CSM0
cxa1244

Abstract: No abstract text available
Text: Output data set up time tODS Output data hold time tODH Output BCK pulse width tWOB Output data set up time tODS Output data hold time tODH Output BCK pulse width tWOB Output data set up time tODS Output data hold time tODH Output signal Rise/Fall time tR


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PDF CXD1244S CXD1244S -100dB cxa1244
1998 - MSC1218

Abstract: OKI D51 7 segment digital display D54 REGULATOR MSC1218GS-K SSOP32-P-430-1 OKI D51 a
Text: - ms tODS CI=100pF - 8 ms tR CI=100pF t=20% to 80% or 80% to 20% - , DATA-IN 2) VALID VALID VALID tCSW SEG1-21, GRID1-3 tR -3.8V -0.8V tODS tR , tODS VDD -3.8V -0.8V tCW tDH CS 3) -3.8V -0.8V tPOF -80%VDD -0.0V -3.8V


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PDF E2C0023-27-Y3 MSC1218 63-Bit MSC1218 64-bit 10-bit 21-segment OKI D51 7 segment digital display D54 REGULATOR MSC1218GS-K SSOP32-P-430-1 OKI D51 a
1998 - SEG23

Abstract: 3525 PWM analog dimming circuit 7 segment display duplex led type
Text: SEG & GRID Output Delay from CS tODS CI = 100pF - 8 ms Slew Rate (All Drivers , CS 3.8V 0.8V tODS tODS tR SEG1-30 GRID1, 2 tR 80% 20% Figure 4 SEG & GRID , 3.340 9 21/2048 1.03 3.305 8 20/2048 0.98 3.270 7 19/2048 0.93 3.240 6 18/2048 0.88


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PDF E2C0016-27-Y4 MSC1200-xx/1200V-xx 30-Bit MSC1200-xx/1200V-xx 64-bit QFP56-P-910-0 65-2K SEG23 3525 PWM analog dimming circuit 7 segment display duplex led type
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